Digital System Design (EE005-3.5-3) : Individual Assignment Report

Digital System Design
(EE005-3.5-3)
INDIVIDUAL ASSIGNMENT REPORT
Name : Arunachalam Balaji

Student ID : TP019324
Intake : UC3F1101TE
Due Date : 19 MAY 2011
Lecturer : Mr. Chandrasekharan Natraj
Digital System Design (EE005-3.5-3)
Introduction to ALU
Arithmetic Logic Unit, which is shortly known as “ALU”, is the very important part of a
computer that performs all arithmetic and logic operations, such as addition and
multiplication, and all comparison operations as well. The ALU is one of the major
component, which is present in the CPU (central processing unit). In certain processors, the
ALU is grouped into two units, an arithmetic unit (AU) and a logic unit (LU). Some
processors might have multiple AU some for the fixed point operations and some of the
floating point operations.
Normally, the ALU has direct input and output access to the processor controller, main
memory and input/output devices. Inputs and outputs flow along an electronic path which is
called a “bus”. The input consists of an instruction word which is called a machine instruction
word that contains an operation code which is called an "op code" and one or more operands.
The operation code will tell the ALU what operation to perform and the operands are used in
the specified operation.
The arithmetic logic unit can perform integer arithmetic operations like addition subtraction,
division and multiplication. It can also perform bitwise logic operations like AND, OR, XOR
and NOR. Besides that, ALU also performs bit-shifting operations which mean shifting or
rotating a word by a required number of bits either to the left or right. These Shifts can be
seen either as multiplications and divisions by a power factor of two.
http://simple.wikipedia.org/wiki/File:ALU_symbol.svg
Arunachalam Balaji (TP019324)

A typical Schematic Symbol of the ALU
Introduction to VHDL
VHDL is an acronym for Very High Speed Integrated Circuits Hardware Description
Language. This programming language is used to model a digital system or mixed signal
system such as Field Programmable Gate Arrays (FGPA) and Integrated Circuits (IC).
It is used to describe the behaviour as well as structure of electronic systems, but its main
purpose is to describe the structure and behaviour of digital electronic designs, such as ASICs
and FPGAs as well as other conventional digital circuits and systems. VHDL has an
international standard, regulated by the IEEE board. Simulation and synthesis are the two
important tools which run and operate on the VHDL language. VHDL can be used to describe
hardware at the gate level as well as behavioural.
VHDL is normally used to write text models that describe a logic circuit or electronic device.
Such kind of model is processed by a synthesis program, only if it is part of the logic design.
Later part, a simulation program is used to test the logic design using simulation models to
represent the logic circuits that interface to the design. This type of simulation models is
commonly called a “test bench” program.
VHDL offers various advantages to the designers such as:
 Standardised language and instantly available tool.

 Powerful and versatile hardware description language.
 Multiple mechanisms and tools to support the design hierarchy.
 Versatile design reconfiguration support.
 Support of multiple levels of abstraction.

Objectives of the study
Main objective
The main objective of this assignment is to design and implement a 4-bit combinational
Arithmetic and Logic Unit (ALU) by using VHDL language and simulate the operations of
ALU with the help of a simulator.
Specific objectives
The other objectives of this assignment are :
 Design a VHDL code for the type of ALU specified.

 Synthesize a net list of the design.
 Create a test bench suite and fully test the ALU
 Test the hardware description of ALU by using MODELSIM Software.

The Required ALU Functions & Operations
ALU Operations:
Opcode Operation Description
000 LES OUTPUT <= A << B
001 GRA OUTPUT <= A >> B
010 ADD OUTPUT <= A + B
011 SUB OUTPUT <= A – B
100 AND OUTPUT <= A and B
101 NOR OUTPUT <= A nor B
110 OR OUTPUT <= A or B
111 XOR OUTPUT <= A xor B
Operation:
The ALU Opcode determines the operation of the ALU that it should perform with the two
operands namely A and B.
ALU Block diagram:
Opcode (2 downto 0)
Input A (3 downto 0)
Output (3 downto 0)
Input B (3 downto 0)

Logical OR Function
The OR gate performs logical addition, more widely known as OR function. In this OR gate
two or more inputs are present. When all inputs are low (0) then only output is low (0),
otherwise the output will be high (1).
TRUTH TABLE FOR OR GATE
INPUTS OUTPUT
A B C
0 0 0
0 1 1
1 0 1
1 1 1
Logic Diagram :
Waveform Output :

VHDL Program For OR Function
-- 1 Bit OR Gate program

library ieee;
use ieee.std_logic_1164.all;
entity or1 is
port (A,B : in std_logic; Z : out std_logic);
end or1;
architecture behave of or1 is
begin
Z<= A or B;
end behave ;
-- Main Program (4-bit OR Gate Program)

library ieee;
entity or4bit is
port(A,B :in std_logic_vector (4 downto 1) ;
Z :out std_logic_vector (4 downto 1));
end or4bit;
architecture behave of or4bit is
component or1
port (A,B: in std_logic ; Z :out std_logic);
end component;
begin
or11:or1 port map (A(1),B(1),Z(1));
end behave;

Logical Exclusive OR Function (XOR) :
This type of logical XOR is called inequality comparator or detector because it produces the
output only when the two inputs are different. In this design two or more inputs are used.
When number of high (1) inputs is even then the output is low (0), otherwise the output is
high(1).
TRUTH TABLE FOR XOR

GATE
INPUTS OUTPUT
A B C
0 0 0
0 1 1
1 0 1
1 1 0
Logical Design :
Waveform Output :

VHDL Program For XOR Function
--XOR Program (1-bit)

library ieee;
entity xor1 is
port(A,B : in std_logic; z :out std_logic);
end xor1;
architecture behave of xor1 is
begin
z<= A xor B;
end behave;
--Main Program (4-bit XOR gate)

library ieee;
entity xor4bit is
port (A,B: in std_logic_vector(3 downto 0);
z: out std_logic_vector(3 downto 0));
end xor4bit;
architecture behave of xor4bit is
component xor1
port (A,B :in std_logic; Z :out std_logic);
end component;
begin
xor10: xor1 port map (A(0),B(0),Z(0));
end behave;

Compliment OR Function (NOR) :
This is opposite function of OR gate. In this NOR gate two or more inputs are used. When all
inputs are low (0) then only output will be high (1), otherwise the output will be low (0).
TRUTH TABLE FOR NOR

GATE
INPUTS OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Logic Design :
Waveform Output :

VHDL Program For NOR Function
--NOR Program (1-bit)

library ieee;
use ieee.std_logic_1164.ALL;
entity nor1 is
port(A,B : in std_logic; Z :out std_logic);
end nor1;
architecture behave of nor1 is
begin
z<= not (A or B);
end behave;
--Main Program (4-bit NOR Gate)

library ieee;
entity nor4bit is
port (A,B: in std_logic_vector (3 downto 0);
Z: out std_logic_vector (3 downto 0));
end nor4bit;
architecture behave of nor4bit is
component nor1
port (A,B :in std_logic; Z :out std_logic);
end component;
begin
nor10: nor1 port map (A(0),B(0),Z(0));
end behave;

Logical AND Function :
The typical AND gate performs the logical multiplication function, more widely known as
AND function. In this gate two or more inputs are used. When all inputs are high (1) then
only output will be high (1), otherwise the output will be low (0).
TRUTH TABLE FOR AND

GATE
INPUTS OUTPUT
A B C
0 0 0
0 1 0
1 0 0
1 1 1
Logical Design :
Waveform Output :

VHDL Program For AND Function
--And Program (1-Bit)

library ieee;
entity and1 is
port (A,B : in std_logic; Z : out std_logic);
end and1;
architecture behave of and1 is
begin
Z<= A and B;
end behave ;
-- Main Program (4-bit AND Gate)

library ieee;
entity and4bit is
port(A,B :in std_logic_vector(3 downto 0) ;
z :out std_logic_vector(3 downto 0));
end and4bit;
architecture behave of and4bit is
component and1
port (A,B: in std_logic ; z :out std_logic);
end component;
begin
and10 :and1 port map (A(0),B(0),Z(0));
end behave;

Adder Function
A logic circuit that can add four bits, three bits to be added and a CARRY bit from the lower
bit order which results in a SUM and a CARRY.
TRUTH TABLE FOR ADDER
INPUTS OUTPUTS
A B C_IN SUM C_OUT

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Fourbit Full Adder Design :
Logical Equation For Full Adder :
.

VHDL Program For ADDER
--Full Adder Program (1-Bit)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FA is
port
( A,B, Cin : IN std_logic;
Sum, Cout : OUT std_logic);
End FA;
architecture Behave of FA is
signal p, q, r : bit;
Begin
Sum <= A xor B xor Cin;
Cout <= ((A xor B) and Cin) or (A and B);
End behave;

--MAIN PROGRAM (4-Bit Full Adder)

library IEEE;
entity FA4 is
port(A, B : IN std_logic_vector (3 downto 0);
Cin : IN std_logic;
Z : OUT std_logic_vector (3 downto 0);
Cout : OUT std_logic);
End FA4;
architecture structure of FA4 is
Component FA
port
( A,B, Cin : IN std_logic;
Sum, Cout : OUT std_logic);
End component;
Signal Sum0, Sum1, Sum2, C1, C2, C3 : std_logic;
Begin
FA0: FA port map (A(0), B(0), Cin, Z(0), C1);
FA1: FA port map (A(1), B(1), C1, Z(1), C2);
FA2: FA port map (A(2), B(2), C2, Z(2), C3);
FA3: FA port map (A(3), B(3), C3, Z(3), Cout);
End structure;

SUBTRACTOR:-
A logic circuit that can subtract four bits, one bit is to be subtracted from another and a
BORROW bit which is denoted by Bin from the previous bit order which results in a output
Difference, denoted by D and a BORROW OUT, denoted by Bout.
TRUTH TABLE FOR SUBTRACTOR
INPUTS OUTPUTS
A B B_IN D B_OUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
DESIGN:
Logic equations Of Subtractor:

VHDL Program For Subtractor
--Full Subtractor Program (1-Bit)

library ieee;
entity FS1 is
port (A,B,Bin : in std_logic ; Z,Bout : out std_logic);
end FS1;
Architecture behave of FS1 is
begin
Z <= A xor B xor Bin;
Bout <= ((not(A xor B)) and Bin) or (A and (not (B)));
end behave;
--Main Program (4-Bit Full Subtractor)

library ieee;
entity fourbitsubtractor is
port( A,B:in std_logic_vector (3 downto 0);
Bin: in std_logic;
Bout: out std_logic;
Z:out std_logic_vector (3 downto 0));
end fourbitsubtractor;
Architecture structure of fourbitsubtractor is
component FS1
port (A,B,Bin :in std_logic ; Z,Bout:out std_logic);
end component;
signal S1,S2,S3 :std_logic;
begin
FS10 :FS1 port map (A(0),B(0),Bin,Z(0),S1);
FS11 :FS1 port map (A(1),B(2),S1,Z(1),S2);
FS12 :FS1 port map (A(2),B(2),S2,Z(2),S3);
FS13 :FS1 port map (A(3),B(3),S3,Z(3),Bout);
end structure;

MULTIPLEXERS
Multiplexer or more commonly known as MUX or even called as data selector is a logic
circuit that accepts multiple data inputs and allows only one of them at a time to get through
the output. In this circuit select lines are used and the output depends on it. If n is the number
of select lines then inputs are 2^n.
MULTIPLEXER 8 TO 1
TRUTH TABLE:—
INPUTS SELECT OUTPUT
A B C D E F G H S S S MUX_OUT
2 1 0
0 1 0 1 0 1 0 1 0 0 0 0
0 1 0 1 0 1 0 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 0
0 1 0 1 0 1 0 1 0 1 1 1
0 1 0 1 0 1 0 1 1 0 0 0
0 1 0 1 0 1 0 1 1 0 1 1
0 1 0 1 0 1 0 1 1 1 0 0
0 1 0 1 0 1 0 1 1 1 1 1
8 : 1 MUX Design :

VHDL Program For Multiplexer
--MUX Program
library IEEE;
entity sel is
port
(Op : in std_logic_vector(2 downto 0);
M : out std_logic;
T : out std_logic_vector(3 downto 0) );
end sel;
architecture Behave of sel is
signal I: std_logic;
Signal L: std_logic_vector (3 downto 0);
begin
po: process (Op) is
begin
case Op (2 downto 0) is
when "000" =>
M <= I;
when "001" =>
M <= I;
when "010" =>
T <= L;
when "011" =>
T <= L;
when "100" =>
T <= L;
when "101" =>
T <= L;
when "110" =>
T <= L;
when "111" =>
T <= L;
when others =>
null;
end case;
end process po;
end behave;

ARITHMETIC & LOGIC UNIT

ALU is an acronym for Arithmetic and Logic Unit. This unit performs various
mathematical(addition, subtraction etc.) operations and logical operations(AND,OR,XOR
etc.). in addition to these operations it also takes complements of a number, it compares two
numbers, rotates the bits of number from left to right, shifts the bits of a number left or right,
increments or decrements a number.
ALU Operations:
Opcode Operation Description
000 LES OUTPUT <= A << B
001 GRA OUTPUT <= A >> B
010 ADD OUTPUT <= A + B
011 SUB OUTPUT <= A - B
100 AND OUTPUT <= A and B
101 NOR OUTPUT <= A nor B
110 OR OUTPUT <= A or B
111 XOR OUTPUT <= A xor B
ALU Block diagram:
Opcode (2 downto 0)
Input A (3 downto 0)
Output (3 downto 0)
Input B (3 downto 0)
VHDL Program For ALU

--Main ALU Program With 8:1 MUX

library IEEE;
entity ALU_VHDL is
port
(A, B : in std_logic_vector(3 downto 0);
Op : in std_logic_vector(2 downto 0);
T : out std_logic_vector(3 downto 0));
end ALU_VHDL;
architecture structure of ALU_VHDL is
component LES--Calling Less program
port
(A, B : in std_logic_vector (3 downto 0);
Z: out std_logic);
End component;
component gra--Calling Greater Program
port (A, B : in std_logic_vector (3 downto 0);
Z: out std_logic);
End component;
component FA4--Calling full adder program
port (A, B : IN std_logic_vector (3 downto 0);
Cin : IN std_logic;
Z : OUT std_logic_vector (3 downto 0);
Cout : OUT std_logic);
End component;
component fourbitsubtractor--Calling Subtractor program
port (A, B : IN std_logic_vector (3 downto 0);
Bin : IN std_logic;
Z: OUT std_logic_vector (3 downto 0);
Bout : OUT std_logic);
End component;
component and4bit--Calling AND program
Z: out std_logic_vector (3 downto 0));

End component;
component nor4bit--Calling NOR program
Z : out std_logic_vector (3 downto 0) );
End component;
component or4bit--Calling OR program
End component;
component xor4bit--Calling XOR program
End component;
component sel--Calling MUX program
port(Op : in std_logic_vector(2 downto 0);
M : out std_logic;
end component;
signal I: std_logic;
Signal L: std_logic_vector (3 downto 0);
Begin
m: LES port map (A, B, I);
n: GRA port map (A, B, I);
o: FA4 port map (A, B, I, L);
e: fourbitsubtractor port map (A, B, I, L);
f: and4bit port map (A, B, L);
g: nor4bit port map (A, B, L);
h: or4bit port map (A, B, L);
j: xor4bit port map (A, B, L);
s: sel port map (Op, I, T);
end structure;

VHDL Coding For Test Bench For ALU
--Test Bench Program For ALU

library IEEE;
entity TEST is
End TEST;
architecture TBA of TEST is
component ALU_VHDL
port
( A, B : in std_logic_vector(3 downto 0);
Op : in std_logic_vector(2 downto 0);
End component;
Signal Awire, Bwire, Zwire: std_logic_vector (3 downto 0);
Signal Opwire : std_logic_vector (2 downto 0);
Begin
mk : ALU_VHDL port map (Awire, Bwire, Opwire, Zwire);
p0: Process
Begin
Awire <= "0000" after 10 ns;
End Process;
p1: Process
Begin
Bwire <= "1111" after 10 ns;
End Process;

P2: Process
Begin
Opwire <= "000" after 10 ns;
End process;
End TBA;

VHDL Coding For Less Function
--Program To Implement Less Than

library IEEE;
entity les is
port
(
A, B : in std_logic_vector (3 downto 0);
Z: out std_logic
);
End les;
architecture Behave of les is
signal
p, q, r, u, v, w, x, y : std_logic;
Begin
p <= A(3) xor B(3);
q <= A(2) xor B(2);
r <= A(1) xor B(1);
u <= (not (A(3))) and B(3);
v <= (not (A(2))) and B(2) and p;
x <= (not (A(1))) and B(1) and p and q;
y <= (not (A(0))) and B(0) and p and q and r;
Z <= u or v or x or y;
end behave;

VHDL Coding For Greater Function
--Program To Implement Greater Than

library IEEE;
entity gra is
port(A, B: in std_logic_vector (3 downto 0);Z: out std_logic);
End gra;
architecture Behave of gra is
signal
p, q, r, u, v, w, x, y : std_logic;
Begin
P <= A(3) xor B(3);
q <= A(2) xor B(2);
r <= A(1) xor B(1);
u <= (not (B(3))) and A(3);
v <= (not (B(2))) and A(2) and p;
x <= (not (B(1))) and A(1) and p and q;
y <= (not (B(0))) and A(0) and p and q and r;
Z <= u or v or x or y;
end behave;

Digital System Design (EE005-3.5-3) : Individual Assignment Report

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Digital System Design

Name : Arunachalam Balaji

Arunachalam Balaji (TP019324)

A typical Schematic Symbol of the ALU

VHDL offers various advantages to the designers such as:

 Standardised language and instantly available tool.

Arunachalam Balaji (TP019324)

Objectives of the study

The other objectives of this assignment are :

 Design a VHDL code for the type of ALU specified.

Arunachalam Balaji (TP019324)

The Required ALU Functions & Operations

Opcode Operation Description

000 LES OUTPUT <= A << B

001 GRA OUTPUT <= A >> B

010 ADD OUTPUT <= A + B

011 SUB OUTPUT <= A – B

100 AND OUTPUT <= A and B

101 NOR OUTPUT <= A nor B

110 OR OUTPUT <= A or B

111 XOR OUTPUT <= A xor B

ALU Block diagram:

Arunachalam Balaji (TP019324)

TRUTH TABLE FOR OR GATE

Arunachalam Balaji (TP019324)

VHDL Program For OR Function

-- 1 Bit OR Gate program

-- Main Program (4-bit OR Gate Program)

Arunachalam Balaji (TP019324)

Logical Exclusive OR Function (XOR) :

TRUTH TABLE FOR XOR

Arunachalam Balaji (TP019324)

VHDL Program For XOR Function

--XOR Program (1-bit)

--Main Program (4-bit XOR gate)

Arunachalam Balaji (TP019324)

Compliment OR Function (NOR) :

TRUTH TABLE FOR NOR

Arunachalam Balaji (TP019324)

VHDL Program For NOR Function

--NOR Program (1-bit)

--Main Program (4-bit NOR Gate)

Arunachalam Balaji (TP019324)

Logical AND Function :

TRUTH TABLE FOR AND

Arunachalam Balaji (TP019324)

VHDL Program For AND Function

--And Program (1-Bit)

-- Main Program (4-bit AND Gate)

Arunachalam Balaji (TP019324)

TRUTH TABLE FOR ADDER

A B C_IN SUM C_OUT

Fourbit Full Adder Design :

Logical Equation For Full Adder :

Arunachalam Balaji (TP019324)

VHDL Program For ADDER

--Full Adder Program (1-Bit)

Arunachalam Balaji (TP019324)

--MAIN PROGRAM (4-Bit Full Adder)

Arunachalam Balaji (TP019324)

TRUTH TABLE FOR SUBTRACTOR

Logic equations Of Subtractor: