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Prior to placement of the standard cells, the placement of all metal layers increase, the direction alternates so that any two
macro, IP blocks, and pad cells needs to be defined. The tool consecutive metal layers will always be perpendicular to one
then places the standard cells automatically based upon the another. To route standard cells together, the router uses a
timing of the design, which is given by the design constraints. grid or routing track to maneuver from point A to point B.
Along with the timing, the ability to connect each standard Due to design rules imposed by a fabrication vendor
cell as described in the gate-level netlist is also taken into (foundry), the metal routes need to have a certain minimum
account so that overall wire length (RC affect) is reduced. width and spacing in order to be manufactured correctly. The
The pins on the standard cells are then physically connected routing tracks are designed to make sure that these width and
during the routing stage of the process. This is also based on spacing requirements are achieved. The problem of routing
timing due to the fact that more timing critical nets such as congestion can then occur if there are more connections to be
clocks should have the shortest lengths and non-critical nets made than routing tracks available.
can afford to be longer. This concept is represented by Fig. 4. This background information on placement and routing
only sketches some of the things that can be done during the
physical design process. There are other problems that need
addressed during the flow in order to complete a design.
These problems include what to do in the likely case the
critical paths of the design do not meet the timing
requirements of the system or how to connect all of the
Fig 4. Visualization of Place and Route. Synopsys® register clock pins in the design so that the design is
synchronized correctly. The remainder of the design flow will
The timing driven placement of cells takes advantage of the show how Astro™ can be used to deal with all of these
common cell height and locates the standard cells into problems to produce a final place and routed design with all
“placement rows”. Within the rows, cells that are part the timing constraints achieved.
timing critical path based upon the design constraints will be
placed closer together so that interconnect delays are reduced. B. DESIGN SETUP
These placement rows can either be abutted or non-abutted
Before a design can be placed and routed within Astro™,
rows. As shown by Fig. 5, one drawback to non-abutted rows
the environment for the design needs to be created. The goal
is increase in area due to the gap between standard cell
of the design setup stage in the physical design flow is to
placement rows. If the rows were abutted, then the cells on
prepare the design for floorplanning. The design setup flow is
the top row would need to be flipped so that the VDD lines
outlined in Fig 6. As shown in the figure, the first step is to
would merge as opposed to VSS shorting with VDD if they
create a design library. Without a design library, the physical
are not flipped. The most common approach is to implement
design process using Astro™ will not work. This library
abutted rows to reduce area as well as increase the metal size
contains all of the logical and physical data that Astro™ will
of the VDD or VSS connections.
need. Therefore the design library is also referenced as the
design container during physical design. One of the inputs to
the design library which will make the library technology
specific is the technology file. This file must be explicitly
defined when creating the design the library. The technology
file contains all of the necessary data for Astro™ based upon
a specific process node, such as 130 or 90nm. This file
contains all of the mask layer information as well as via
definitions used for the connection of metal. This is also
where a version of the process design rules used by the tool is
maintained. This information such as metal widths and
Fig 5. Timing driven placement of standard cells on non-abutted rows.
spacing for each layer can be used by the place and router to
Synopsys®
aid in simple design rule checking for manufacturing. Since
Now that the basic concept of placement has been Astro™ is a graphical user interface (GUI), the layout layers
understood, the background of routing can be established. In can have different colors and fill backgrounds associated with
many technologies, there are several levels of aluminum or each layer. This information is also stored in the technology
copper metal that can be used to provide the connections file. Other critical data that is contained in the technology file
between all of the cells in the design. When going from one are the resistance and capacitance values for each layer. This
layer to another, a “via” must be used to make the connection. data usually comes in table look-up (TLU) format and is used
To prevent metal shorting together during routing, each metal by Astro™ to determine the resistance and capacitance of a
layer has a preferred direction, either horizontal or vertical. particular route. It then can be used to calculate delay
Typically in routing, the first metal layer is horizontal. As the introduced by the routing. The units for dimensions such as
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time, distance, resistance, capacitance, etc are identified in the even the Electronic Design Interchange Format (EDIF).
technology file, so that Astro™ as well as the physical design There are positives and negatives to using any of the formats;
engineer can interpret the data correctly. During the creating however, the industry standard is to use either Verilog or
of the design library, this technology is processed into the VHDL as the gate-level input. The netlist is parsed for any
library and stored within the database. Once this is done, the syntax errors that will cause problems during the physical
design library or container has been created. design process. If errors are found, then the netlist needs to be
updated prior to continuing. The first two stages do not need
to be repeated if there are netlist problems, only the read
netlist portion of the flow needs to be repeated.
Since most designs are complex enough to require logical
hierarchy, the design needs to be flattened or made non-
hierarchical in order to work for Astro™. This step is called
expanding the netlist because each level of hierarchy in the
design is expanded or flattened until the only representation is
the leaf cells. During this process, Astro™ is able to validate
that all leaf cells have a corresponding abstract view in a
reference library. As described before, the abstract view is the
necessary data from the layout that is needed for place and
route. If there are abstract views of leaf cells missing from the
reference libraries, then the layout design is incomplete and
Astro™ will not be able to continue. Once all leaf cells are
determined to have the correct abstract views in the reference
library, the expansion process will complete without error.
Now that the netlist has been read into the design library and
has been correctly expanded, a starting cell needs to be
created within the design library.
This starting cell will be the beginning point for place and
route in Astro™. The directory structure is seen in UNIX or
Linux for a design library named “design_lib_orca” as shown
in Fig. 7.
Fig 6. Design Setup Flow using Astro™. Synopsys® Fig 7. Directory structure created under a design library in Astro™.
Synopsys®
The next step is to attach reference libraries to the design
library. These reference libraries, as discussed previously, The CEL directory is the where the starting cell and all
contain the standard cells, macro cells, pad cells, and/or subsequent cells are stored for place and route. The starting
reusable IP core cells that are being implemented into the cell is typically named by the name of the top level of
design. These libraries can contain several hundreds of cells hierarchy in the netlist. In this case, the starting cell view
and are referenced by pointers in the library for memory would be named “ORCA”. The NETL directory is created
efficiency. However, the cells being implemented by the gate- during the read netlist stage of design setup. This is where all
level netlist need to be located within the reference library. If levels are hierarchy are maintained as well as the connectivity
the cell does not exist, then the next step of reading the netlist of all levels in the design. The EXP is the directory created
into the library will fail. when the design is expanded so that all sub-blocks are
Once the design library has been created, and all flattened to the leaf cells. This expanded version of the netlist
appropriate reference libraries have been attached, the next maintained in the EXP directory is the logical representation
step is to read the gate-level netlist into the library. This gate- of the netlist needed by Astro™ to perform place and route.
level netlist is produced during the logic synthesis stage that The CEL directory is where the layout or graphical
was discussed earlier. There are several different formats that representation is stored. Therefore the EXP and CEL views of
this file can be generated into including Verilog, VHDL, or the design need to be combined to begin the place and route
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process. This leads to the next step which is referred to as areas. These areas are the pad area, core area and the
binding the netlist to the cell. During this step, the expanded power/ground distribution area as shown in Fig. 8.
netlist is bound to a specific graphical cell view. This allows
Astro™ to merge the logical and physical representations of
the design. Within the cell (CEL) view, all cells referenced in
the gate-level netlist are now visible, or in other words, the
cells needed to make the design have been assembled
together. This includes all standard cells, pad cells, macro
cells, and reusable IP cells which are implemented within the
netlist. The placement of all used cells in the starting cell
view is not considered placement but rather a graphical
representation of what will be needed. At this point the netlist
has been expanded since Astro™ operates only on a flattened
design. The problem exists that after Astro™ has placed and
routed the design, there will need to be functional verification
of the netlist produced by Astro™. Since most testing and Fig 8. The location of the core and periphery areas as well as the Power and
verification performed prior to place and route was conducted Ground grid define the floorplan of a design. Synopsys®
using the benefits of hierarchy, the tool needs to be able to
reproduce the netlist in a hierarchical fashion. This is solved The pad or periphery area identifies the locations of the
during the last stage of design setup which is to preserve the input/output (I/O) cells for the design, and the core area
hierarchy. Since the preservation is done prior to floorplan, defines the location for the standard cells, macro cells, and
clock trees, and other Astro™ optimizations, the tool will be any reusable IP implemented in the design. The
able to create a hierarchical netlist to be used for verification. power/ground network distributes the power and ground
The preserve hierarchy utility maintains the ports and the needed by the core area logic as well as the I/O in the
function of the ports at the hierarchical boundaries of the sub- periphery area. In the peripheral area, there are several types
blocks. This information is used to reconstruct the hierarchy of I/O pads that can be implemented. Most of the area is used
based upon the expanded version within Astro™. Once the by signal pads so that signals can go into and out of the chip.
netlist is bound to the starting cell and the hierarchy preserved Their placement is fixed and is usually based upon the chip
in the design the library, the design setup stage is completed packaging requirements. The pads can be moved during the
and the design is ready for the floorplanning stage. floorplanning stage if the package requirements change or the
C. FLOORPLAN original placement of the pads causes a packaging violation as
can occur when wire-bonding is used to make connections to
The design setup prepares the netlist and design for
the chip. The pad locations need to be fixed prior to
floorplanning within Astro™. Floorplanning can be
completion of the floorplanning stage. In addition to signal
considered layout design done at the chip level [2]. This
pads, power and ground pads are placed to receive the power
design blueprint shows the actual placement of major
and ground connection externally. These pads are placed in
components in the design such as inputs/outputs and memory
the peripheral area similar to signal pads, however, their
elements such as RAMs. Floorplanning is a form of
inputs are power (VDD) and ground (VSS) as opposed to a
placement which can be done manually or automatically. It
switching digital or analog signal.
helps do things such as define the layout hierarchy of the
The physical size of the I/O circuitry as well as the chip size
design as well as aid in the estimation of the overall area
being implemented determines the amount of core area
required. This is also the time where aspect ratios of certain
available for standard and macro cells. The actual amount or
design blocks can be analyzed and established as to which
percentage of the core area that is used by standard cell and
sizes will give the best timing results [9]. There are a few
macro logic in a given design is referred to as the core
approaches to floorplanning that can be used. These
utilization of the design. This percentage is found by
approaches include constructive, iterative, and knowledge-
summing the total standard cell area in addition to the macro
based [9]. Constructive assumes a starting module and other
cell area and dividing by the core area. To achieve maximum
parts of the design are added one at a time until all major
efficiency and use of expensive silicon, the design should be
blocks have been added to the floorplan [9]. The other
100% utilized with standard and macro cells. However, with
methods of iteration and knowledge-based assume that an
dimensions becoming smaller and the density or amount of
initial floorplan have been proposed. However, using current
shapes becoming larger inside of standard and macro cells,
and previous design knowledge to help in the floorplan can
having 100% core utilization would result in routing failure of
reduce the number of iterations that produce a final floorplan
the design. Once the design is placed, all of the cells need to
with the greatest probability of meeting the design timing
be routed. With such high utilization, there would be more
constraints.
routes or wires in the design than the fixed number of routing
For most designs, the floorplan consists of three major
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tracks could manage. This routing congestion would be come complete including pad/macro placement and power and
an obstacle almost impossible to overcome without a ground distribution, the standard cells are ready to be placed.
reduction in the utilization. Many designs range from 80-85%
D. TIMING DRIVEN PLACEMENT
for final core utilization. However, the starting gate-level
netlist should only range from 60-75%. This will allow the When discussing the fundamental steps of place and route,
needed area for logic optimizations, clock tree cells, and other the timing constraints must be incorporated. These timing
constraints are the requirements for a complete working
cells added during the timing closure of the physical design
design, and neglecting them will result in an expensive piece
process.
of junk. The place and route steps must be timing oriented
Floorplanning the core area consists of placing the large
and Astro™ provides this timing-driven place and route tool.
macro cells such as RAM, ROM, or other IP being used in the Astro™ will optimize, place, and route the logic gates to meet
design. As shown in Fig. 8, these blocks can be placed all timing constraints or speed goals of a particular design. As
anywhere in the core area. However, approaches mentioned mentioned in the overview of the design flow, the timing
previously such as iterative or knowledge-based floorplanning constraints are a critical input to the place and route tool.
will help in the proper placement of such blocks. Poor Astro™ needs these timing constraints to understand the
placement of macros during floorplanning can lead to design timing objectives. Standard constraints on most
problems later in the physical design process such as designs include arrival times of input signals to the design as
placement and routing that require the design to be re- well as the required arrival time at the output of the chip.
floorplanned wasting time and money. Therefore, it is Other common constraints include the clock period of the
recommended to assemble a good floorplan using the system clock as well as other clocks if the design contains
following guidelines. The large macros such as RAMs and IP multiple clock domains. The format of these constraints used
should be to the sides or close to the corners depending on the by Astro™ is called Synopsys Design Constraints (SDC).
number of macros. When placing these macros, sufficient The SDC used by Astro™ during place and route is generated
space should be maintained between macros so that large by the logic synthesis tool. This allows Astro™ to place and
routing channels are defined. The placement of the blocks route based upon the same timing constraints as the synthesis
should also create large partitions for standard cell placement. tool. The timing information that Astro™ uses to meet these
Restricting the placement of standard cells into small areas goals is based upon the delays of the standard cells in the
design as well as the nets or wiring that connect the cells
between macros or in other parts of the chip may lead to
together. The standard cell delays are a function of the input
timing constraint problems. Each design is different and these
transition time as well as the summation of the capacitance of
guidelines should only serve as a starting point for an initial
the output wire and input gates of all logic connected to the
floorplan. A few quick iterations of placement and routing output wire. If any of these attributes are large or small, then
may reveal a better but different floorplan. the cell delay will increase or decrease respectively. The wire
Once the pads and large macros have a fixed location, the delay is similar and is a function of the resistance of the metal
power and ground network can be created to connect power as well as the capacitances described for the cell delay (wire
and ground to these cells. This network or grid will also capacitance + input gate capacitance). Using this cell and
supply the power and ground connections to the standard cells wire delay information, Astro™ is able to perform timing-
that will be placed in the design. The purpose of this grid is to driven placement. However, prior to placement, Astro™ can
take the powers and grounds received from the pads in the perform a sanity check on the design constraints before
periphery and distribute it evenly across the entire core area. continuing in the design flow. The process is call a “zero-
This is to ensure that all cells in the design receive the same interconnect” check and the purpose is to verify that the
power and ground signals as applied to the power and ground design constraints can be achieved throughout the physical
pads. In reality, the power and ground levels in the core area design process. Astro™ can perform the timing analysis on
are different than those at the pad, but the grid should be the design while ignoring the wiring delay. If the design can
constructed in a way that makes the difference as small as not meet the constraints, then it is a good indication that after
possible. As shown in Fig. 8, the power and ground rings are the design is routed and wiring delay is added, the design will
created around the edge of the core area. Then straps are not achieve the timing objectives. After this check has passed
and the constraints for a given netlist are considered
created that connect from one side of the ring to the other side.
achievable, the design can be placed.
The rings and straps are created using the process metal layers
Timing-driven placement of a design is the process of
and span both vertically and horizontally depending on the
placing all standard cells onto rows in the core area using the
preferred direction of each metal layer. Since the network is timing constraints as the guidelines as to where to place cells.
created using most of the metal layers in a horizontal and The design in Fig 9 shows all of the unplaced standard cells
vertical manner, the end result is power and ground grid. on the right side of the figure. The rows are abutted in this
There are separate straps for power and ground that connect to design and cells will be placed similar to those in Fig 5. As
the other power and ground straps and rings as well as any described in the overview, timing-driven placement will
macros in the design. Using the rings and straps, the power attempt to place cells within the critical timing paths close
and ground applied to the pads is now distributed to all the together to reduce wiring resistance and capacitance. Since
cells in the design. Now that the floorplan of the design is the design is not routed, Astro™ uses virtual routes or best
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estimates to simulate the length and direction of cell will occur associated with the signal transition time and
connections. capacitance due to the length of the net and the many
connections (load) to it. Known as skew, if the clock reaches
some registers before others, data transfer problems will be
the result as well as overall timing objectives not being
achieved.
There are some traditional clock network topologies that are
used to prevent or reduce the amount of clock skew
introduced into the design. These topologies are referred to as
the H-Tree and X-Tree networks and are shown in Fig 10.
capacity to not only buffer the high fan-out network and short as possible. Nets that are non-critical are routed around
balance the loads at each stage, but to optimize and minimize critical areas to provide more wiring area for critical nets.
the skew within the clock network. The results of before and The routing system used by Astro™ is grid-based as shown
after clock tree synthesis can be seen in Fig 11. Once the in Fig 12. Metal traces or routes are created and centered on
clock tree is generated, Astro™ can calculate the delay from routing tracks. These metal routes must meet minimum width
the clock source in the pad area, through the clock network and spacing requirements to prevent defects during
and to the register. This delay is considered the insertion fabrication.
delay of the clock. Prior to clock tree synthesis, information
such as a target skew and/or an insertion delay target can be
given to Astro™. Some design constraints may contain a
minimum insertion delay required for the clock. If Astro™
determines that the insertion delay after clock tree synthesis is
still less than the minimum insertion delay required, the tool
has the ability to add a delay line of buffers to meet the
required insertion delay.
There has been an assumption made and reinforced by Fig
11 that the clock source comes directly from the I/O pad area
and directly connects the registers of the design. However, in
many designs, power-saving techniques such as clock gating
are employed so that the clocking can be enabled or disabled
to sections of the design. During clock tree synthesis, Astro™
can understand this clock gating logic and still build a clock
tree to all clock pins on the output of the clock gating logic.
This allows there to be logic between the clock source and the
registers in the design.
The result of clock tree synthesis is a balanced clock tree
with minimized skew. This means that the output loads at the
different tree levels are balanced and the delays to the clock
inputs are matched among all registers. Other effects of clock
tree generation include the increase of design congestion due Fig 12. Grid-based routing systems using tracks. Synopsys®
to the fact that many clock buffers were added. Placed cells
from before may have been moved to non ideal locations Grid-based systems use these pitches (width + spacing) to
when the clock buffers were placed into the design. Since determine the minimum center to center space for each metal
these cells have moved from there original locations after layer. The design rule information to form this grid is located
placement, the timing information will be different and there in the technology file for each metal layer. There are
may be timing constraints not being met. Therefore, after horizontal and vertical tracks (grid) to correspond with
clock tree generation, some of the optimizations performed preferred routing directions of metal layers. As shown in Fig
during the placement process may need to be used in a post- 12, the preferred direction for metal 1 is horizontal and
placement method. Now that the design has been placed, vertical for metal 2. A major problem with routing in a grid-
optimized, and all clock trees have been grown, the next step based system is the potential congestion of the metal routes.
is to route the design. Congestion results from there being more wires in the design
to route than tracks available. Typically only small areas of
the design experience congestion in which standard cells can
F. ROUTING be moved accordingly. If the congestion is severe, more
Routing is a fundamental step in the place and route process. extreme measures may need to be taken such as the moving of
The virtual routes that were used in the previous steps of macros or the re-floorplanning of the entire design.
placement and clock tree synthesis need to become reality for Astro™ performs several operations during the routing
fabrication. The basic goal of routing is to create metal shapes process. These include global routing, track assignment,
that meet the requirements of a fabrication process. These detail routing, and search and repair. Global routing is the
metal shapes then become the physical connection between first step in the routing process. In this step, each wire
the cells in the design. Once the cells are connected by receives a broad routing plan determining how the net will be
routing, the overall timing of the design needs to be preserved. routed in the design or through which channels that are open
Timing data such as signal transitions and clock network skew for routing [9]. This step outlines the overview of how all of
that were used to meet the timing requirements during the point A’s will get to the point B’s. It also lays the
placement and clock tree synthesis need to be kept. Similar to groundwork for the next step which is track assignment.
placement, the process of routing is also timing-driven. In Track assignment assigns each net or wire to a specific track
efforts to maintain the overall timing, the routing of a timing and creates the physical metal connections. Once all of the
critical path is given the highest priority so that the route is as nets have a corresponding track, the track assignment will
attempt to reduce the number of jogs or bends in the metal by
10
making the routes straighter. The other goal is to reduce the the design stage prior to fabrication will help in the
number of vias in the design to help in the eventual manufacturing and ultimately the yield of the design. These
manufacturing of the design. The design rule spacing and problems can include gate/oxide integrity, via resistance and
widths in the technology file for each metal layer are not reliability, and metal erosion. In terms of via resistance and
checked during the track assignment phase. These rules are reliability, single via connections throughout the design can
checked during the next two steps, detail routing and search reduce the yield. One missing via on one connection in the
and repair. Detail routing tries to fix the design rules design will result in an open connection and, the design will
(minimum width, spacing, etc) which were violated during not function correctly. Therefore, having extra via
track assignment. The design is broken into smaller boxes connections reduces the chance of having open connections in
(“Sboxes”) as shown in Fig 13. the design. Astro™ has the capability to add extra vias on one
or all connections (routes) within the design with the tradeoff
of expending the area to add vias to increase yield.
The problem of metal erosion is a result of attempts to
planarize or make the wafer flat. This technique, chemical-
mechanical polishing (CMP), polishes the deposited dielectric
layers during the metal interconnect process to provide a
smooth and level surface for the next metal layers being
deposited [15]. Due to the material property differences
between the metal and the dielectric, erosion can occur during
CMP on the metal traces which are very wide [15].
Therefore, the metal density needs to be reduced in those
areas. The reduction is referred to as metal slotting and is
implemented by creating rectangular openings or slots in the
wide metal traces during the physical design process [16].
Another problem of damaging the gate/oxide of a transistor
is introduced during the metal etching stages of fabrication.
Ion etching is used both to remove excess metal under a mask
as well as the removal of the mask layer itself [16]. During
this etching, charge collection occurs on the metal traces and
Fig 13. Detail Route SBoxes. Synopsys®
if the charge is significant, the transistor can be damaged or
even destroyed. This phenomenon is referred to as the
Due to the fact the boxes are a fixed size, the detail router may antenna effect. The longer the metal trace connected to the
not be able to fix all the design rule violations. The next step transistor, the more charge that can collect during the etching
of search and repair is designed to resolve the remainder of process. Therefore the amount of metal connected to a
the design rule violations. Search and repair uses the same transistor gate needs to be limited. Many chip manufacturers
concept of Sbox, however, each time through the design the define acceptable length of metal traces by the ratio of the
size of the box increases to incorporate a larger portion of the metal area to the transistor gate area. This antenna ratio rule
design. The search and repair stage is the last step in the must be observed similar to other design rules such as metal
routing process. Once search and repair has resolved all spacing and widths. Astro™ has the capability to recognize
design rule violations, the design is considered to have been and repair any routes that violate the antenna ratio rule using
placed and routed and ready for verification and fabrication. standard techniques of “layer jumping” and diode insertion
during the routing phase of physical design.
G. DESIGN FOR MANUFACTURING
Prior to verification and fabrication, the physical design
engineer can use Astro™ to address several manufacturing III. VERIFICATION
yield problems. Yield improvement is typically considered a Once the physical design process in Astro™ is complete,
process domain issue. However, there are other parts of the the design needs to be verified prior to fabrication. The
design process which can improve yield. One domain that can design needs to be verified for timing, functionality, and
improve yield is in the testability of the product using design manufacturability. This verification is completed outside of
for test (DFT). Another domain is during the mask Astro™, using industry standard, production quality (“sign-
preparation phase through procedures such as reticle off”) CAD tools. The Synopsys® sign off tool Formality® is
enhancement technologies (RET). The domain in which used for checking functionality of the design. This formal
Astro™ can be implemented is during the physical design verification compares the original gate level netlist produced
phase through techniques described as design for by the logic synthesis tool and the final netlist created by
manufacturability (DFM) [10]. Before a designer can actually
Astro™. This comparison is to ensure functional equivalency
design for manufacturability, the designer needs to know what
at the logical level between the two implementations of the
features of the design will cause problems during the
design.
fabrication process [11]. Focusing on these problems during
The verification of timing contraints is a multiple step
11
have forced logic designers to think more physically, physical library and intellectual property (IP), or cell data, for that
designers to think more electrically, and have driven EDA process.
vendors to provide solutions for both [7]. The future of EDA RSPF – Reduced Standard Parasitic Format. This format
tools will be to provide logic and physical designers the tools replaces the RC trees used by DSPF format with simpler
that will accurately solve or eliminate the challenges of the models for drivers and loads.
65nm node and beyond, and therefore produce systems with SDF – Standard Delay Format. This format is used for
the fastest speeds, lowest cost and power, and in the least back-annotating delay information from chip layout to VHDL
amount of area. or Verilog source code. This provides more accurate
information for timing simulation.
V. CONCLUSION SPEF – Standard Parasitic Extended Format. This format is
Designing a sophisticated VLSI system of any kind is a based mainly upon SPF. However, this format has extended
complicated task. Completing a design can take over one year capabilities and is implemented in a smaller format.
from system conception to fabricated chips. With the number SPF – Standard Parasitic Format. This format enables the
of transistors that can be involved and the challenges posed transfer of design specific parasitic capacitances and
and each process node, no one person or team could manually resistances from the physical design tools to timing analysis
design and complete a system within the given time frames and simulation tools.
required to be competitive. Therefore, the task of designing, Verilog – A hardware descriptive language similar to C
placing, routing, and fabricating such complex chips needs to language used in the design of ASICs and FPGAs. Verilog
become automated. This automation comes in the form of contains a hierarchy of modules which describe the inputs and
EDA tools like Astro™ produced by companies such as outputs as well as the wire connections within that module [3].
Synopsys®. VHDL – A hardware descriptive language used as a design
entry language for the design of ASICs and FPGAs [3].
APPENDIX
ACKNOWLEDGMENT
This appendix will briefly describe some of the standard
data formats that are used in the EDA industry. Some of these Jamie Bernard would like to thank Synopsys® and the
descriptions were found on the Electrical Design News application engineers who supported the effort in describing
website [13] unless otherwise noted. their EDA tools and applications of the physical design
DEF – Design Exchange Format. This format contains both process.
the logical and physical design information. Logical
information includes cell connectivity, cell grouping, timing REFERENCES
parameters, path constraints, scan chains, and clock tree [1] http://www.intel.com
[2] W. Wolf, “Modern VLSI Design System On Chip Design”, 3 rd ed.,
information. Physical information includes cell placement and Prentice Hall, 2002.
routing geometries. [3] http://en.wikipedia.org
DSPF – Detailed Standard Parasitic Format. This format, [4] http://www.synopsys.com/corporate/co_profile.html#fact
[5] S. Rajan, “Essential VHDL RTL Synthesis Done Right”, 1998.
defined by Cadence®, is now in the public domain. The root
[6] “Where are the tools for the next node?”, EE Times Issue 1394 October
format, SPF, looks very much like Spice. DSPF includes 24, 2005.
comments and a structure that make it easier to organize the [7] N. Deo, “At 90nm, history repeats itself”, EE Times Online Article,
netlist information into the original circuit with added 2002.
[8] J. Banker, A. Shanbhag, and N. Sherwani, “Physical Design Tradeoffs
information for RC trees. for ASIC Technologies”, Western Michigan University, 1993, pp 70-78.
EDIF – Electronic Design Interchange Format. This format [9] S.M. Sait, H. Youssef, “VLSI Physical Design Automation Theory and
provides the syntax for exchange of electronic circuit Practice”, vol 6, World Scientific Publishing, 2001.
[10] L. Riviere-Cazaux, K. Lucas, and J. Fitch, “Integration of Design For
information. This information includes circuit connectivity Manufacturability (DFM) Practices In Design Flows”, Sixth
and related attributes as well as a schematic representation. International Symposium on Quality Electronic Design, 2005.
GDSII – Graphic Design System II. This format contains [11] M. Bajaj, R. Peak, M. Wilson, I. Kim, T. Thurman, M. Jothishankar, M.
Brenda, P. Ferreira, and J. Stori, “Towards Next-Generation Design-for-
the physical geometry information of a design. It is a binary Manufacturability (DFM) Frameworks for Electronics Product
format for representation of planar geometric shapes and text Realization”, International Electronics Manufacturing Technology
labels. The shapes are assigned numeric attributes in the form Symposium, 2003.
of "layer number" and optional "datatype" or "texttype" [3]. [12] E. Friedman, “Clock Distribution Networks in Synchronous Digital
Integrated Circuits”, vol 89, May 2001.
LEF – Library Exchange Format. This format includes the [13] http://www.edn.com/archives/1996/101096 “Electrical Design News”
ports and wiring congestion information for routing tools. It [14] M. Chen Chi and S. Huang, “A Reliable Clock Tree Design
also contains data relative to the process geometry within each Methodology for ASIC Designs”, International Symposium on Quality
Electronic Design, March 2000.
cell. There is also other "abstract" information relative to the
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