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Source: http://newsgroups.derkeiler.com/Archive/Comp/comp.arch.fpga/2006−01/msg00260.html
• From: cdsmith69@xxxxxxxxx
• Date: 5 Jan 2006 11:53:33 −0800
So I need some help getting started with programmable logic and VHDL.
In the past all I have done in the programmable logic area are 16V8 and
22V10 PALs.
But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and
the Xilinx XC9536XL experimenter board I am using.
I've gone through ALDEC's Evita VHDL tutoral end to end and I think
I've learned the basics of the language.
I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through
a current limiting resistor. The other end of each LED is connected to
an output of the CPLD. So sending a logic zero to the output should
sink current and turn on the LED. The LEDs work because I can unplug
them from the socket header and connect each to ground and the LED
lights as expected.
The first "simple" program I wrote was to read the switch inputs and
output them to the LEDs, using the following VHDL code in Xilinx ISE
7.1:
−−−−−−−−−−−−−−−−−−−−−−
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Test1 is
Port (SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Test1;
This code shows that the LEDs and switches work. I can flip the
switches and the LEDs change state. But here is the first problem.
The LEDs light opposite what I expect. The LEDs light when the
corresponding switch is set to input a high into the CPLD. It's like
either the inputs or outputs are being inverted inside the CPLD.
This should kill two birds with one stone. It will show me if I can
assign pins directly to values when it is part of an equation that
includes inputs that can change state. I thought mabye my previous
attempts didn't work since there was nothing to "trigger" the equation.
Also, with ANDing the switches and outputting that to one LED, I can
tell if it is the inputs or the outputs that are being inverted inside
the CPLD. If it is the inputs, I would have to set the switches to all
The result is that the upper 3 LEDs still all remain off, despite
directly setting two outputs to a one and one output to a zero. My
logic probe shows a high on those three CPLD pins. Apparently I can't
directly set a pin even when it is part of an equation.
The last LED lights when all four switch inputs are set to input a
high. This indicates that the inputs are not being inverted in the
CPLD. But the LED lights when the switches are all set high and I can
measure a logic low, 0V, on that LED's pin. This would indicate that
the outputs are being inverted from the way the assignment equation
would indicate.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter1 is
Port ( CLK_IN : std_logic;
SWITCH_IN : in std_logic_vector(3 downto 0);
LEDS_OUT : out std_logic_vector(3 downto 0));
end Counter1;
In the simulator this counter works fine, but when I run this code the
output sequence I get is not a straight count from 0 to 15. I get the
sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly
repeatable, and the sequence reverses when I flip SWITCH_IN(0). After
some looking at the binary for that count sequence, I noticed that
every second number is the inverse of the previous, instead of the
expected number (14 is 1110, inverse of 0001 that preceeded it, not
0010 as expected next). I don't get it.
So my questions are:
1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an
inversion happening somewhere inside the CPLD, apparently at the
outputs?
2. Why can't I just set outputs to a zero and have a LED light? Any
pin I directly assign to a value stays high.
3. Why doesn't my counter count?
This ended up a lot longer than I expected, so if you made it this far,
thanks for reading it, and thanks for any help you can provide...
cdsmith
• Follow−Ups:
♦ Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
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♦ Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
◊ From: James Kennedy
♦ Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
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