CONSTRUCTION
Serial programmer / IC Burner
for 8051 Microcontrollers
HARSH KUMAR
In-System Programming (abbreviated ISP) is the
ability of some programmable logic devices,
microcontrollers, and other programmable
electronic chips to be programmed while installed
in a complete system, rather than requiring the chip
to be programmed prior to installing it into the
system. The primary advantage of this feature is that
it allows manufacturers of electronic devices to
integrate programming and testing into a single
production phase, rather than requiring a separate
programming stage prior to assembling the system.
This may allow manufacturers to program the chips
in their own system's production line instead of
buying preprogrammed chips from a manufacturer
or distributor, making it feasible to apply code or
design changes in the middle of a production run.
NXP P89V51RD2 microcontroller can be
programmed using this IC Burner. The P89V51RD2
is an 80C51 microcontroller with 64 kB Flash and
1024 bytes of data RAM. A key feature of the
P89V51RD2 is its X2 mode option. The design
engineer can choose to run the application with the
conventional 80C51 clock rate (12 clocks per
machine cycle) or select the X2 mode (6 clocks per
machine cycle) to achieve twice the throughput at
the same clock frequency. Another way to benefit
from this feature is to keep the same performance
by reducing the clock frequency by half, thus
dramatically reducing the EMI. The Flash program
memory supports both parallel programming and
in serial In-System Programming (ISP). Parallel
programming mode offers gang-programming at
high speed, reducing programming costs and time
to market. ISP allows a device to be reprogrammed
in the end product under software control. The
capability to field/update the application firmware
makes a wide range of applications possible. The
EM TESTED
EM TESTED
EM TES
TED
P89V51RD2 is also In-Application Programmable
(IAP), allowing the Flash program memory to be
reconfigured even while the application is running.
Features of P89V51RD2 micro-
controller
• 80C51 Central Processing Unit
• 5 V Operating voltage from 0 to 40 MHZ
• 64 kB of on-chip Flash program memory with
ISP (In-System Programming) and IAP (In-
Application Programming)
• Supports 12-clock (default) or 6-clock mode
selection via software or ISP
• SPI (Serial Peripheral Interface) and enhanced
UART
• PCA (Programmable Counter Array) with PWM
and Capture/Compare functions
• Four 8-bit I/O ports with three high-current Port
1 pins (16 mA each)
• Three 16-bit timers/counters
• Programmable Watchdog timer (WDT)
• Eight interrupt sources with four priority levels
• Second DPTR register
• Low EMI mode (ALE inhibit)
• TTL- and CMOS-compatible logic levels
• Brown-out detection
• Low power modes
Power-down mode with external interrupt wake-
up
Idle mode
• PDIP40, PLCC44 and TQFP44 packages
In- System Programming (ISP)
feature of NXP P89V51RD2 IC
In-System Programming is performed without
removing the microcontroller from the system. The
In-System Programming facility consists of a series
of internal hardware resources coupled with
internal firmware to facilitate remote programming
of the P89V51RD2 through the serial port. This
 CONSTRUCTION
firmware is provided by Philips and embedded
within each P89V51RD2 device. The Philips In-
System Programming facility has made in-circuit
programming in an embedded application
possible with a minimum of additional expense in
components and circuit board area. The ISP
function uses five pins (VDD, VSS, TxD, RxD, and
RST). Only a small connector needs to be available
to interface your application to an external circuit in
order to use this feature.
Serial communication is the process of sending
data one bit at one time, sequentially, over a
communication channel or computer bus. This is in
contrast to parallel communication, where several
bits are sent together, on a link with several parallel
channels.
Memory organization
The device has separate address spaces for
program and data memory.
Flash program memory
There are two internal flash memory blocks in the
device. Block 0 has 64 kbytes and contains the
user's code. Block 1 contains the Philips-provided
ISP/IAP routines and may be enabled such that it
overlays the first 8 kbytes of the user code memory.
The 64 kB Block 0 is organized as 512 sectors,
each sector consists of 128 bytes. Access to the IAP
routines may be enabled by clearing the BSEL bit in
the FCF register. However, caution must be taken
when dynamically changing the BSEL bit. Since this
will cause different physical memory to be mapped
to the logical program address space, the user must
avoid clearing the BSEL bit when executing user
code within the address range 0000H to 1FFFH.
Data RAM memory
The data RAM has 1024 bytes of internal memory.
The device can also address up to 64 kB for
external data memory.
Expanded data RAM addressing
The P89V51RD2 has 1 kB of RAM. The device has
four sections of internal data memory:
1. The lower 128 bytes of RAM (00H to 7FH) are
directly and indirectly addressable.
2. The higher 128 bytes of RAM (80H to FFH) are
indirectly addressable.
3. The special function registers (80H to FFH) are
directly addressable only.
4. The expanded RAM of 768 bytes (00H to 2FFH)
is indirectly addressable by the move external
instruction (MOVX) and clearing the EXTRAM bit.
Since the upper 128 bytes occupy the same
addresses as the SFRs, the RAM must be accessed
indirectly. The RAM and SFRs space are physically
separate even though they have the same
addresses. When instructions access addresses in
the upper 128 bytes (above 7FH), the MCU
determines whether to access the SFRs or RAM by
the type of instruction given. If it is indirect, then
RAM is accessed. If it is direct, then an SFR is
accessed.
Flash memory In-Application Programming
Flash organization
The P89V51RD2 program memory consists of a 64
kB block. An In-System Programming (ISP)
capability, in a second 8 kB block, is provided to
allow the user code to be programmed in-circuit
through the serial port. There are three methods of
erasing or programming of the Flash memory that
may be used. First, the Flash may be programmed
or erased in the end-user application by calling
low-level routines through a common entry point
(IAP). Second, the on-chip ISP boot loader may be
invoked. This ISP boot loader will, in turn, call low-
level routines through the same common entry
point that can be used by the end-user application.
Third, the Flash may be programmed or erased
using the parallel method by using a commercially
available EPROM programmer which supports this
device.
Boot block
When the microcontroller programs its own Flash
memory, all of the low level details are handled by
code that is contained in a Boot block that is
separate from the user Flash memory. A user
program calls the common entry point in the Boot
block with appropriate parameters to accomplish
the desired operation. Boot block operations
include erase user code, program user code,
program security bits, etc. A Chip-Erase operation
can be performed using a commercially available
parallel programer. This operation will erase the
contents of this Boot Block and it will be necessary
for the user to reprogram this Boot Block (Block 1)
with the Philips-provided ISP/IAP code in order to
use the ISP or IAP capabilities of this device. Serial
communication is used for all long-haul
communication and most computer networks,
where the cost of cable and synchronization
difficulties make parallel communication
impractical.
Serial communications
RS-232 (Recommended Standard 232) is a
standard for serial binary data signals connecting
between a DTE (Data Terminal Equipment) and a
 CONSTRUCTION

+5V INPUT C3
+ +
MAX232 IC C5
16
1 C1+ Vcc 2
+ +5V TO +10V V+ +10V
C1 3 C1-
VOLTAGE DOUBLER
4 C2+
+ +10V TO -10V V- 6 -10V
C2 5 C2- VOLTAGE INVERTER C4
+
+5V
400k
11 T1IN T1OUT 14
+5V
TTL/CMOS RS-232
INPUTS 400k OUTPUTS
10 T2IN T2OUT 7

12 R1 OUT R1IN 13

TTL/CMOS 5k RS-232
OUTPUTS INPUTS
9 R2 OUT R2IN 8

5k
GND
15
as high as ± 25 V), to standard 5 V TTL levels.
These receivers have a typical threshold of 1.3 V,
DCE (Data Circuit-terminating Equipment). It is and a typical hysteresis of 0.5 V.
commonly used in computer serial ports. Here is a circuit through which you can download
The MAX232 is an integrated circuit that converts your code into your Philips IC using a software tool
signals from an RS-232 serial port to signals called Flash Magic. This software tool is only used
suitable for use in TTL compatible digital logic for NXP (Philips) ICs such as P89V51RD2 IC. Flash
circuits. The MAX232 is a dual driver/receiver and Magic software is freely available on internet. You
typically converts the RX, TX, CTS and RTS signals. can download hex file of your software through
The drivers provide RS-232 voltage level outputs Flash Magic software utility.
(approx. ± 7.5 V) from a single + 5 V supply via In RS-232, user data is sent as a time-series of bits.
on-chip charge pumps and external capacitors. Both synchronous and asynchronous transmissions
This makes it useful for implementing RS-232 in are supported by the standard. In addition to the
devices that otherwise do not need any voltages data circuits, the standard defines a number of
outside the 0 V to + 5 V range, as power supply control circuits used to manage the connection
design does not need to be made more between the DTE and DCE. Each data or control
complicated just for driving the RS-232 in this case. circuit only operates in one direction, i.e., signaling
The receivers reduce RS-232 inputs (which may be from a DTE to the attached DCE or the reverse.
PB1
+5V
C1 C2
C3
A B U2
C1
C4 B A 1 P1.0/T2 VCC 40
B A U1 2 P1.1/T2EX P0.0/AD0 39
3 P1.2/ECI P0.1/AD1 38
J1 1 2 4 37
1 C1+ VDD P1.3/CEX0 P0.2/AD2
2 3 10 5 P1.4/CEX1 P0.3/AD3 36
3 4 C1- VCC 6 P1.5/CEX2 P0.4/AD4 35
4 5 C2+ 7 P1.6/CEX3 P0.5/AD5 34
C2- 8 33
5 14
P1.7/CEX4 P0.6/AD6
6 11 T1OUT 9 RST P0.7/AD7 32
A

13 T1IN 7 10 31
C2

7 T2OUT P3.0/RXD EA
Z

T2IN 11 30
P3.1//TXD ALE/PROG
B

8
R1.1

12 R1OUT 13 12 P3.2/INT0 PSEN 29

9 R1IN
9 R2OUT 8 C6
13 P3.3/INT1 P2.7/A15 28
R2IN 14 27
C5 P3.4/T0 P2.6/A14
I

15 9 B A 15 P3.5/T1 P2.5/A13 26
A B GND VEE 16 25
P3.6/WR P2.4/A12
17 P3.7/RO P2.3/A11 24
18 XTAL2 P2.2/A10 23
19 XTAL1 P2.1/A9 22
A1 20 21
GND P2.0/A8
A B
A

A
C7

GND
C8
B

Schematic of Serial Programmer

 CONSTRUCTION
8051 IC Burner
Since transmit data and receive data are separate
circuits, the interface can operate in a full duplex
manner, supporting concurrent data flow in both
directions. The standard does
not define character framing
within the data stream, or
character encoding. The RS-
232 standard defines the
voltage levels that correspond to
logical one and logical zero
levels for the data transmission
and the control signal lines.
Valid signals are plus or minus 3
to 15 volts - the range near zero
volts is not a valid RS-232 level.
CON1
The standard specifies a
maximum open-circuit voltage
of 25 volts: signal levels of ±5 V,
±10 V, ±12 V, and ±15 V are
all commonly seen depending
on the power supplies available 8051 IC Burner
within a device. RS-232 drivers
and receivers must be able to withstand indefinite
short circuit to ground or to any voltage level up to
±25 volts. The slew rate, or how fast the signal
changes between levels, is also controlled. For data
transmission lines (TxD, RxD and their secondary
channel equivalents) logic one is defined as a
negative voltage, the signal condition is called
marking, and has the functional significance. Logic
zero is positive and the signal condition is termed
spacing. Control signals are logically inverted with
respect to what one would see on the data
transmission lines. When one of these signals is
active, the voltage on the line
will be between +3 to +15
volts. The inactive state for these
signals would be the opposite
voltage condition, between -3
and -15 volts. Examples of
control lines would include
request to send (RTS), clear to
send (CTS), data terminal ready
(DTR), and data set ready (DSR).
Because the voltage levels are
higher than logic levels typically
used by integrated circuits,
special intervening driver
circuits are required to translate
logic levels. These also protect
the device's internal circuitry
from short circuits or transients
that may appear on the RS-232
interface, and provide sufficient current to comply
with the slew rate requirements for data
transmission. Because both ends of the RS-232
S2
C4
8051
C5
R2
S1
C3
C6
L1
R1
C7 C8
C1
X1
C2
circuit depend on the ground pin being zero volts,
problems will occur when connecting machinery
and computers where the voltage between the
ground pin on one end, and the ground pin on the
other is not zero. This may also cause a hazardous
ground loop. Unused interface signals terminated
to ground will have an undefined logic state. Where
it is necessary to permanently set a control signal to
a defined state, it must be connected to a voltage
source that asserts the logic 1 or logic 0 level. Some
devices provide test voltages on their interface
connectors for this purpose.