3-D SVPWM FOR THREE-LEG FOUR-WIRE VOLTAGE SOURCE INVERTERS

Marcelo Gradella Villalva∗, Ernesto Ruppert F.∗

∗
UNICAMP
Campinas, São Paulo, Brazil
Emails: mvillalv@dsce.fee.unicamp.br, ruppert@fee.unicamp.br

Abstract— This paper presents a discussion about the three-dimensional (3-D) space vector pulse width
modulation (SVPWM) for three-leg four-wire voltage source inverters (VSI). This subject has appeared with the
necessity of feeding nonlinear or unbalanced loads with sinusoidal or non-sinusoidal waveforms. Few papers treat
this subject and their discussions are very superficial. This paper investigates the 3-D SVPWM and presents
application examples.

Keywords— 3-D space vectors, pulse width modulation, three-leg voltage source inverter

1 Introduction voltages expressed in the αβ0 reference frame. Because the

The study of the 2-D SVPWM with three-leg VSI
without neutral conductor is already consolidated. Papers
such as (van der Broeck, Skudelny & Stanke 1988, Holtz
1992, Holtz, Lotzkat & Khambadkone 1992) deeply inves-
tigate the 2-D SVPWM used with this type of inverter.
The necessity of feeding unbalanced and nonlinear
load is balanced and because there is no neutral connection
of the inverter with the load the vectors have no 0 com-
ponents and are placed on the αβ plane. The abc → αβ0
coordinate transformation is given by eq. (1). All voltages
in table 1 are normalized with reference to VDC .

{
loads in applications such as series and shunt active power S1 S2 S3
filters demands an improved SVPWM method capable of VDC / 2 + va
controlling the synthesis of zero-sequence voltages and the vb
flow of neutral currents. VDC v0 vn
+ vc
In (Verdelho 1997, Verdelho & Marques 1998) the au-
thors use a three-leg four-wire VSI for controlling currents VDC / 2
S4 S5 S6
in three-phase four-wire active power filters. With the
use of hysteresis comparators and by selecting appropriate
3-D voltage space vectors their closed-loop current con-
troller allows the synthesis of positive, negative and zero- Figure 1: Three-leg voltage source inverter.
sequence currents in shunt active filter applications. The
idea of using 3-D space vectors to control zero-sequence
voltages and currents with a three-leg VSI explored in   r  1  
vα −1/2
√ −1/2
√ va
(Verdelho 1997, Verdelho & Marques 1998) can be used 2
 vβ  =  0 3/2 − √3/2  vb  (1)
with the SVPWM method. v0 3 1/√2 √
1/ 2 1/ 2 vc
The use of 3-D space vectors with a four-leg VSI is pre-
sented in (Zhang, Prasad, Boroyevich & Lee 2002), where Each output voltage combination of table 1 corre-
sponds to a different voltage space vector. Vectors V ~ 0 -V
~7
the authors thoroughly and clearly investigate the applica-
tion of the 3-D SVPWM to this kind of inverter. However are the representation of the VSI output voltages in the
two problems arise about the 3-D SVPWM with four-leg αβ0 reference frame, as fig. 2a shows. These are the ba-
inverters. First, the control algorithm is very complex and sic space vectors of the phase-to-neutral output voltages
may not fit in low-cost microcontrollers. Second, the four- of the VSI inverter. With the 2-D SVPWM the VSI can
leg VSI topology is not conventional. Although it presents synthesize three-phase voltages which are combinations of
some advantages over the three-leg VSI (such as robust- the eight basic space vectors, provided that the condition
ness) three-leg VSI power modules are widely available in van + vbn + vcn = 0 is satisfied at every time instant. This
the market and this converter topology is frequently pre- way it is possible to produce sinusoidal and balanced three-
ferred in many applications. phase voltages at the outputs of the VSI.
This paper studies in detail the application of the 3-D
SVPWM to three-leg four-wire VSI, i.e. three-leg invert- 2.2 Output voltage synthesis
ers with a neutral conductor connected to the load neutral ~ ∗ that rotates with angular speed
A reference vector V
point. The use of 3-D SVPWM with three-leg four-wire
ω on the αβ plane represents three sinusoidal waveforms
VSI was discussed in (Zhan, Arulampalam, Ramachan-
with angular frequency ω (displaced of 2π/3 rad from each
daramurthy, Fitzer, Barnes & Jenkins 2001) with a volt-
other) in the abc coordinate system. If the VSI is supposed
age restorer application. However, although interesting,
the discussion of (Zhan et al. 2001) is very poor and lacks
details about the 3-D SVPWM technique.
Table 1: Output voltages of the three-leg VSI without
2 A brief discussion about the 2-D SVPWM neutral (in pu, normalized with reference to VDC ).
S1 S2 S3 van vbn vcn vα vβ SV
2.1 Inverter topology and basic space vectors ~0
0 0 0 0 0 0 0
p 0 V
1 0 0 2/3 -1/3 -1/3 2/3 0 √ ~1
V
A three-leg VSI is show in fig. 1. A 2-D SVPWM mod- √
1 1 0 1/3 1/3 -2/3 1/ √6 1/√2 ~2
V
ulator may drive this kind of inverter when the three-phase
0 1 0 -1/3 2/3 -1/3 ~3
load is balanced and the potentials vn and v0 are indepen- p 6 1/ 2
−1/ V
0 1 1 -2/3 1/3 1/3 − 2/3 0 √ ~4
V
dent, i.e. there is no neutral connection between the load √
0 0 1 -1/3 -1/3 2/3 ~5
and the inverter. With these conditions satisfied this in- √ 6 −1/√2
−1/ V
1 0 1 1/3 -2/3 1/3 1/ 6 −1/ 2 ~6
V
verter is capable of producing the output voltages van , vbn ~7
1 0 1 0 0 0 0 0 V
and vcn found in table 1. This table also shows the same
    
va 1 √0
· ∗¸
 vβ
V3 V2
 vb  =  −1/2 3/2 ∗ (5)
SECTOR II √ vα
vc −1/2 − 3/2
(
SECTOR III SECTOR I
1 if va,b,c > 0
sign(va,b,c ) = (6)
0 if va,b,c ≤ 0
b axis V4 V0 V7 V1
(a)
N = sign(va ) + 2 sign(vb ) + 4 sign(vc ) (7)
SECTOR IV SECTOR VI

SECTOR V
Table 2: Identification of sectors
V5 V6 N 1 2 3 4 5 6
sector II VI I IV III V
a axis

V2 2.4 Determination of the application intervals

~ ∗ is given in the form of eq. (4) the intervals ∆T 1
If V
and ∆T 2 , which are the intervals of application of the vec-
b axis

DT /DT2V2
(b) ~1 and V
tors V ~2 , are obtained with eq. (8). The vectors V~0
V0 V* V1 and V~7 need not be considered in this equation because
V7 DT /DT1V1 they do not contribute to the vectorial sum which results
~ ∗.
in V
a axis ·p ¸ · √ ¸ · ∗¸
2/3 1/√6 vα
∆T 1 +∆T 2 = ∆T ∗ (8)
0 1/ 2 vβ
Figure 2: (a) The eight basic 2-D voltage space vec- | {z }
~
| {z }
~
| {z }
~∗
V1 V2 V
tors on the αβ plane (normalized with reference to
VDC ). (b) Combination of two basic space vectors ~ ∗ is in
Eq. (8) results in eq. (9). MI is valid when V
~ ∗ in sector I.
forming V sector I. For sectors II-VI the same procedure described
by eq. (8) and eq. (9) may be adopted to find matrices
MII -MV I .
to generate sinusoidal balanced three-phase voltages then · ¸ ·p √ ¸ −1 · ∗ ¸
∆T 1 2/3 1/√6 vα
a rotating vector V~ ∗ is the reference for the 2-D SVPWM = ∆T ∗ (9)
∆T 2 0 1/ 2 vβ
modulator. The 2-D SVPWM algorithm consists of mak- | {z }
MI
ing combinations of the basic space vectors of fig. 2a to
synthesize the reference V ~ ∗ . Although two space vectors ~ ∗ is given in the form of eq. (3) a general equation
If V
cannot coexist at the same instant a temporal combina- (valid for sectors I-VI) for the determination of the applica-
tion of vectors can be made during a very small discrete tion intervals may be found. In this case matrices MI -MV I
time interval, which corresponds to the modulation period are not used but the calculation of the intervals requires
∆T . This produces an average voltage (within the interval the evaluation of two trigonometrical functions for every
∆T ) that approximates the desired reference voltage V ~ ∗. interval ∆T . This is well explained in (van der Broeck
This is well documented in (van der Broeck et al. 1988). et al. 1988).
Fig. 2b illustrates the rotating vector V ~ ∗ being composed If time is left, i.e. if ∆T 1 + ∆T 2 < ∆T vectors V ~0
by two adjacent basic space vectors in sector I. Each vec- and V~7 are used to fill the modulation period ∆T . Eq. (10)
tor remains active during a small fraction of the modula- equally divides the left time between ∆T 0 and ∆T 7 .
tion period ∆T . This vectorial composition is described by
eq. (2), which is valid for sector I only. ∆T 0 = ∆T 7 = (∆T − ∆T 1 − ∆T 2 )/2 (10)

~
∆T V
∗ ~1 ∆T 1 + V
=V ~2 ∆T 2 + V
~0 ∆T 0 + V
~7 ∆T 7 (2) 2.5 Generation of the gate signals

Eq. (2) shows that during the modulation period ∆T After the application intervals are determined it is
~1 , V
~2 , V
~0 and V
~7 are applied during a fraction of necessary to obtain the gate signals S1 -S6 for the switches
vectors V
of the VSI. A very common pattern of gate signals is shown
the whole interval ∆T so that ∆T = ∆T 1 + ∆T 2 + ∆T 0 +
~0 and V~7 represent null voltages at the in fig. 3b. Other more complicated patterns may be em-
∆T 7 . Vectors V
ployed and this is the subject of papers such as (Prasad,
outputs of the VSI, as seen in table 1.
~ ∗ is located in Boroyevich & Zhang 1997, Zhang et al. 2002, Zhan, Aru-
Eq. (2) and fig. 2b are valid when V
lampalam & Jenkins 2003).
sector I. For sectors II-VI other appropriate basic space
~ ∗. Evidently fig. 3b shows the gate pattern used when
vectors must be used to compose the reference vector V ~ ∗ is located in sector I. For other sectors similar patterns
V
may be obtained by appropriately choosing the basic space
2.3 Sector identification vectors which are used in eq. (8) to compose V ~ ∗ . Table 3
~ ∗ is given in the form of eq. (3) the identification
If V shows the vector sequences for all the six sectors. Fig. 3a
of the sector where the reference vector V ~ ∗ is located is shows how the pattern of fig. 3b is obtained when the 2-D
straightforward. This is the case when the 2-D SVPWM SVPWM algorithm is implemented with a microprocessor.
modulator is used to synthesize sinusoidal waveforms. In An up-down counter set to count with period ∆T is used.
this form m is the modulation index, A is the maximum When the counter status crosses the comparison levels ta ,
norm of V ~ ∗ and θ = ωt. tb and tc the gate signals S1 , S2 and S3 are set to one or

~ ∗ = mA6 θ
V (3)
~ ∗ is given in the matrix form of eq. (4) the sec-
If V
tor identification is not straightforward. An algorithm for
Table 3: Vector sequences for sectors I-VI.
I ~0 -V
V ~1 -V
~2 -V
~7 -V
~2 -V
~1 -V
~0 IV ~0 -V
V ~5 -V
~4 -V
~7 -V
~4 -V
~5 -V
~0
identifying sectors is given by equations (5)-(7) and table 2. ~0 -V
~3 -V
~2 -V
~7 -V
~2 -V
~3 -V
~0 ~0 -V
~5 -V
~6 -V
~7 -V
~6 -V
~5 -V
~0
II V V V
~ ∗ = [v ∗ v ∗ ]T III ~0 -V
V ~3 -V
~4 -V
~7 -V
~4 -V
~3 -V
~0 VI ~0 -V
V ~1 -V
~6 -V
~7 -V
~6 -V
~1 -V
~0
V α β (4)
 DT

S3 S3 V*
tc
S2 S2 DT

β axis
(a) tb ∆T 1/ 2
2 2 ta tb tc
S1 S1 region of linear operation
ta

π
DT0 DT1 DT2 DT7 DT2 DT1 DT0 ω
2 2 2 2 2
α axis
2
(a) (b)
S1

(b) S2 Figure 4: (a) Waveforms of the comparison levels ta ,

tb and tc for linear operation with sinusoidal outputs.
S3 (b) Locus of V ~ ∗ for maximum output under linear
√
V0 V1 V2 V7 V2 V1 V0
operation (A = 1/ 2 , m = 1).

Figure 3: (a) Process of generation of the gate signals Table 4: Output voltages of the three-leg VSI with
with an up-down counter. (b) Generated gate signals neutral (in pu, normalized with reference to VDC ).
for sector I. S1 S2 S3 van vbn vcn vα vβ v0 SV
√
0 0 0 −1 −1 −1
0 0 − 3 ~0
V
2 2 2 q 2
1 0 0 1 −1 −1 2
0 −1
√ ~1
V
2 2 2 3 2 3
to zero. Eq. (11) shows how ta , tb and tc are determined 1 1 −1 1 1 1 ~2
1 1 0 √ √ √ V
for the switching sequence of sector I. 2 2 2 6 2 2 3
0 1 0 −1 1 −1
− √16 1
√ −1
√ ~3
V
2 2 2 q 2 2 3
ta = ∆T 0 /2 0 1 1 −1 1 1
− 23 0 1
√ ~4
V
2 2 2 2 3
tb = ∆T 0 /2 + ∆T 1 /2 (11)
0 0 1 −1 −1 1
− √16 − √12 −1
√ ~5
V
tc = ∆T 0 /2 + ∆T 1 /2 + ∆T 2 /2 2 2 2 2 3
1 0 1 1 −1 1 √1
− √12 1
√ ~6
V
2 2 2 6 2
√ 3
2.6 Limitations of the 2-D SVPWM and saturation-mode 1 0 1 1 1 1
0 0 3 ~7
V
2 2 2 2
operation
When the 2-D SVPWM is used to synthesize sinu-
soidal and balanced three-phase voltages, i.e. when V ~∗ ing ∆T 0 = ∆T 7 = 0, ∆T 1 = ∆T 1,sat and ∆T 2 = ∆T 2,sat
rotates at constant speed on the αβ plane, the compar- so that ∆T 1 + ∆T 2 = ∆T . Eq. (12) determines ∆T 1,sat
ison signals ta , tb and tc have the waveforms shown in and ∆T 2,sat .
fig. 4a. This produces output phase voltages (va0 , vb0 and
∆T {1,2}
vc0 ) with 3rd-harmonic components. These common mode ∆T {1,2},sat = ∆T (12)
∆T 1 + ∆T 2
components disappear when the line voltages (vab , vbc and
vca ) are taken from the outputs of the VSI. And because
there is no connection of the VSI with the load neutral 3 The 3-D SVPWM
point (vn ) the 3rd-harmonic components are not present
The 2-D SVPWM algorithm detailed in the previous
at the load phase-to-neutral voltages (van , vbn and vcn ).
section may be extended to the 3-D SVPWM algorithm
With the VSI of fig. 1 without neutral connection the
with some simple modifications. In this case the VSI of
maximum amplitude of the sinusoidal output √ phase volt- fig. 1 has the v0 potential connected to the load neutral
ages (van , vbn and vcn ) is limited to VDC / 3 because the
point vn . This allows the VSI to synthesize zero-sequence
amplitude of the line voltages (vab , vbc and vca ) is lim-
~∗ voltages and control the flow of neutral currents between
ited to VDC . This means that√ the maximum length of V the load and the DC voltage source. Because the VSI has
for sinusoidal output is 1/ 2. (One should have in mind a neutral connection and v0 = vn the basic voltage space
that V~ ∗ is the space vector of the phase-to-neutral out-
vectors of the VSI are three-dimensional. Table 4 shows
put voltages. This vector is normalized with reference to the phase-to-neutral voltages (normalized with reference
VDC .) Fig. 4b shows the locus of V ~ ∗ for maximum output
to VDC ) that can be supplied by the three-leg VSI. The 0-
with linear operation (the dimensions are normalized with axis coordinates are no longer null, thus the basic voltage
reference to VDC ). Linear operation occurs when the am- ~ 0 -V
space vectors V ~7 are situated in the αβ0 space.
plitude of the sinusoidal output voltages is proportional to Each output voltage combination of table 4 corre-
the magnitude ~∗ ~∗
√ of V . For V given in the form of eq. (3), sponds to a different voltage space vector. Vectors V ~0 -
with A = 1/ 2, the 2-D SVPWM operates in the linear ~7 are the representation of the phase-to-neutral output
V
mode for 0 ≤ m ≤ 1 and enters the saturation mode for voltages of the VSI in the αβ0 reference frame, as fig. 5
m > 1. shows. These are the basic 3-D space vectors of the phase-
When V ~ ∗ lies outside of the circle of fig. 4b the 2-
to-neutral voltages of the VSI inverter with neutral con-
D SVPWM modulator operates in the saturation mode. ductor. The 3-D SVPWM allows the VSI to synthesize
In this case the output line voltages are no longer sinu- any kind voltages with zero-sequence components by com-
soidal and saturate at ±VDC . Saturation may be useful bining the eight basic 3-D space vectors.
when the maximum output from the VSI is desired and
harmonic distortion is not a problem. If extremely satu-
3.1 Output voltage synthesis
rated outputs are not desired a special care must be taken
to handle saturation situations with the 2-D SVPWM. √ In section 2 it was shown how voltages are synthesized
When V ~ ∗ lies outside the circle of radius 1/ 2 one at the outputs of the VSI by combining adjacent voltage
have ∆T 1 + ∆T 2 > ∆T . References (Holtz 1992, Holtz space vectors. For a given reference vector V ~ ∗ the 3-D
et al. 1992) study the occurrence of saturation and pro- SVPWM, similarly to the 2-D SVPWM, combines basic
pose solutions for this problem. A simple solution to space vectors to form the desired output voltages. However
avoid excessive saturation and keep ∆T 1 + ∆T 2 ≤ ∆T in the 3-D SVPWM the vector V ~ ∗ is three-dimensional,
is limiting the magnitude of V ~ ∗ to the border of the which means that zero-sequence components must be taken
hexagon of figures 2a and 4b. This is achieved by mak- in account when the modulation algorithm is carried.
 matrix MI,3D is valid for sector I only. For sectors II-VI
matrices MII,3D -MV I,3D are obtained through the same
procedure described by equations (14) and (15).
V2 V7

V1 V6 3.4 Generation of the gate signals

1

0.5
The gate signals S1 -S6 for the VSI switches are ob-
V3 1 tained by the process explained in section 2.5. The 3-D
0 axis

V4
0
0.5 SVPWM employs the same patterns of gate signals used
V5
-0.5 V0 with the 2-D SVPWM. Consequently table 3 is still valid.

xis
0 Fig. 3a shows the pattern of gate signals for sector I. The

αa
-1 -0.5 patterns of gate signals for other sectors may be found
0.8 0.6 0.4 0.2 0 -0.2 by determining the application intervals for the appropri-
-0.4 -0.6 -1
β axis -0.8 ate vectors (according to the sector where the projection of
~ ∗ is situated) and by choosing the correct vector sequence
V
(according to table 3).
Figure 5: The eight basic 3-D voltage space vectors
in the αβ0 space (normalized with reference to VDC ). 3.5 Limitations of the 3-D SVPWM and saturation-mode
operation
The 3-D SVPWM may be used to synthesize balanced
All the eight basic space vectors of table 4 have zero- sinusoidal three-phase voltages. In this case, as it was ex-
sequence components. Vectors V ~0 and V ~7 , which corre- plained earlier for the 2-D SVPWM, the reference vector
spond to null voltages in the 2-D SVPWM, now correspond ~ ∗ is situated on the αβ plane and rotates at constant
V
to zero-sequence components. angular speed.
√ In this situation the maximum magnitude
In the 3-D SVPWM the 3-D vectors are combined to ~ ∗ is 6/4. This imposes to the VSI a maximum out-
of V
form the reference vector V ~ ∗ . This process is similar to put voltage amplitude (under linear operation) about 13%
what is illustrated in fig. 2b. Eq. (2) is also valid for the 3- smaller than that obtained with the 2-D SVPWM. An ob-
D SVPWM however vectors V ~0 and V~7 must be considered vious conclusion is that a three-leg VSI inverter used with
in the vectorial sum because they no longer represent null 3-D SVPWM is not efficient for generating balanced sinu-
voltages. Eq. (2), when applied to the 3-D SVPWM, leads soidal three-phase voltages (2-D SVPWM is more adequate
to eq. (14). for this purpose). Fig. 6a shows the waveforms of the com-
parison levels ta , tb and tc obtained with the 3-D SVPWM
when V ~ ∗ describes a circumference on the αβ plane. One
3.2 Sector identification
should note that there is no 3rd-harmonic injection, on the
In the 2-D SVPWM the 2-D vectors divide the αβ contrary of what happens with the 2-D SVPWM (fig. 4a).
plane in six sectors which form an hexagon. In the 3-D The occurence of 3rd-harmonic components in the com-
SVPWM vectors V ~ 0 -V
~7 are no longer situated on the same parison levels ta , tb and tc with the 2-D SVPWM is due
plane so they do not delimit sectors on the αβ plane. In- to the fact that in this modulation strategy the relation
stead the 3-D basic space vectors form tetrahedrons in the between ∆T 0 and ∆T 7 is fixed (eq. (10) states that ∆T 0
αβ0 space. Reference (Pinheiro, Botterón, Rech, Schuch, and ∆T 7 are equal, although any other relation could have
Camargo, Hey, Gründling & Pinheiro 2002) shows that the been adopted). With the 3-D SVPWM technique the val-
output voltage space is divided into six tetrahedrons. The ues of ∆T 0 and ∆T 7 depend on eq. (15) and may assume
projections of these tetrahedrons on the αβ plane form the any value. √
hexagons of fig. 2a. The 2-D space vectors of fig. 2a are With V ~ ∗ in the form of eq. (3) and A = 6/4 the
the projections of the 3-D space vectors of fig. 5 on the αβ 3-D SVPWM modulator operates in the linear mode for
plane. 0 ≤ m ≤ 1. For m > 1 the modulator enters the satura-
The same algorithm for sector identification studied tion region, which means that the outputs are no longer
in section 2.3 can be applied to the 3-D SVPWM. In this sinusoidal. If the 3-D SVPWM is used to synthesize si-
case, of course, the algorithm does not determine the region nusoidal balanced voltages saturation occurs when the ref-
where the reference vector is located but determines the erence vector V ~ ∗ is excessively large and lies outside the
√
sector where the projections of these vectors on the αβ circumference of radius 6/4 (see fig. 6b). In the worst
plane are located. situation, when the 3-D SVPWM degenerates completely,
the VSI synthesizes square voltage waveforms. The maxi-
3.3 Determination of the application intervals mum achievable fundamental amplitude is the same as that
obtained with the 2-D SVPWM, since both 2-D and 3-D
For V~ ∗ given in the form of eq. (13) the vectorial sum
modulation techniques degenerate to square-wave outputs
of eq. (2) may be written as eq. (14). The row of ones is in the worst situation of saturation.
necessary so that the matrix which contains the basic space Whenever saturation occurs the condition ∆T 1 +
vectors is invertible. ∆T 2 > ∆T becomes true. (However the equality ∆T 1 +
~ ∗ = [v ∗ v ∗ v ∗ ]T ∆T 2 +∆T 0 +∆T 7 = ∆T is still valid because ∆T 0 and ∆T 7
V α β 0 (13)
assume negative values when saturation occurs.) Eq. (12)
  is a simple way to resize the application intervals so that
· ¸ ∆T 1 · ∗¸ ∆T 0 = ∆T 7 = 0 and ∆T 1 + ∆T 2 = ∆T , but this works
~1
V ~2
V ~0
V ~7  ∆T 2 
V ~
V
 ∆  = ∆T (14) well only when the reference vector is located on the αβ
1 1 1 1 T0 1
∆T 7 plane (i.e. when the reference vector has no zero-sequence
component). If the 3-D SVPWM is used to synthesize
 q  −1
  2 √1
0 0  ∗ non-sinusoidal voltages or unbalanced sinusoidal voltages
∆T 1 3 vα
 1
6  ∗ eq. (12) will make the outputs of the VSI be distorted be-
 ∆T 2   0 √ 0 0   vβ 
 ∆  = ∆T 
 2 √ √   v ∗ (15) cause the intervals ∆T 0 and ∆T 7 are not correctly taken
T0 − √1 1 3 3
√ − 2 2
 0
in account. As a consequence vectors V ~0 and V ~7 are not
∆T 7 2 3 2 3 1
1 1 1 1 properly applied, which results in unexpected distortion at
| {z }
MI,3D the outputs of the VSI. It is rather complicated to handle
saturation situations with the 3-D SVPWM. It seems that
Evidently equations (14) and (15) are valid only for the most appropriate way to solve this problem is to allow
~ ∗ situated in sector I. Consequently
a reference vector V the existence of negative values for ∆T 0 and ∆T 7 , permit
 500 van
van*

[V]
0

V*
6
−500

β axis
∆T 4
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
2 ta tb tc region of
linear operation 500 vbn
vbn*

[V]
0

ω
α axis −500
(a) (b) 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

500 vcn
Figure 6: (a) Waveforms of the comparison levels ta , vcn*

[V]
0
tb and tc for linear operation with sinusoidal outputs.
(b) Locus of V ~ ∗ for maximum output under linear
√ −500
operation (A = 6/4 , m = 1). 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
[s]

∆T 1 +∆T 2 > ∆T and limit the resulting comparison levels

Figure 8: Synthesized three-phase voltages - open-
ta , tb and tc in the scope of the 3-D SVPWM algorithm. loop control.
If these levels are limited to a range between 0 and ∆T /2
(which is the range of values that the up-down counter may vCa
assume) the generated phase-to-neutral voltages will ap-
pear saturated at ±VDC /2 but remain undistorted within vCb
AC
the range between −VDC /2 and +VDC/2 . load
source
vCc
4 Application examples vn

This section shows application examples of the 3-D 3-leg VSI

+
SVPWM algorithm with the three-leg VSI (with neutral
connection) of fig. 1.
VDC
{ +
v0 voltage
compensator
vCa* vCb* vCc*
S1 - S 6
4.1 Open-loop synthesis of voltage waveforms
va* vb* v0* vCa
3-D SVPWM voltage vCb
Fig. 7 shows a three-leg inverter used to synthesize
modulator controller vCc
generic voltage waveforms with a 3-D SVPWM modulator.

vn
3-leg VSI
va
+ Y
VDC
{ + v0
vb
vc
load
S 1 - S6
voltage
references
3-D SVPWM va* vb* v0*
modulator
Figure 7: Voltage synthesis with 3-D SVPWM.
Fig. 8 shows simulated results obtained with the
scheme of fig. 7. Voltages van , vbn and vcn are superim-
posed with their respective reference waveforms. Because
VDC = 500V the outputs are saturated at ±250V .
4.2 Closed-loop synthesis of voltage waveforms
The generation of voltage waveforms in series com-
pensators require the use of the 3-D SVPWM with closed-
loop control. Fig. 9 shows the scheme of a series voltage
compensator. The voltage controller and the 3-D SVPWM
modulator synthesize voltages at the outputs of the trans-
formers that are connected in series with the electric system
lines.
The series compensator works as a voltage regula-
tor which is capable to eliminate distortions of the volt-
ages delivered to the load by the AC source. The volt-
age compensator determines what voltages must be synthe-
sized according to the purposes of the series compensation.
The voltage controller supplies reference signals to the 3-
D SVPWM modulator so that the desired compensation
voltages vCa , vCb and vCc are obtained.
The series voltage compensator of fig. 9 was simulated
with 1:1 coupling transformers. The voltage controller was
Figure 9: Series compensator with 3-D SVPWM.
based on αβ0 coordinates and was composed of three pro-
portional and integral regulators. The compensation volt-
ages vCa , vCb and vCc are shown in fig. 10.
4.3 Closed-loop synthesis of current waveforms
Fig. 11 shows the 3-D SVPWM technique employed in
a shunt current compensator. The VSI together with the
coupling inductors Lf and the current controller constitute
a controlled current source. It was said that the VSI with
3-D SVPWM may synthesize voltages without closed-loop
control. For the synthesis of currents, on the other hand,
closed-loop control is mandatory.
In fig. 11 the current compensator determines the form
of the currents that must be synthesized to achieve the de-
sired compensation purposes. The current controller uses
the reference currents and the measured currents to achieve
the closed-loop control and generate the voltage references
for the 3-D SVPWM modulator.
Fig. 12 shows the results of the simulation of the
scheme of fig. 11. The phase and neutral currents synthe-
sized by the shunt compensator are shown in this figure.
5 Conclusions
The understanding of the 3-D SVPWM technique is
very relevant because applications such as series and shunt
compensators for three-phase four-wire systems require an
appropriate modulation technique for the synthesis of volt-
ages and currents. This paper has presented a detailed
analysis of the 3-D SVPWM for three-leg four-wire voltage
source inverters. Theory, operation, implementation and
applications have been discussed. The authors hope that
 50 5
v
Ca iCa
vCa*
iCa*

[A]
0
[V]
0

−5
−50 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
5
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
i
Cb
iCb*

[A]
50 v 0
Cb
vCb*
−5
[V]

0 0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
5
iCc
−50 i *
Cc

[V]
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0

50 vCc −5
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
vCc*
5
iCn
[V]

[A]
0

−50
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 −5
0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
[s]
[s]

Figure 10: Voltages synthesized by the three-phase Figure 12: Phase currents (iCa , iCb and iCc ) and
series compensator - closed-loop control. neutral current (iCn ) synthesized by the three-phase
shunt compensator - closed-loop control.
AC
Y load
source
vn
L Verdelho, P. & Marques, G. D. (1998). Four-wire current-
iCn
current regulated pwm voltage conveter, IEEE Transactions on
iCa iCb iCc compensator Industrial Electronics 45(5): 761–770.
Zhan, C., Arulampalam, A. & Jenkins, N. (2003). Four-wire
3-leg VSI

+
dynamic voltage restorer based on a three-dimensional
v0
+ { VDC
iCa
iCb
iCa*
iCb*
voltage space vector pwm algorithm, IEEE Transactions
on Power Electronics 18(4): 1093–1102.
iCc iCc* Zhan, C., Arulampalam, A., Ramachandaramurthy, V. K.,
S1 - S 6 Fitzer, C., Barnes, M. & Jenkins, N. (2001). Novel volt-
va* vb* v0* age space vector pwm algorithm of 3-phase 4-wire power
3-D SVPWM current conditioner, IEEE Power Engineering Society Winter
modulator controller Meeting 3: 1045–1050.
Zhang, R., Prasad, V. H., Boroyevich, D. & Lee, F. C. (2002).
Three-dimensional space vector modulation for four-leg
Figure 11: Shunt current compensator. voltage-source converters, IEEE Transactions on Power
Electronics 17(3): 314–236.

this work has contributed for the understanding of the 3-D

SVPWM technique for three-leg inverters.

Acknowledgment

The authors are grateful to FAPESP - Fundação de

Amparo à Pesquisa do Estado de São Paulo - for the finan-
cial support.

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