439 South 4th St Apt 10

San Jose, CA-95112

Contact no: (408)759 1338
Mail:
Professional Objective:
Seeking a position to utilize my skills and abilities as an ASIC Design/Verifica
tion Engineer that offers professional growth while being resourceful, innovativ
e and flexible
Academic Qualification:
MS in Electrical Engineering, San Jose State University, CA, May 2010. GPA 3.5/4
.0
BS in Electrical Engineering Mumbai University, Mumbai, India, Jan 2007
Coursework:
Semiconductor Devices
Digital System Design and Synthesis
CMOS ASIC Design
SOC and System Verilog concepts
Digital Signal Processing
Skills:
Languages: Verilog, C, Python
Design Tools: Cadence Schematic and Virtuoso, ModelSim, VCS
Verification: System Verilog
Operating Systems: UNIX, Windows
* Hands on experience with 8051 Microcontroller
* Good knowledge about ARM processors
* Hands on experience with test instruments like oscilloscopes
* Good knowledge of Static Timing analysis (STA)
* Good understanding of OVM verification methodology
Project Summary:
* Design of a Low cost direct RF PSK demodulator using PLL, August 2009 - May 2
010
Design, schematic and Layout of PLL, using a differential VCO and CML divider, i
n CMOS 0.18? TSMC technology locking at 433.93MHz ISM bandwidth and Verilog A co
ding for a Finite state machine as well as NRZ, bit unstuffing and framing of th
e data output
* Design of Phase Locked Loop, August 2009 - December 2009
Designed a phase locked loop in CMOS 0.13?m TSMC technology. The PLL locked the
reference at a natural frequency of 2GHz with a tuning frequency range of 250MHz
. The design of the VCO was achieved using CMOS differential ring oscillator

* ATM switching using System Verilog, January 2009 - May 2009

System Verilog was used for verification of the ATM switching SOC with assertion
and functional coverage based verification on VCS as well as ModelSim tool
* 64-bit Adder that drives a load of 20fF, Jan 2009 - May 2009
Design schematic of a 64bit 5 stage Carry look Ahead adder in CMOS 45 nm TSMC te
chnology and performing Layout and LVS
* Analysis of Area-Delay and Power-Delay Tradeoffs in Addition Circuits, August
2008 -December 2008
RTL Design and comparative study including Timing Analysis for 8,16,32,64 bit Ri
pple carry adders and Carry look-ahead adders using Verilog coding using VCS and
for synthesis used the Toshiba library
* Circuit simulation for a Confuzer to Unconfuzer circuit with the concept of t
he Networking Cryptography, August 2008 - December 2008
Implemented and tested the Unconfuzer circuit with test-bench with CRC in Verilo
g also done in VCS