8 Registers and Memory

Clocked sequential circuits: a group of flip-flops and combinational gates

 a feedback path
Without flip-flops  no feedback

Resister: a group of flip-flops

n bit resister: a group of n flip-flops capable of storing n bits of binary
information, in addition, gates that effect their transition
Flip-flops: hold the binary information
Gates: determine how the information is transferred to the resister

Counter: a resister that goes through a predetermined sequence of states

(Gates produce the prescribed sequence of binary states)

2010-05-30 ASIC LAB 1

 Registers
Register- a group of binary cells suitable for holding binary information.
4 bit register: only four D flip-flops
 Only flip flops without any gates

Positive edge triggered

- Clock=1; input information transferred
- Clock=0; unchanged
- Clear=0; clearing the register to all 0’s prior to its
clocked operation.
During normal clocked operation, R inputs must be
maintained at logic 1

0  all flip-flops are reset asynchronously

2010-05-30 ASIC LAB 2
Register with parallel load
Clock pulses are applied to the C inputs at all times
Load input determines whether the next pulse will accept new information or leave the
information in the register inact
Master clock: acts like a pump that
supplies a constant beat to all parts of
the system
Loading the register: transfer of
new information (a separate control signal to
decide which specific clock pulse will have an
effect on a particular register)
 Parallel loading: all the bits of the register are
loaded simultaneously with a common clock pulse
Uneven propagation delays by gates: between
master clock and input of D flip-flop : Load
input determines the action to be taken with each
clock pulse
- Clock=1; input information  loading

- Clock=0; the content of the register

 unchanged

- Load input=1; the I inputs are

transferred into the register

- Load input=0; maintain the content

of the register
2010-05-30 ASIC LAB 3
 Shift registers
Shift register: capable of shifting its binary information in one or both directions,
a chain of flip-flops in cascade
All flip-flops receive common clock pulses, which activate the shift from one stage to
the next

Serial input determine what goes into the leftmost flip-flop during the shift
Serial output taken from the output of the rightmost flip-flop

2010-05-30 ASIC LAB 4

Serial transfer To prevent the loss
of information stored
in the source register

In a serial mode: when information

is transferred and manipulated one bit
at a time
In a parallel mode: all the bits of the
register are transferred at the same
time

Shift control signal is synchronized with

the clock and changes value just after
the negative edge of the clock
Each rising edge of the pulse causes a
shift in both registers

2010-05-30 ASIC LAB 5

Serial-transfer example
Timing pulse Shift register A Shift register B Serial output of B

Initial value 1011 0010 0

After T1 1101 1001 1

After T2 1110 1100 0
After T3 0111 0110 0
After T4 1011 1011 1
The content of A is transferred into B,
while the content of A remains unchanged

2010-05-30 ASIC LAB 6

Serial addition
For storing sum Operation
- A register  augend,
B register  addend, carry  0
- SO of A and B provide a pair
of significant bits for the FA
- Output Q gives the input carry
at z
- Shift-right control enables
both registers and the carry flip-
flop.
- Sum bit from S enters the
leftmost flip-flop of A

2010-05-30 ASIC LAB 7

State table for serial adder
Present value of carry
Output carry

JQ = xy
KQ= x' y=' ( x + y)' By k-map
S = x ⊕ y ⊕Q

2010-05-30 ASIC LAB 8

 Second form of serial adder

JQ = xy
KQ= x' y=' ( x + y)'
S = x ⊕ y ⊕Q
The output S is a function not only of x and y, but also of the present state of Q.
The next state of Q is a function of the present state of Q and the values of x
and y that come out of the serial outputs of the shift registers
2010-05-30 ASIC LAB 9
 1. Clear control to clear register to 0

Universal shift register 2. Clock input to synchronize the

operations
 Shifts and parallel load capabilities 3. Shift-right control to enable the
shift right operation and the serial
Unidirectional shift register: one direction input and output lines associated
Bidirectional shift register: both directions with the shift right
4. Shift-left control to enable the
shift left operation and the serial
input and output lines associated
with the shift left
5. Parallel-load control to enable a
parallel transfer and the n input
lines associated with the parallel
transfer
6. n parallel output lines
7. A control state that leaves the
information in the register
unchanged in the presence of the
clock

- S1, S0 -> 0, 0; No change

- S1, S0 -> 0, 1; Shift right
- S1, S0 -> 1, 0; Shift left
- S1, S0 -> 1, 1; Parallel load

2010-05-30 ASIC LAB 10

 Memory
Memory: a collection of cells capable of storing a large quantity of
binary information
Write operation: The process of storing new information into memory
Read operation: The process of transferring the stored information out of memory
RAM (random access memory): read and write operation
ROM (read only memory): only read operation
 a suitable binary information is already stored inside the memory which can be
retrieved or read at any time (it cannot read)

Programmable Logic Device  binary information stored within a PLD is

specified in some fashion and then embedded within the hardware
(programming: a hardware procedure)
PLD (programmable logic device)
 IC with internal logic gates that are connected through electronic
paths that behave similar to fuses
 Programming: blowing those fuses along the paths to obtain the
particular configuration of the desired logic function
PLA (programmable logic array)
PAL (programmable array logic)
FPGA (field programmable gate array)
2010-05-30 ASIC LAB. 11
 Random-access memory (RAM)
The time it takes to transfer information to or form any desired random location
is always the same
1024x16 Memory
Capacity of 1K words of 16 bit
each

into memory

out of memory

- Memory stores binary information in

groups of bits (Most computer word:
multiples of bytes in length) cf. 32 bit word:
4 bytes
- 8 bits = 1 byte
The 1K x 16 memory has 10 bits in
- The address lines select one particular the address and 16 bits in each word.
word.
K: 210, M: 220, G: 230 (cf. 64K=216)
- A decoder inside the memory accepts
this address and opens the paths needed 64K x 10 memory
to select the word specified.  16 bit in address and 10 bit in12
word
2010-05-30 ASIC LAB.
2k ≥ m, where m is the total number of words, k is the number of address bits needed
to satisfy the relationship

Write and read operations

- Write operation
1. Transfer the binary address of the desired word to the address lines.
2. Transfer the data bits that must be stored in memory to the data
input lines
3. Activate the write input

- Read operation
1. Transfer the binary address of the desired word to the address lines.
2. Activate the read input.

2010-05-30 ASIC LAB. 13

 Memory is controlled by an external device
such as a CPU
Timing waveforms CPU: central processing unit
CPU clock freq: 50 MHz
CPU: has own clock
Memory: does not internal clock,
but is specified by control input

Access time: required to select

a word and read it Low level: write

Cycle time: required to complete

a write operation

CPU memory control signals

to synchronized its internal clock
operations with read and write
operations
Access time and cycle time
high level: read
within a time to a fixed number
of CPU clock cycle
Assume a memory’s access time
and cycle time does not exceed 50 ns CPU transfer the data into one of its internal registers during the
negative transition of T3

2010-05-30 ASIC LAB. 14

 Types of memories

- Random access Memory -each word occupy one particular

location.the access time is always the same, ex) CD
-Sequential access Memory-information is read out only when
the required word has been reached. the access time is variable.
Ex) magnetic tape or disk
- Volatile -Memory units lose the stored information when power is
turned off, RAM
- Nonvolatile-A nonvolatile memory retains its stored information
after removal of power. ex) magnetic disk ,ROM (Read Only Memory)
- Static RAM-The stored information remains valid as long as
power is applied to the unit. Static RAM is easier to use and
has shorter read and write cycles. (SR latches)
- Dynamic RAM-The binary information is stored in the form of
electric charges on capacitors. The capacitors must be periodically
recharged by refreshing the dynamic memory. Dynamic RAM offers
reduced power consumption and larger storage capacity (Capacitors)
2010-05-30 ASIC LAB. 15
Memory decoding
To select the memory word specified by the input address
RAM of m words and n bits per word consists of m x n binary storage cells

1: read
0: write

- The equivalent logic of a binary cell that stores one bit of

information
- The binary cell stores one bit in its internal flip-flop
- It has three inputs and one output. The read/write
input determines the cell operation when it is selected.

2010-05-30 ASIC LAB. 16

 In general,
2k words
n bit per word
Internal construction k address lines  k x 2k decoder

k=2 - It has 16 binary cells

-Memory enable=0; all
outputs of the decoder =0,
none of the memory words
are selected.
- Memory enable=1; one of
the four words is selected.
1: selected The read/write input
0: all outputs of the decoder 0 determines the operation.
- During the read operation,
the four bits of the selected
word go through OR gates to
the output terminals.
- During the write operation,
the data available in the input
lines are transferred into the
four binary cells of the
selected word.

2010-05-30 ASIC LAB. 17

 Coincident decoding
Cf. k x 2k decoder
 2k AND gates with k inputs per gate - The basic idea in two-
dimensional decoding is to arrange
k=5 input decoder the memory cells in an array that is
close as possible as square. In this
Single k=10 input decoder: configuration, two k/2-input
10 x 210 decoders are used instead of one
 Two k=5 (10/2) input decoder
k-input decoder.
- In the two-decoder case,we need
k=5 input decoder
64 AND gates with five inputs in
each.

- If the word address is 404,

X=01100 (12) and Y=10100(20).

Reduce the total number of gates and the number of inputs

per gate
2010-05-30 ASIC LAB. 18
 Address multiplexing
- SRAM (Fig. 7-5)  6 transistors
256
- DRAM  1 MOS Transistor + 1 capacitor
DRAM typically have four times the
density of SRAM (Cost per bit of DRAM
storage is three to four times less than
SRAM), low power requirement of DRAM
 DRAM: 64 K to 256 Mbits
- Most DRAMs 1 bit word size  several
chips combined to a larger word size

- To reduce the number of pins in the IC

package, designers utilize address
256 multiplexing whereby one set of address
input pins accommodates the address
components.
- Since the same set of pins is used for
both parts of the address, the size of the
package is decreased significantly.
256 x 256 = 28 x 28 = 64 K
2010-05-30 ASIC LAB. 19
 Read-only memory
ROM= Decoder + OR gates
- permanent binary information is stored.

No write operation
No data inputs

Programmable connection
between to lines (cross point)
k input lines and n output lines a switch
Number of output lines (n) = number of Fuse: blown or opened by applying
bits per word a high voltage pulse into the fuse
ROM = AND gates connected
as a decoder + a number of
OR gates
32 words
5 X 32 decoder has 32 AND
gates and 5 inverters.
32x8 = 256
Internal connection
2010-05-30 ASIC LAB. 20
 ROM truth table (Partial)

Each address has a word of 8 bit

0: no connection
1: connection
2010-05-30 ASIC LAB. 21
 Combinational circuit implementation

‘1’ connection (intact)

‘0’: blown
A7(I4,I3,I2,I1,I0)= Sum of
minterms (0,2,3,…,29)

Input of ROM 
00011(3)
All the outputs of the
decoder except for
output 3  all ’0’
Output  10110010

2010-05-30 ASIC LAB. 22

 Example

2010-05-30 ASIC LAB. 23

 Types of ROMs
The required paths in a ROM may be programmed in four different ways
1) For large quantities, mask programming is economical.
Mask programming: by the semiconductor company during the last
fabrication process of the unit

2) PROM - irreversible and permanent

For small quantities, programmable read-only memory (PROM) is more
economical. (all ‘1’s)

3) EPROM (Erasable PROM)- can be restructured to the initial value (UV

light  discharge)

4) EEPROM (Electrically erasable PROM)- can be erased with electrical

signals instead ultra violet light. 0

2010-05-30 ASIC LAB. 24

 HDL for combinational circuit

Modeling techniques:
 Gate level modeling
 Instantiation of gates and user defined modules
 Dataflow modeling
 Using continuous assignment statements-assign
 Behavioral modeling
 Using procedural assignment statements-always

25
 Gate-level modeling
Circuit is specified by its gates and their
interconnection

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Instantiation

27
Instantiation in 4-bit adder

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 Dataflow modeling

Assign a value to a
net by using
operands and
operators
eg)J=01,K=10 can be
{J,K}=0110

out=x ? A : B means
out=A, if x is true
=B, if x is false

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 Assignment
2-to-4 line decoder

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4-bit adder

31
 Behavioral modeling

Use procedural assignment

statement,always
Target output
must be the reg
data type

Eg)4 to 1 line mux

32
 Writing a simple test bench

Test bench : Applying stimulus to test HDL

and observe its response
reg - inputs , wire - outputs

33
 System tasks

System tasks : keywords that can display

various outputs (begin with $)
$display , $write , $monitor , $time , $finish
Format of system tasks
 Task name(format specification,argument list);
 Eg) $monitor(%d %b %b, C,A,B);

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Example of testbench

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