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Features of FET
An important feature of the FET is simpler to fabricate and occupies less space on the
chip than BJT. Resulting component density can be extremely high, often exceeding
100,000 MOSFETs per chip.
A second desirable property is that MOS devices can be connected as resistors and
capacitors. This makes possible the design of system consisting exclusively of
MOSFETs and no other components. Exploiting these features makes MOSFETs
dominant device in very large-scale integrated circuits (VLSI) systems.
FET is a majority carrier device. Its operation depends on the use of an applied
electric field to control device current. Thus FET is a voltage controlled current
source.
Depletion MOSFET
Enhancement MOSFET
1. Depletion MOSFET
This device has maximum current at zero gate voltage and fixed drain voltage and
then current decreases with applied gate potential of proper polarity.
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Field Effect Transistor (FET)
For a depletion NMOS transistor, the channel conducts even if VGS =0.
If the value of VGS is positive, the channel is further enhanced. That is, more
free electrons are attracted to the channel, and its conductivity increases.
If the VGS is negative, free electrons are repelled from the channel. The
conductivity of the channel is thus decreased. We call this phenomenon
channel depletion.
If the value of the VGS is sufficiently negative, all of the free electrons in the
channel will be repelled-the channel is said to be completely depleted.
Thus, the negative value of VGS at which the channel is completely depleted is
the threshold voltage Vt for a depletion NMOS device. In other words, to have
a conducting channel, the gate-to-source voltage VGS must be greater than the
threshold voltage Vt.
VGS > Vt
VGS - Vt >0
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Field Effect Transistor (FET)
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Field Effect Transistor (FET)
Enhancement MOSFET
This device exhibits no current at zero gate voltage and the magnitude of the output
current increases with an increase in the magnitude of the gate potential.
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Field Effect Transistor (FET)
device is also called the insulated-gate field effect transistor (IGFET). This layer results in
an extremely high input resistance (1010 to 1015) for the MOSFET.
Biased NMOS enhancement transistor showing induced channel is given below with VDS=0
and VDS>0
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Field Effect Transistor (FET)
The positive voltage applied to the gate establishes electric field which is directed
perpendicular through oxide. This filed induces negative charges near the
semiconductor surface.
Since p-type substrate contains very few electronics, the positive surface charges are
primarily electrons obtained from the n-type source and drain.
These mobile charges form an inversion layer. Such inversion layer is formed only if
VGS exceeds a threshold level VT (ie., VGS> VT)The induced charges beneath the oxide
constitute an n-channel.
As the voltage on the gate increases beyond VT, the number of induced negative
charges in the semiconductor increases. Consequently, the conductivity of the channel
increases.
Application of a positive potential between drain and source produce current in the
induced channel between drain and source.
Hence drain current is enhanced by positive gate voltage and device is called an
enhancement type MOSFET.
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Field Effect Transistor (FET)
Output characteristics
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Field Effect Transistor (FET)
Early voltage
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Field Effect Transistor (FET)
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