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(IJACSA) International Journal of Advanced Computer Science and Applications,

Vol. 2, No. 5, 2011

FPGA-Based Design of High-Speed CIC Decimator

for Wireless Applications

Rajesh Mehra Rashmi Arora

ECE Department, M.E. Student, ECE Department,
National Institute of Technical Teachers„ Training & National Institute of Technical Teachers„ Training &
Research Research
Chandigarh, India Chandigarh, India

Abstract— In this paper an efficient multiplier-less technique is performed in SDR, including advanced compression
presented to design and implement a high speed CIC decimator algorithms, power control, channel estimation, equalization,
for wireless applications like SDR and GSM. The Cascaded forward error control, adaptive antennas, rake processing in a
Integrator Comb is a commonly used decimation filter which WCDMA (wideband code division multiple access) system and
performs sample rate conversion (SRC) using only protocol management.
additions/subtractions. The implementation is based on efficient
utilization of embedded LUTs of the target device to enhance the Today‟s consumer electronics such as cellular phones and
speed of proposed design. It is an efficient method used to design other multi-media and wireless devices often require digital
and implement CIC decimator because the use of embedded signal processing (DSP) algorithms for several crucial
LUTs not only increases the speed but also saves the resources on operations[5] in order to increase speed, reduce area and power
the target device. The fully pipelined CIC decimator is designed consumption. Due to a growing demand for such complex DSP
with Matlab, simulated with Xilinx AccelDSP, synthesized with applications, high performance, low-cost Soc implementations
Xilinx Synthesis Tool (XST), and implemented on Virtex-II based of DSP algorithms are receiving increased attention among
XC2VP50-6 target FPGA device. The proposed design can researchers and design engineers. Although ASICs and DSP
operate at an estimated frequency of 276.6 MHz by consuming chips have been the traditional solution for high performance
considerably less resources on target device to provide cost applications, now the technology and the market demands are
effective solution for SDR based wireless applications.
looking for changes.
Keywords- CIC; FPGA; FPGA; GSM; LUT; SDR. On one hand, high development costs and time-to-market
factors associated with ASICs can be prohibitive for certain
I. INTRODUCTION applications while, on the other hand, programmable DSP
The widespread use of digital representation of signals for processors can be unable to meet desired performance due to
transmission and storage has created challenges in the area of their sequential-execution architecture [6]. In this context,
digital signal processing [1]. The applications of digital FIR embedded FPGAs offer a very attractive solution that balance
filter and up/down sampling techniques are found everywhere high flexibility, time-to-market, cost and performance.
in modem electronic products. For every electronic product,
The digital signal processing application by using variable
lower circuit complexity is always an important design target
sampling rates can improve the flexibility of a software defined
since it reduces the cost [2]. There are many applications where
radio. It reduces the need for expensive anti-aliasing analog
the sampling rate must be changed. Interpolators and
filters and enables processing of different types of signals with
decimators are utilized to increase or decrease the sampling
different sampling rates. It allows partitioning of the high-
rate. This rate conversion requirement leads to production of
speed processing into parallel multiple lower speed processing
undesired signals associated with aliasing and imaging errors.
tasks which can lead to a significant saving in computational
So some kind of filter should be placed to attenuate these errors
power and cost. Wideband receivers take advantage of multi-
rate signal processing for efficient channelization and offers
Recently, there is increasingly strong interest on flexibility for symbol synchronization.
implementing multi-mode terminals, which are able to process
different types of signals, e.g. WCDMA, GPRS, WLAN and II. CIC DECIMATORS
Bluetooth. These versatile mobile terminals favor simple First, confirm that you have the correct template for your
receiver architectures because otherwise they‟d be too costly paper size. This template has been tailored for output on the
and bulky for practical applications [4]. The answer to the US-letter paper size. If you are using A4-sized paper, please
diverse range of requirements is the software defined radio. close this file and download the file for “MSW A4 format”.
Software defined radios (SDR) are highly configurable
hardware platforms that provide the technology for realizing The Cascaded Integrator Comb (CIC), first introduced by
the rapidly expanding digital wireless communication Hogenauer, presents a simple but effective platform for
infrastructure. Many sophisticated signal processing tasks are implementation of decimations. It is a commonly used

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(IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 2, No. 5, 2011

decimation filter which performs sample rate conversion (SRC) When we build a CIC filter, we cascade, or chain output to
using only additions/subtractions. It then has experienced some input, N integrator sections together with N comb sections.
modifications toward improvements in power consumption and This filter would be fine, but we can simplify it by combining it
frequency response [7]-[8]. with the rate changer. Using a technique for multi-rate analysis
of LTI systems from [13], we can “push" the comb sections
It consists of two main sections: an integrator and a comb, through the rate changer, and have them become at the slower
separated by a down-sampler [9]-[10]. An integrator is simply a sampling rate fs/R.
single-pole IIR filter with a unity feedback coefficient:
y[n]  x[n]  x[n  M ] (5)
y[n]  y[n  1]  x[n] (1)

The transfer function for a CIC filter at fs is

This system is also known as an accumulator. The transfer
function for an integrator on the z-plane is H ( z )  H IN ( z ) H CN ( z )
1 (1  z  RM ) N RM 1
H I ( z)  (6)
1  z 1
H ( z) 
(1  z )1 N
 ( 
k 0
z k ) N

The power response of integrator is basically a low-pass

filter with a -20 dB per decade (-6 dB per octave) rolloff, but This equation shows that even though a CIC has integrators
with infinite gain at DC [11]. This is due to the single pole at z in it, which by themselves have an infinite impulse response, a
= 1; the output can grow without bound for a bounded input. In CIC filter is equivalent to N FIR filters, each having a
other words, a single integrator by itself is unstable and shown rectangular impulse response. The CIC filter has a high pass-
in Figure 1 band droop and a low stop-band attenuation, which can be
improved by increasing the number of the cascaded CIC filters
[14]. Sharpening based methods generally improve both the
pass-band and the stop-band characteristic of the CIC filter at
an expense of the increased complexity [15].
Since all of the coefficients of these FIR filters are unity,
and therefore symmetric, a CIC filter also has a linear phase
response and constant group delay [16]. The magnitude
response at the output of the filter can be shown to be:
Figure 1. Basic Integrator
A comb filter running at the high sampling rate, fs, for a H( f )  (7)
rate change of R is an odd symmetric FIR filter described by
y[n]  x[n]  x[n  RM ] (3)
By using the relation sin x  x for small x and some
Where M is a design parameter and is called the differential algebra, we can approximate this function for large R as
delay. M can be any positive integer, but it is usually limited to
1 or 2. The corresponding transfer at fs 1
H ( f )  RM for 0  f  (8)
 RM MF M
H c ( z)  1  z (4)
We can notice a few things about the response. One is that
the output spectrum has nulls at multiples of f = 1/M. In
When R = 1 and M = 1, the power response is a high-pass addition, the region around the null is where aliasing/imaging
function with 20 dB per decade (6 dB per octave) gain (after occurs. If we define fc to be the cutoff of the usable passband,
all, it is the inverse of an integrator). When RM ≠ 1; the power then the aliasing/imaging regions are at
response takes on the familiar raised cosine form, with RM
cycles from 0 to 2π. The basic comb is shown in Figure 2. (i  f c )  f  (i  f c ) (9)
1 M
for f  and i = 1, 2,……[R/2]. If f c  ,
2 2
then the maximum of these will occur at the lower edge of
the first band, 1-fc. The system designer must take this into
consideration, and adjust R, M, and N as needed. Another thing
we can notice is that the passband attenuation is a function of
the number of stages. As a result, while increasing the number
Figure 2. Basic Comb

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(IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 2, No. 5, 2011

of stages improves the imaging/alias rejection, it also increases as shown in Figure 5 The complete Matlab to AccelDSP design
the passband “droop." flow is shown in Fig6.
In this proposed work fully pipelined 3-stage CIC
decimator is designed using Matlab and Xilinx AccelDSP by
taking filter R as 8 and M as 2.
Figure 5. CIC Decimator

Figure 6. AccelDSP Design Flow

The proposed design shows an efficient realization of CIC

decimator by using embedded LUTs of target FPGA to provide
Figure 3. Floating Point Output of CIC Decimator high speed operation. The multiplier less LUT based technique
consist of input registers, 4-input LUT unit and
The Matlab based floating point output of proposed design shifter/accumulator unit as shown in Fig7.
is shown in Fig 3. Then the equivalent fixed point file is
generated and verified by AccelDSP whose output is shown in
Fig4. The red wave shows the input sequence, green wave
shows the ideal response and blue plot is the output from CIC

Figure 7. LUT based Multiplier Less Implementation


To observe the speed and resource utilization, RTL is
generated, verified and synthesized. The proposed CIC
decimator filter is implemented on Virtex-II Pro based
XC2VP50-6 target device using fully pipelined LUT based
Figure 4. Fixed Point Output of CIC Decimator multiplier less technique. The resource utilization of proposed
implementation is shown in table I.
The 3 stage CIC decimator is designed to accomplish three
things here. First, we have slowed down half of the filter and TABLE I. VIRTEX-II PRO BASED RESOURCE UTILIZATION
therefore increased efficiency. Second, we have reduced the
number of delay elements needed in the comb sections. Third,
and most important, the integrator and comb structure are now
independent of the rate change. This means we can design a
CIC filter with a programmable rate change and keep the same
filtering structure. A CIC decimator would have N cascaded
integrator stages clocked at fs, followed by a rate change by a
factor R, followed by N cascaded comb stages running at fs/R

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(IJACSA) International Journal of Advanced Computer Science and Applications,
Vol. 2, No. 5, 2011

TABLE II. TRANSPOSED FORM PERFORMANCE EVALUATION [7] F.J.A. de Aquino, C.A.F. da Rocha, and L.S. Resende, “Design of CIC
filters for software radio system,” IEEE International Conference on
Acoustics, Speech, Signal Processing, May 2006.
[8] R. Uusikartano, and J. Takala, “Power-efficient CIC decimator
architecture for fs/4-downconverting digital receivers,” IEEE
International Midwest Symposium on Circuits and Systems, Dec. 2004.
[9] G. Jovanovic Dolecek, S.K. Mitra, “ Efficient Comb-Rotated Sinc (RS)
Decimator With Sharpened Magnitude Response,” IEEE International
XC2VP50-6 FPGA [10] W.A. Abu-Al-Saud, and G.L. Stuber, “Modified CIC filter for sample
rate conversion in software radio systems,” IEEE Signal Processing
Letters, Vol. 10, Issue: 5, pp. 152-154, May 2003.
[11] G.J. Dolecek, and J.D. Carmona, “A new cascaded modified CIC-cosine
decimation filter,” IEEE International Symposium on Circuits and
Systems, May 2005.
[12] M. Becker; N. Lotze et al;"Implementation of a Power Optimized
Decimator for Cascaded Sigma-Delta A/D Converters," in ICSES,
2004,pp. 83-86.
[13] Quan Liu; Jun Gao; “On Design of Efficient Comb Decimator with
Improved Response for Sigma-Delta Analog-to-Digital Converters”,
International Conference on image and signal processing, pp. 1-5, 2009.
[14] G. Jovanovic Dolecek; S.K. Mitra; “Two-stage CIC-based decimator
As shown in table III, the proposed LUT based design can with improved characteristics”, in IET Signal Process., Vol. 4, pp. 22–
work at an estimated frequency of 276.6 MHz as compared to 29, Oct 2010.
156 MHz in case of [3] by using considerable less resources of [15] Alfonso Fernandez-Vazquez, Gordana Jovanovic Dolecek, “Passband
target FPGA. The speed performance of proposed design is and Stopband CIC Improvement Based on Efficient IIR Filter
VOL. 52, NO. 7, JULY 2005.
V. CONCLUSION [16] H. Aboushady; Y. Dumonteix, M. Louerat; and H. Mehrez; “Efficient
polyphase decomposition comb decimation filters in sigma–delta
In this paper, a Xilinx AccelDSP based approach is analog–digital converter,” IEEE Trans. Circuits Syst. II, Analog
presented for a CIC Decimator to minimize the time to market Digit.Signal Process., vol. 48, no. 10, pp. 898–903, Oct. 2001.
factor. The proposed fully pipelined CIC decimator filter is [17] Gordana Jovanovic-Dolecek, Sanjit K. Mitra, “A New Two-Stage
designed by using embedded LUTs of target device. The Sharpened Comb Decimator”, IEEE TRANSACTIONS ON CIRCUITS
results show enhanced performance in terms of speed and area AND SYSTEMS, VOL. 52, NO. 7, JULY 2005.
utilization. The proposed transposed design can operate at an [18] Y. Gao; L. Jia, J. Isoaha; and H. Tenhunen; “A comparison design of
comb decimators for sigma–delta analog-to-digital converters”,
estimated frequency of 276.6 MHz by consuming considerably AnalogIntegr. Circuits Signal Process., vol. 22, no. 1, pp. 51–60, Jan.
less resources available on target device to provide cost 2000.
effective solution for SDR based wireless communication [19] Chakraborty, R. (2011). FPGA Based Cipher Design & Implementation
applications. of Recursive Oriented Block Arithmetic and Substitution Technique (
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REFERENCES Applications - IJACSA, 2(4), 54-59.
[1] Vijay Sundararajan, Keshab K. Parhi, “Synthesis of Minimum-Area
Folded Architectures for Rectangular Multidimensional”, IEEE AUTHORS PROFILE
TRANSACTIONS ON SIGNAL PROCESSING, pp. 1954-1965, VOL. Mr. Rajesh Mehra is currently Assistant Professor at National Institute
51, NO. 7, JULY 2003. of Technical Teachers‟ Training & Research, Chandigarh, India. He is
[2] ShyhJye Jou, Kai-Yuan Jheng*, Hsiao-Yun Chen and An-Yeu Wu, pursuing his PhD from Panjab University, Chandigarh, India. He has
“Multiplierless Multirate Decimator I Interpolator Module Generator”, completed his M.E. from NITTTR, Chandigarh, India and B.Tech. from
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, NIT, Jalandhar, India. Mr. Mehra has 15 years of academic experience.
pp. 58-61, Aug-2004. He has authored more than 15 research papers in reputed International
[3] Amir Beygi, Ali Mohammadi, Adib Abrishamifar. “AN FPGA-BASED Journals and 35 research papers in National and
IRRATIONAL DECIMATOR FOR DIGITAL RECEIVERS” in 9th International conferences. Mr. Mehra‟s interest
IEEE International Symposium on Signal Processing and its areas include VLSI Design, Embedded System
Applications, pp. 1-4, ISSPA-2007. Design, Advanced Digital Signal Processing,
[4] K. B. Huang, Y. H. Chew, and P. S. Chin “A Novel DS-CDMA Rake Wireless & Mobile Communication and Digital
Receiver: Architecture and Performance” IEEE International Conference System Design. Mr. Mehra is life member of ISTE.
on Communications, pp-2904-2908, ICC-2004. rajeshmehra@yahoo.com
[5] D.J. Allred, H. Yoo, V. Krishnan, W. Huang, and D. Anderson, “A
Ms Rashmi Arora received her B.E. Degree with Honors in Electronics
Novel High Performance Distributed Arithmetic Adaptive Filter
& Communication engineering from M.J.P.
Implementation on an FPGA”, in Proc. IEEE Int. Conference on
Acoustics, Speech, and Signal Processing (ICASSP‟04), Vol. 5, pp. 161- Rohilkhand University, Bareilly, U.P., India, in
164, 2004 2002. She is currently pursuing her M.E. degree
from NITTTR, Chandigarh, India. She has 7 years
[6] Patrick Longa and Ali Miri “Area-Efficient FIR Filter Design on FPGAs of academic experience. Her interest areas are
using Distributed Arithmetic”, pp248-252 IEEE International Signal Processing, Embedded Systems and VLSI
Symposium on Signal Processing and Information Technology,2006. Design. Ms. Rashmi is life member of ISTE.

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