A Fully Integrated 74% Efficiency 3.6V to 1.

5V
150mW Capacitive Point-Of-Load
DC/DC-Converter
Tom Van Breussegem and Michiel Steyaert
Katholieke Universiteit Leuven, Dept. Elektrotechniek, afd. ESAT-MICAS
Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
Email: tvanbreu@esat.kuleuven.be

Abstract— Thanks to scaling, CMOS switches and integrated

capacitors have increased in quality and density. This creates new
opportunities in miniaturizing DC/DC-converters by integrating
power drivers, as well as switches and reactive components on a
single die. A 150mW fully integrated capacitive DC/DC-converter,
with Multiphase Single Bound Hysteresis Control is presented.
The converter achieves a peak efficiency of 77% and a full load
efficiency of 74% for an output-input-voltage conversion ratio of
less than 45%. It is the first fully integrated closed-loop operating
converter fabricated in Bulk CM OS achieving these ratings.
In this paper a 150mW fully integrated capacitive DC/DC-
converter with a Multiphase Single-Bound Hysteresis Con-
troller (SBHC) is proposed. Section II analyzes the converter
topology and the control method. Section III discusses the
implementation of the converter and the control loop. Finally
in Section IV the experimental results are presented.

I. I NTRODUCTION
Due to the ever increasing gap between battery voltage
levels and the nominal supply voltages of state-of-the-art
Systems On-Chip, efficient on-chip DC/DC-converters have
become a necessity. Designers are faced with battery voltages
between 4V and 1.2V (Li-Ion and NiMH type of batteries).
But breakdown voltages of the state-of-the-art Deep-Sub-
Micron CMOS technologies are heading towards 1V and
below. Therefore it is very appealing to integrate DC/DC-
converters on-chip as it is shown in Fig. 1.
A few years ago papers started to appear integrating
inductive converters ([1], [2], [3]): the high switching
frequencies enabled the use of small on-chip inductors
(< 1 − 10nH) and on-chip capacitors(< 1 − 10nF ). Due to
the poor quality factor of integrated inductors, the efficiencies
of these converters are low compared with their Voltage
Conversion Ratio (VCR). The VCR is the ratio between
output voltage and input voltage of the DC/DC-converter. The
efficiency of inductive converters is deteriorated by the high
parasitic series resistance of the inductor [1]. Only recently
monolithic capacitive DC/DC-converters are being considered
to fullfill the high efficiency needs of most of the systems. In
contrast to the low quality of integrated inductors, integrated
Metal-Insulator-Metal (MIM) capacitors have relatively small
parasitics. Therefore, DC/DC-converters using nothing but
capacitors and switches, have grown in importance. Not
only because of their possible high efficiency [4] [5], but
also because of their EMI friendly characteristics. The
benefits of fully integrated capacitive DC/DC-converters have
been demonstrated in some low power designs [6] [4] but
have definitely a lot of potential for point of load applications.
Fig. 1. On-chip DC/DC-converter embedded in SOC
II. S YSTEM
A. Converter Topology
Capacitive DC/DC-converters are Variable Structure
Systems (VSS) that transfer charge from the input to the
output by means of capacitors. The single-flying-capacitor
voltage divider is shown in Fig. 2 a). This topology consists
of a charge-transferring capacitor (the flying capacitor Cf ly ),
a buffer capacitor Cout and four switches. The DC/DC-
converter operates in two phases. In phase φ1 , shown in Fig.
2 b), the flying capacitor Cf ly is connected between input
and output. During the second phase φ2 , Cf ly is connected
between the output node and ground (Fig. 2 c)). By switching
between these configurations charge is transferred from the
input to the output.
B. Control Method
Capacitive DC/DC-converters regulate their output voltage
by controlling the amount of charge that is transferred to the
load and to the buffer capacitor Cout . This control is performed
by means of frequency modulation since this method is
extremely beneficial for low-load operation. Under frequency
modulation the switching losses are proportional with the
output power. The frequency modulation is established in this

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Fig. 2. Schematic of the DC/DC-converter topology
work by means of a Single-Bound Hysteresis Controller. This
controller consists of a comparator that triggers the DC/DC-
converter to transfer charge from the input to the output when
the output voltage is lower than a reference/control voltage.
In order to reduce the output ripple at the output of the con-
verter, this technique is combined with a multiphase switching
scheme. Therefore multiple converters will be switched out of
phase. This results in a charge transfer that is smeared out in
time and a significantly reduced ripple is as a result achieved.
In contrast to conventional multiphase switching schemes,
this implementation does not require a DLL [7]. In this way
power consumption is reduced, the multiphase bandwidth is
increased and no additional stability issues are introduced.
The implementation details of the Multiphase Single-Bound
Hysteresis Controller are discussed in Section III-C.
III. I MPLEMENTATION
A. Charge Pump
In Fig. 3 the transistor implementation of the capacitive
DC/DC-converter is depicted. It consists of four switches
M1 − M4 and the flying capacitor Cf ly . The output buffer
capacitor is omitted in this figure. Switches M2 and M4
require a gate swing between ground and the output voltage
rail in the system. M1 and M3 , on the other hand, need a gate
swing between the input voltage and the output voltage. None
of the switches can withstand the full swing input voltage since
they have a oxide breakdown voltage of 2.5V. Level shifters
are used to translate the control signals to the upper voltage
rails. M3 is implemented by means of an triple-well device to
435
Fig. 3. CMOS implementation and timing
isolate the bulk from the substrate. The substrate is biased with
the generated output voltage. Because of this the threshold of
the device is reduced and the conductance increased compared
to the common bulk solution.
By configuring the switches as shown in Fig. 3 the switches
will not be exposed to the high input voltage (3V < Vin <
3.6V ) which is higher than the breakdown voltage of the
switches. This technique was successfully used by the authors
in a voltage doubler that generated an output voltage equal to
twice the breakdown voltage of the devices [4]. For generation
of the level-shifted control signals, a capacitive level shifter
was implemented. This level shifter is discussed in Section III-
B. The converter is implemented in a 90nm CMOS technology
with integrated capacitors. The flying capacitors are high-
quality MIM Capacitors and the buffer capacitor is a MOS-
capacitor.
B. Level shifter
For driving the upper switches M 1 and M 3, an appropriate
level shifter, shown in Fig. 4 a), is required. A Flip Flop,
implemented by means of a crosscoupled inverter pair, is used
to ensure state retention at the input of the powertrain driving
the solid-state switches. The Flip Flop is toggled by means of
a capacitive coupling with the control circuitry at logic supply
level. The capacitor used in this circuit has a capacitance of
100fF. MIMcaps have been used for this purpose.
C. Control Loop
In Fig. 5 the Multiphase Single-Bound Hysteresis Controller
is shown. It consists of a 5-tap current-starved ring oscillator
that generates 5 equally distributed out-of-phase clock signals.
These 5 clock signals are buffered and inverterted so that
10 clocksignals are fed to 10 comparators. These clocked
comparators (shown in Fig. 4 b)) will compare the output
voltage with a control voltage through a resistive divider.
Charge transfer is only desired at the rising edges of the
clock signal. Therefore, a set of Toggle Flip Flops (T-FF) are
inserted after the comparators filtering out the falling edges of
the clocks.
The clocked comparators will be activated subsequently at the
rising edge of their clock signal. So, instead of activating a
single converter each time interval T = f1s , the converter is
fragmented into N equivalent cores. A single core is then
T
activated each time interval N . The current pulses are then
reduced by at least a factor N and so is the ripple voltage
at the output [4]. The clock signals are distributed over the
chip towards the different converter cores, where they are level
shifted and the non-overlapping clocks for the switches are
generated locally as well.
Fig. 4. a) Levelshifter b) Comparator
Fig. 5. Schematic overview of the control loop
IV. M EASUREMENT R ESULTS
In Fig. 6 the key specifications of the DC/DC-converter
are summarized and the next paragraphs will demonstrate
the performance of this converter on behalve of efficiency,
efficiency enhancement and load regulation.
A. Efficiency
The DC/DC-converter (chip photograph shown in Fig. 11)
was measured under various conditions. Efficiency was mea-
sured for input voltages of 3.0V, 3.3V and 3.6V and output
voltage of respectively 1.3V, 1.42V and 1.5V. This shown in
436
Fig. 6. Specifications
in Fig. 7. A peak efficiency of 77.3% is achieved for a voltage
conversion from 3V to 1.3V resulting in an output power of
70mW. The maximum output power for all conversion pairs
was 150mW. From 10mW to 150mW the efficiency remains
higher than 70% for all conversion pairs. To the authors
knowledge [8] achieves a higher power and similar Efficiency
Enhancement Factor (EEF), but is implemented in a 32nm
SOI technology taking advantage of non standard technology
options. Therefore, this design proves that in BULK CMOS
as well high efficiencies can be achieved and power dense
DC/DC-converters can be designed.
A no-load power consumption of 85µA is measured for Vin =
3.3V . Stability is demonstrated from 150mW down to 0µW ,
taken into account that at no load the control loop is drawing
current from the output.
B. Efficiency Enhancement Factor
In [2] a benchmark for switched-mode down converters is
introduced: the Efficiency Enhancement Factor. It compares
the efficiency of a converter ηConv with the maximum effi-
ciency an ideal linear regulator can achieve, ηLDO . The EEF
is formulated in Equation 1 and calculated for the presented
design in Fig. 8 . It is clear that a converter with a negative
EEF can not compete with a linear regulator. The EEF remains
between +39% and +45% over the whole power range from
10mW and 150mW. Compared to an ideal linear regulator, this
design performs at least 39% better, extending battery lifetime
significantly in portable devices.
ηLDO
EEF = 1 − (1)
ηConv
C. Regulation
The load regulation resides between 1Ω and 1.5Ω. In Fig.
9 the output voltage is shown for a current load step of
90mA in case a 3.3V to 1.4V conversion is performed. Figure
10 demonstrates how the Single-Bound Hysteresis control
anticipates on a load variation of 30mA with a rise time of
25ns. This experiments validates the high speed capability of
this control method.
V. C ONCLUSION
In this work the design of a fully integrated capacitive
DC/DC-converter is demonstrated. The converter achieves
 Fig. 7. Efficiency plots in function of output power
Fig. 8. Efficiency Enhancement Factor over the entire power range
Fig. 9. Load Regulation for 90mA load variation Vin = 3.3V Vout = 1.4V
a peak efficiency of 77% and an efficiency of 74% for
a maximum load of 150mW. A Single-Bound Hysteresis
Multiphase control scheme is proposed, which enables
multiphase for low-power solutions and without stability
issues.
The authors thank the Institute for the Promotion of
Innovation through Science and Technology in Flanders for
financial support, H.J. Bergveld, M Meijer and G. Villar from
NXP Semiconductor - Eindhoven for the fruitfull discussion
437
Fig. 10. Load Regulation speed: 30mA load variation Vin 3.3V Vout 1.4V
Fig. 11. Micro-photograph of the chip
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