Rajendra Prasad et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No.

1, 144 - 149

Low Power ASIC Design For Automation In Various Industrial Applications

Rajendra Prasad SENSE VIT University Vellore, India Rajen.rajan@gmail.com

Dhanabal R. SENSE VIT University Vellore, India Rdhanabal@Vit.ac.in

Abstract Automations in industries are needed to cut down

I.

INTRODUCTION

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the manual efforts. industrial applications like oil spillage or chemical spillage detection, machine overheating detection, speed control, drilling and automatic job feeding are done manually. Farming is also a process involves various steps. These steps are done manually by the farmers [1]. The need for a controller that can serve many purposes across all the industries arises. Speed and area optimizations are the major areas of concern while designing a system and Low power consumption (power efficient ICs) is strongly recommended considering the remote usability of the controller. Designing a configurable controller to include more functions increases the complexity in handling large number of signals and since the signals from the sensors are analog in nature avoiding metastability problem is extremely vital for the proper functioning of the device. Initially a controller for automating farming process has been designed. A verilogHDL code was generated Through the FSM design using HDL-Designer. Then after functionally verifying the code with modelsim, synthesis and post-synthesis simulation has been done for the RTL generated using Mentor Graphics IC-Station for the technology 250nm. With that total power and delay was also calculated for the design. An half swing clock driver [2] with clocked C2MOS latches [3] has been introduced into the design which gave 13% PDP improvement to the design. A proposed 8-bit GPIO core with 8-bit wishbone bus slave interface architecture designed to avoid metastability and to add configurability to the controller design.

Keywords- ASIC, GPIO, Metastability, Verilog HDL, FSM, Clocked CMOS, PDP, Wishbone bus slave interface Architecture.

Rajendra Prasad is with the Vellore Institute of Technology, Vellore, 632014 Tamilnadu, INDIA ( e-mail:rajen.rajan@gmail.com). R. Dhanabal is with the Dept. of VLSI, Vellore Institute of Technology, Vellore, 632014, Tamilnadu, INDIA (e-mail: rdhanabal@vit.ac.in).

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II.

In this project the main objective is the low power ASIC design of a sowing equipment control system to manage different processes of farming and maximum utilization of the available resources. Different processes include weed sensing, drilling, seed feeding, fertilizer feeding and leveling. Our control system is a multi-control system. Our system learns weed detection, drilling for seeds and fertilizer through the use of sensors. Our design contains a new clocking scheme in which all the clock signal swings are reduced to half of the supply voltage. This technology allows us to reduce power consumption of clocking circuitry by as much as 45%. The speed degradation caused by the proposed clocking scheme is quite small because the random logic circuits in the critical path are still supplied by the full supply voltage. The key to the proposed clocking scheme is the concept that the voltage swing is reduced only for clocking circuitry, but is retained for all other circuits in the chip. This results in significant power reduction in the clocking circuitry. A clock driver which generates 4-phase complementary half swing clock voltages has been used into the design. All the flip-flops were interchanged with C2MOS latches to incur minimum delay in the path with half swing clock voltages. Resizing of the latches is done to get optimum timing and lesser power dissipation. The 8-bit GPIO core with 8-bit wishbone bus slave interface architecture has a double latch-up property to make sure that the correct signal should be latched during flickering signal voltages. CONTROLLER DESIGN

A. FSM Design Of Controller ASIC Design of sowing equipment controller starts with the FSM design for generating verilogHDL code of the controller. This whole process has been done on HDLDesigner tool from Mentor Graphics.

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Fer_feed is the output for fertilizer feeding stage.

Fig. 1: Block Diagram Signals used in the above diagram have been taken according to the steps which are followed in the sowing process. During the FSM design special care is taken towards the ease of use for the user. The user can directly access the desired steps by using signals like direct_ferdrill. Clock 1 is a system clock Clock 2 is connected to seed feeding timer Clock 4 is connected to leveling timer.

Clock 3 is connected to fertilizer feeding timer Direct_ferdrill corresponds to input D2. Direct_ferfeed corresponds to input D3. Direct_level corresponds to input D4.

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Direct_seedfeed corresponds to input D1. fertilizer. Fer_drill_sensor is used to sense depth for drilling of Lev_sensor is used to sense the leveling of soil. Reset1 is the system reset Removal_start is used to sense the weeds, and initiation of removal of weeds. Seed_drill_sensor is used to sense the depth for drilling of seeds. Dislay,display2 ,display3 are the seven segment display for seed feed timer, fertilizer feed timer and level timer respectively Fer_drill is the output for the fertilizer drilling stage. Fig. 2: FSM Diagram
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Rajendra Prasad et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 6, Issue No. 1, 144 - 149

Level_soil is the output for leveling phase of the sowing process. On_indiactor is the output as soon as the machine gets started. Remover is the output for weed removal phase, once weed detector sensor signal goes high. Seed_drill is the output for seed drilling phase of the sowing process. Seed_feed is the output for seed feeding phase. Once the FSM design completes, tool generates Verilog HDL code for the design after checking the design for errors and violations. B. Simulation And Synthesis The generated code is then functionally tested for its application through functional simulation, which was done with the use of Modelsim simulator in this design. After cleaning the errors from the code the functionality tested with the test-bench code written to cover all the inputs and expected outputs of the design.

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Fig. 3: Simulation Results of controller design
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Synthesis of this Verilog code has been done with the use of Mentor Graphics Leonardo Spectrum synthesis tool and was optimized for area timing and power. Timing report shows a positive slack of 4ns which insures there are no timing violations in the design. An RTL netlist was generated by the tool which will be used further into the design. The generated RTL Schematic is shown in Fig. 4.

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III. A.

Fig. 4: RTL Schematic of controller

Half swing clock driver design A half swing clock driver generates complementary 4phase clock signal to drive latches. This scheme can help us to reduce power consumption in the clocking circuitry to as much as 35% with incurring a nominal delay, since the random logic in the critical path is still supplied by full voltage. To further reduce delay, C2MOS latches are used. Power dissipation in clocking circuitries are governed by the equation (1) given as Pclk =Cclk . Vdd2. fclk (1) When we reduce the clock swing to half of the supply voltage we get equation (1) as Pclk =1/4Cclk . Vdd2. fclk (2) This shows the power consumption has been reduced to quarter of the total power. While designing the clock driver transistor sizing plays an important role. Capacitors C1 and C2 are external capacitances and are used to improve the driving capability of the driver. Driver is fed with two input full swing clocks complementary to each other. Two outputs produced by the driver are separately used one for switching PMOS transistors another for NMOS transistors. Width of the transistors and size of the capacitors has to be adjusted so that equal charge transfers from one capacitor to another. Technology used in it is 250nm and simulated with TSMC library files in Mentor

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HALF SWING CLOCKING SCHEME
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Graphics IC station tool. Simulation results are shown in fig. 6 and fig. 5 shows clock driver design.

produces a kink at the output edge hence not suitable for half swing clock.

Fig. 5: Clock driver with C2MOS Latch.

Fig. 7: Clock to output delay Tphl=7.6ps

B. Behaviour of C2MOS Latches with half swing clock

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Fig. 6: Simulation Results of clock driver

Reduced clock voltage swing leads to reduced drain current causes longer latch delay. Resizing (increasing) channel width of latch transistors is necessary. The resizingfactor (RF) of the transistors is determined by the timing of the logic path following the latch. The output edge has to be restored only if there is long path with critical timing. With only shorter paths at the latch output, a longer latch delay may be permitted and RF can be smaller with two consecutive latches, resizing of the first is not necessary. Depending on the timing when a transition occurs at a latch input, the clock-tooutput delay or the input-to-output delay has to be considered. Simulation with realistic signal and clock slopes show that a resizing factor of 2 or 3 is sufficient to restore the output edge in most of the cases. In order to avoid RF becoming too large, a 0.1ns latch delay is tolerated at half swing clock. The use transmission gate

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IV.

Methodology followed in the design uses two 8-bit registers one is control register and another is line register. Use a pin as an input and Program the corresponding bit in the control register to 'input mode' ('0').The pin's state (input level) can be checked by reading the Line Register. Writing to the GPIO pin's Line Register bit while in input mode has no effect. Use a pin as an output and Program the corresponding bit in the control register to 'output mode' ('1'). Program the GPIO pin's output level by writing to the corresponding bit in the Line Register. Reading the GPIO pin's Line Register bit while in output mode returns the current output level. Adapt the core for fewer GPIOs, if less than 8 GPIOs are required, than the 'IO' parameter can be set to the amount of required interrupts. GPIOs are mapped starting at the LSBs. So only the 'IO' LSBs per register are valid. All other bits (i.e. the 8-'IO' MSBs) are set to zero '0'. Code size is approximately linear to the amount of interrupts. I.e. using 4 instead of 8 GPIO sources reduces the size by approximately half. Double latch-

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Fig. 8: Data to output delay Tplh =0.84ns 8-BIT GPIO CORE DESIGN
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GPIO MODULE

Fig. 9: Block Diagram of 8-bit GPIO Core

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Fig. 10: Functional Simulation of 8-bit GPIO Core
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ACK_o V. VI.

CLK_i RST_i CYC_i STB_i ADR_i WE_i DATA_i[7:0]

DAT_o[7:0]

INTRODUCING HALF SWING AND GPIO CORE INTO CONTROLLER DESIGN

The synthesized netlist of the controller design is imported in Mentor Graphics IC-station for post synthesis simulation. The design is then simulated with TSMC025.mod library files. Total power dissipation was calculated as 1.8845mW and an average delay of 1.214 S. Then the symbols had been generated for the clock driver and GPIO. These symbols brought into the controller design and all the latches were replaced with the C2MOS latches. All the connections updated with the new ones. The updated design had been simulated again and the total power dissipation calculated as 1.3757mW, which can be intuited as power dissipation in the circuit dropped down 27% of its original value. But the average delay increased to1.44682. CONCLUSION

This paper introduces a complementary 4-phase half swing clocking scheme along with C2MOS latches into the design to improve the PDP of the design up to 13%. It also introduces an 8-bit wishbone bus slave interface architecture based GPIO core to give leverage to its configurability for various other industrial applications. The future work can be extended to use the same controller design for automation in different industrial and automotive applications, which can be done by using different sensors and signals into the design.

up at the input of the GPIO pins ensures reduced metastabillity risks. It has the following advantages over conventional IOs: This 8-bit GPIO core is used to avoid METASTABILITY problem in latching the input or output especially when the signal is analog in nature. It has 8-bit wishbone bus slave interface. Separate control and line registers for wishbone access,Double latch up to reduce metastability risk. Acknowledgement signal to ensure that correct data has been latched. Configurable up to 32 ports, each port can be input, output or bypass. Data set or bitwise set and clear control, input data synchronization. Flexible interrupt generation for each GPIO pin. Synchronous bus interface- zero wait states, supports system bus such as AMBA APB version 2.0. Full synchronous design, technology independent. Adds configurability into design.

Fig. 11: RTL-Schematic of 8-bit GPIO Core

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REFERENCES [1] Jayendra kumar and pritesh FP A based advanced G sowing and planting equipment controller design 2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009). [2] Hirotsugu Kojima,Satoshi Tanaka, and Katsuro Sasaki Half-swing clocking scheme for 75% power reduction in clocking circuitry, IEEE. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL. 30, NO. 4, APRIL 1995. [3] Dr.-Ing. Manuel Lw (Infineon),Dipl.-Ing. Nikolaus Brls (Infineon),Prof. Dr.-Ing. Hans-Jrg Pfleiderer (University of Ulm) Power saving in cmos using half-swing clocking scheme ESSIRC 2001, 18-20 sept. Villach,Austria. [4] Wayne Wolf, FPGA-Based System Design, Prentice Hall, 2005. [5] Jan M. Rabaey, Digital Integrated Circuits, A Design Perspective, Second Ed., Prentice Hall, 2003. [6] FSM-based Digital Design using Verilog H DL Peter Minns and Ian Elliott,2008 John Wiley & Sons, Ltd. ISBN: 978-0-470-06070-4.

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