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Offset and CMRR : Random and systematic

Willy Sansen
KULeuven, ESAT-MICAS Leuven, Belgium
willy.sansen@esat.kuleuven.be
Willy Sansen
10-05

151

Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bipolar transistors

Ref: Pelgrom, JSSC Oct.1989, 1433-1439 Croon, JSSC Aug.02, 1056-1064 Croon, Springer, 2005
Willy Sansen
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152

Definition of offset
+ vOUT 0 + vOUT = 0

vOS

Offset voltage vos

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10-05

153

Gain error with offset


RF = 100 k RS = 1 k vOS = 4 mV + vOUT = - 596 mV - Offset free

vIN = 10 mV

The gain is 59 instead of 100 !


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154

Yield of n-bit flash-ADC with offset

Ref: Pelgrom, IEDM 1998, pp.789.


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155

Random offset : mismatches


N VT IDS = K W (VGS - VT)2 L AVT WL
4

VT =

VT

VT

AVT ~ tox NB AVT 5 mVm for 0.25 m nMOST


+50 % for pMOST
Willy Sansen
10-05

Ref: Keyes, JSSC Aug. 1975, 245-247 Shyu, JSSC Dec 1984, 948-955 Lakshmikumar, JSSC Dec 1986, 1057-1066 Pelgrom, JSSC Oct.1989, 1433-1439 Croon, JSSC Aug. 2002, 1056-1064

156

Threshold voltage sigma VT


mV

VT

VT =

AVT WL

(VT) 2 mV W/L = 60/0.7 m in 0.7 m CMOS

1/

WL

1/m
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10-05

Threshold voltage mismatch AVT


4

mVm 40 20 10 5 2.5 1.2

AVT ~ tox NB

1 mVm /nm tox

1.25 0.06

2.5

10

20 1.2

40

nm tox

0.13 0.18 0.25 0.35 0.5 0.7

2.4 m L
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158

Random offset : mismatches


K K = AK WL AK 0.0056 m +50 % for pMOST

W/L W/L

= AWL

1 W2

1 L2

AWL 0.02 m +50 % for pMOST

A WL

A 0.016 m -25 % for pMOST Negligible if B = S


Ref.: Pelgrom : JSSC Oct.1989, pp.1430-1440
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159

Mismatch coefficients for nMOST


Techno L (m) tox (nm) AVT AWL (mV m) (% m) 2.5 50 30 2.5 0.3 0.3 1.2 25 21 1.8 0.3 0.7 15 13 2.5 0.4 0.2 0.5 11 7.1 1.3 0.2 0.2 0.35 8 6 2 0.25 6 0 1.8

SVT (mV/mm) SWL (%/mm)

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10-05

1510

Random offset in differential pair


RL vo1 RL+RL vo2 IB vod = RL 2 vos = vod gmRL RL IB RL 2gm RL VGS - VT RL 2

- +
vod

vos IB

vos =

vos =

Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994


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1511

Random offset in differential pair


RL vo1 RL+RL vo2 VGS - VT 2 K K +

- +
vod

vOS = VT + RL RL +

( )

K W/L VT

W/L W/L

vos IB

small VGS - VT
Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994
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1512

Random offset in current mirror


Iout iout
M1 M2

iin

Iout

VT (VGS - VT )/2

K K

W/L W/L

K W/L VT large VGS - VT


Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994
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1513

More offset in current mirror

iin iout1
2

iin iout1
2

M1

M2

M3

M1

M2

M3

RS K W/L VT RS

K W/L VT

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10-05

1514

Mismatch in drain current


IDS = IDS IDS
2

2 =

(VGS - VT - VT

)2 2 VGS - VT

K W = n L

IDS IDS

) = (
2

) + (VT )
2

4 (VGS - VT )2 1 (nkT/q )2 in wi

gm IDS

)2

in general
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10-05

1515

Mismatch in drain current for wi and si

IDS IDS

) = (
2

) + (VT )
2

4 (VGS - VT in si )2

or

1 (nkT/q )2 in wi

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10-05

1516

Random CMRR in differential pair -1


RL vo1 vinc RL+RL vo2 K W/L VT vod = Add vid + Adc vic voc = Acd vid + Acc vic vod Add = = gm RL vid v = 0 ic vod Adc = 0 vic v = 0
id

- +
vod

RB

IB CMRR =

Add Adc

10-05

Willy Sansen

1517

Random CMRR in differential pair -2


RL vo1 vinc ic/2 RL+RL vo2 ic/2 vod Adc = 0 vic v = 0 id vic = vinc vod = RL ic/2 ic RB IB RL Adc = 2 RB 2 gm RB RL/RL ic = vinc RB

- +
vod

CMRR =

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10-05

1518

Random CMRR in differential pair -3


RL vo1 vinc RL+RL vo2 K W/L VT CMRR = 2 gm RB RB IB 2 VT VGS - VT + RL RL + K K + W/L W/L
10-05

- +
vod

Willy Sansen

1519

Relation random offset and CMRR


vOSr = VT + VGS - VT 2 ( RL RL + K K + W/L W/L )

CMRRr =

2 gm RB 2 VT VGS - VT + RL RL + K K + W/L W/L

vOSr CMRRr = vOSr CMRRr =

VGS - VT 2

2 gm RB = IB RB = VELB = 5 15 V 10 V
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1520

Relation random offset and CMRR

vOSr CMRRr VELB 10 V 10 mV 60 dB 10 V 1 mV 80 dB 10 V

( ~ LB)

as for MOSTs as for Bipolar transistors with trimming : with laser with Zener zap with fusible links

10 V 120 dB 10 V

Low offset = High CMRR


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1521

Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bip.transistors

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10-05

1522

Systematic offset in current mirror


iDS iout
M1 M2

iin

iout vGS

vDS1 K W/L VT iout iout =

vDS2

vDS

vDS2 - vDS1 VEL2


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1523

Systematic CMRR in differential Pair - 1


RB ic vosc +vinc
M3 M1 M2

IB K W/L VT

ic =

vinc RB

iout ic ro1

2 gm3ro1

ic/2

ic/2 1/gm3

ic/2
M4

vOUT
CL

iOUT i

iOUT

K W/L VT
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1524

Systematic CMRR in differential Pair - 2


RB ic vosc +vinc
M3 M1 M2

IB

iout vinc iout vosc

1 2 = RB gm3ro1 = gm1 vind = Adc Add = 1 CMRRs

ic/2
M4

vOUT
CL

iout vinc iout vosc

iOUT

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10-05

1525

Systematic CMRR in differential Pair - 3


iout vinc iout vosc vOUT = 0 vOUT = 0 = vosc vinc = Adc Add = 1 CMRRs 1 CMRRs = gm1RB gm3ro1 2 CMRRs vosc = vinc

vosc

vinc

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10-05

1526

Total CMRR
1 CMRR 1 CMRRr 1 CMRRs

vOUT = 0

vOUT = 0

vosc

vinc

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10-05

1527

Offset Miller CMOS OTA


M7 1 : B M5

Av1= gm1 r02//r04 vOS = VDS1 Av1 gm3 gm1 +

M1

3 M2

Cc

vOUT
CL

VT1 +

VT3* +

+ VDS1 2
M3

1
M4

M6

+ S=
Kn Kn

VGS1 - VT 2

Kp W/L1 W/L3 + + + Kp W/L1 W/L3


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1528

Offset Folded cascode CMOS OTA


M9 M1 M2 3 M5 M7 M6

vOS = gm6

VDS3 Av

+ VT1 +

+
5 M3

M8 4

vOUT

gm11 + VT5 + VT11* gm1 gm1

+ VDS3 -

M4

CL Kn Kn

VGS1 - VT 2

S=
M11 M10

Kp W/L1,6,11 + + Kp W/L1,6,11

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Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bip.transistors

Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994


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1530

CMRR vs frequency
- +
vinc vod A Add CMRR fB = 1 2RBCB

fB IB Adc RB CB

CB CGS RB 100/gm >> fB fT/100 BUT CB includes Cwell, bulk !!!


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1531

Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bipolar transistors

Willy Sansen

10-05

1532

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Hastings, The Art of Analog Layout Prentice Hall 2001 R. Soin, ..A-D Asics, .. Peregrinus, 1991
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1533

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

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1534

On same isotherm

Solomon, JSSC Dec 74, 314-332


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1535

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

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1536

Layout resistor
B R1 R2

p+

n+

Source/drain diffusion resistor in CMOS

Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994 Table 2-6


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1537

Table resistors

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1538

Mismatch vs size for resistors


(R2/R1) R2/R1
% 10 3

Local errors : jagged edges, .. Error ~ 1/size

Diffused
1 0.3

Ion-implanted
0.1 1 3 10 30 100 m W
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10-05

1539

Layout capacitors
B C1 C2

Poly to S/D capacitor


p+ p n+

n+ poly
B C1 C2

Poly to poly capacitor Cpar 1 Cpp 6 15


10-05

p+

n+

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1540

Table capacitors

Ref.: Laker, Sansen : Design of analog , MacGrawHill 1994 Table 2-7


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1541

Mismatch vs size for capacitors


(C2/C1) C2/C1
% 1 0.3 0.1 0.03 0.01 1 3 10 30 100 m S
Willy Sansen
10-05

Wet etched

Local errors : jagged edges, .. Error ~ 1/size Global errors : oxide thickness, bulk doping, ..

Dry etched

1542

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

10-05

1543

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

10-05

1544

Matching of transistor pairs

Bad

Better

Better

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10-05

1545

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

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10-05

1546

Matching of current mirrors

1 : 4

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1547

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

10-05

1548

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

10-05

1549

Cross-coupled differential pair

Oxide thickness

Less sensitive to global variations : Oxide thickness Substrate doping level ..


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10-05

1550

Centroide layout of capacitors

Ratio: 1 2 4 8 16

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10-05

1551

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

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10-05

1552

Matching of current mirrors

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1553

Layout capacitance ratio

Ratio 7/2 = 3.5


Courtesy Vittoz
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1554

Layout rules for low offset


1. Equal nature 2. Same temperature 3. Increase size 4. Minimum distance 5. Same orientation 6. Same area/perimeter ratio 7. Round shape 8. Centroide layout 9. End dummies 10. Bipolar always better !

Willy Sansen

10-05

1555

Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bipolar transistors

Willy Sansen

10-05

1556

Offset of MOST and bipolar transistors


vOS = VT + kT q VGS - VT 2 RL RL + IS IS RL RL K K W/L W/L

MOST :

Bipolar :

vOS =

) is much smaller !!

1) no VT 2) kT/q << (VGS-VT)/2 3) Drift decreases with vOS : Bipolar : Base current ! vOS T
Willy Sansen

vOS T
1557

10-05

Bias or base currents


Ibias
pA 1000 100 10 1 0.1 5 25 45 65 85 105
oC

Bipolar

JFET or MOST with protection diode : X 2 every 8 oC

Super Bipolar MOST

T
10-05

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1558

Base current compensation


OP07

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1559

Common-mode base current compensation


OP27

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1560

Tracking base current compensation

Q29 & Q30 provide a voltage clamp to track the input bias currents for changes in CM input voltage.

Ref. Gross, JSSC, Feb. 2004, 404.


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1561

OP-97 : input current compensation


Low input currents because super- transistors at the input !
I2

Q3 Q1 Q2

I1 I1 + I2

Q4 Q5

Require low VCE !


VCE1,2 = VBEon 0.7 V

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10-05

1562

OP-97 : input current compensation


2IB
Q3 Q1

IB

Q2

IB IB /

IB / 0 3IB
Q4 Q5

IB / IB

Same and VCE as input transistors

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10-05

1563

Limits because of device mismatch


1 (Accuracy)2 (
2

IDS IDS

4 AVT 2 WL (VGS - VT )2 VDD 2

Speed fT =

2 IDS 2 WL 2/3 Cox (VGS - VT ) = 1 Cox AVT2 ~ 1 tox


Willy Sansen

Speed x (Accuracy)2 Power

= Technological constant
10-05

1564

Limits because of device noise


S/N = Vpp2/ 2 4kT R BW Vpp2 R S/N = Vpp2/ 8 kT / C

Pmin =

Pmin = VDD BW Vpp C

Pmin 8kT BW S/N

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10-05

1565

Noise versus mismatch for high DR


Mismatch Noise

Ref. P.Kinget, ... Analog VLSI .. page 67, Kluwer 1997.


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1566

Reduced DR in deep submicron CMOS

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1567

Table of contents
Random offset and CMRRr Systematic offset and CMRRs CMRR versus frequency Design rules Comparison MOST and bipolar transistors

Ref: Pelgrom, JSSC Oct.1989, 1433-1439 Croon, JSSC Aug.02, 1056-1064 Croon, Springer, 2005
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10-05

1568