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Printed Circuit Board Basics

Ing. Fernando Hernndez, MBA

V 1.3 - 20010

Designing a PCB

How many routing layers and power planes are required for functionality within the context of acceptable costs ? # layers:
Functional specification Noise immunity Signal category separations, Number of nets (traces) Impedance control Component density of VLSI circuits Routing of buses

Proper use of stripline and microstrip topology are required for RF suppression in the PCB The use of planes (voltage & ground) embedded in the PCB is one of the most important methods of suppressing common-mode RF internal to the board => intrinsically contribute to reducing HF power distribution impedance Minimizing lead inductance from components on the outer layers of the PCB will reduce radiated emission effects.

Microstrip and stripline


Microstrip
Refers to outer trace(s) on a PCB, which are separated by a dielectric material and then a solid plane. Although microestrip techniques provide suppression of RF energy on the board, faster clock and logic signals are possible than with stripline With lower capacitive coupling between two solid planes, faster signal propagation can be implemented. The drawback of microstrip is that the outer layers of the PCB can radiate RF energy into the environment unless one adds the protection of a plane on both sides of this outer circuit plane.

Microstrip and stripline


Stripline
Refers to placement of a circuit plane between two solid planes either voltage or ground. Provides better noise immunity for RF emissions, but it comes at the expense of slower propagation speeds Capacitive coupling effects on stripline topology are generally observed on signals with edges faster than 1 ns. Main benefit: the complete shielding of RF energy generated from internal traces and the consequent supression of RF radiation.

Microstrip and stripline topologies

Layer stackup assignment


Each and every routing layer must be adjacent to a solid plane (power or ground).

Two-layer boards
Two layout methodologies: First Older technologies low speed components: DIL in straight row or matrix configuration. Few use this tech today!

Two-layer boards Configuration 1


Layer the power and ground in a grid style with the total loop area (each grid) 1,5 square inches Run power and circuit traces at a 90, with power on one layer, ground on the other layer Place ground traces on the top layer, vertical polarization. Place power traces on the bottom layer, horizontal polarization Locate decoupling capacitors between the power and ground traces at all connectors and at each IC.

Two-layer boards Configuration 2


Commonly used in lowfreq analog designs running at less than 10 KHz. Single-point grounding is recommended

High freq performance in layout for low-freq applications: For Hi freq: Control the surface impedance of all signal traces and their return current paths For Low-freq: control topology layout rather than impedance

Radial migration(1)
Signal propagation delay: Devices have internal capacitance and propagation delay

As circuits progress from high-bandwidth to lowbandwidth areas, a slowing down of the signal propagation delay of the traces occurs, with enhanced EMI performance at the I/O connector

(1) Technique developed by W. Michael King

Four-layer boards
There is only one way to perform a fourlayer stackup Use of power and ground planes enhances EMI suppresion in comparison to that of two layers boards However: four-layer boards are not optimal for flux cancellation of RF currents created by circuits and traces.

Four-layer board stackup


First layer (component side) Signals and clocks

Second layer
Third layer

Ground plane
Power plane

Fourth layer (solder side)

Signals and clocks

Basic fundamental concepts of EMI suppression in a PCB.


Optimal performance of extra-high-speed clock traces are achieved when they are routed adjacent to a ground plane and not adjacent to the power plane.
Use of the power plane as flux cancellation control may not present an optimum condition, resulting in signal flux phase shift, greater inductance, poor impedance control, and noise instability. Use of the ground plane for optimal signal reference is thus preferred.

PCB flux cancellation


Multilayer boards provide superior signal quality EMC performance: Impedance control through stripline or microstriplines is observed flux cancellation that minimizes (control) inductance in any transmission line. The distribution impedance of the power and ground planes must be dramatically reduced These planes contain RF spectral current surges caused by logic crossover, momentary shorts, and capacitive loading on signals with wide buses Various logic devices may be quite asymmetrical in their pull-up/-down current ratios: flux cancellation is enhanced between the signal and the ground planes rather than the power planes.

PCB flux cancellation


The fundamental concept of board-level suppression lies in flux cancellation between RF currents that exist within the board traces, components, and circuits, in relation to a plane. Power planes, due to this flux phase shift, do not perform as well for flux cancellation as do ground planes. As a result, optimal performance is achieve when traces are routed adjacent to ground planes rather than adjacent to power planes, as evidenced by the pull up/down ratios that are indicative of flux-phase preference.

Six-layer board stackup


Three common configurations are used for six-layerPCBs

Six-layer board Configuration I


This is commonly used with clock signal or high-frequency components
First layer (component side) Second layer Third layer Fourth layer Fifth layer Sixth layer (solder side) Microstrip signal routing layer Ground plane Stripline routing layer Stripline routing layer Power plane Microstrip signal routing layer

Six-layer board Configuration II


This arrangement offers improved performance due to increased planar decoupling between voltage and ground four routing layers.
First layer (component side)
Second layer Third layer Fourth layer Fifth layer Sixth layer (solder side)

Microstrip signal routing layer


Embedded microstrip routing layer Ground plane Power plane Embedded microstrip routing layer Microstrip signal routing layer

Six-layer board Configuration III


This offers the best performance with increased flux cancellation for all routing layers and lower power plane impedance- three routing layers
First layer (component side) Second layer
Third layer

Microstrip signal routing layer Ground plane


Stripline routing plane, followe by fill material

Fourth layer
Fifth layer Sixth layer (solder side)

Power plane
Ground plane Microstrip signal routing layer

Eight-layer board stackup


Two types of assignments generally are employed:
First: provides minimal EMI flux cancellation. Second: provides maximum cancellation due to use of additional solid planes and tigher flux cancellation for RF currents

Whether to use? Depends on the number of nets to be routed, component density (pin count), size of bus structures, analog and digital circuitry and available real estate.

Eight-layer board Configuration I


This is not an optimal stack-up scheme due to poor flux cancellation on signal planes and poor power impedance. It employs six routing layers and two planes.
First layer (component side)
Second layer

Microstrip routing signal layer


Embedded microstrip routing signal layer

Third layer
Fourth layer Fifth layer Sixth layer Seventh layer Eighth layer (solder side)

Ground plane
Stripline routing signal layer Stripline routing signal layer Power plane Embedded microstrip routing signal layer Microstrip routing signal layer

Eight-layer board Configuration II


This is a preferred stack-up scheme due to tight flux cancellation of RF currents. It uses four routing layers and four planes.
First layer (component side)
Second layer

Microstrip signal routing layer


Ground plane

Third layer
Fourth layer Fifth layer Sixth layer

Stripline signal routing layer


Ground plane Power plane Stripline signal routing layer

Seventh layer
Eighth layer (solder side)

Ground plane
Microstrip signal routing layer

Ten-layer board stackup


Six routing layers are used, with four planes
First layer (component side) Second layer Third layer Fourth layer Fifth layer Sixth layer Microstrip signal routing layer Ground plane Stripline signal routing layer Stripline signal routing layer Ground plane Power plane

Seventh layer
Eighth layer Ninth layer Tenth layer (solder side)

Stripline signal routing layer


Stripline signal routing layer Ground plane Microstrip signal routing layer

20-H Rule (defined by W. Michael King)


RF currents exist on the edges of power planes due to magnetic flux linkage. This interplane coupling is called fringing and it is generally observed only on very high-speed PCBs. When using high-speed logic and clocks, power planes can couple RF currents to each other and thus radiate RF energy into free space.

To minimize this coupling effect, all power votage planes must be physically smaller than the closest ground plane per the 20-H roule.

20-H Rule
Use of the 20-H Rule increases the intrinsic self-resonant frequency of the PCB

Implementing the 20-H rule