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EMI/EMC Engineering Tips

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Tips for Electronic Printed Circuit Board Design

Introduction

This information is presented as guidelines to the preliminary design and development stages of electronic circuits for the purpose of preventing potential electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems. The tips are representative of good printed circuit board (PCB) design practices and are recommended as a checklist for evaluating and selecting EMI/EMC software modeling tools. The EMI

simulation of circuit boards requires the evaluation of many details such as clock frequencies, switching rates, rise/fall times, signal harmonics, data transfer rates, impedances, trace loading and consideration of the types and values of the various circuit components. The physical layout of the PC board and its associated metallic components are important considerations. Special attention should be given to the placement and characteristics of signal source components, vias, traces, pads, board stack-up, shielded enclosures, connectors and cables. For example, as signal frequencies and clock/switching rates increase, PC board trace characteristics can become

similar to those of transmission lines and radiators.

component can become an efficient antenna at a length as small as one twentieth of a wavelength.

A PC board trace or

EMI/EMC problems may be approached at the component, PC board or enclosure levels. However, it is much more efficient to deal with these problems as close to the source or susceptible victim as possible. Therefore, it is important to consider these tips as guidelines for PCB design and layout so that problems may be identified and prevented prior to actual fabrication of the equipment.

General

(1) EMI controls should be applied at the circuit and box levels prior to addressing EMI at the interconnected and system levels.

(2) Digital circuits are more likely to be the source of emissions due to the handling of periodic waveforms and the fast clock/switching rates. Analog circuits are more likely to be the susceptible victims due to higher gain functions.

(3) The source or susceptible victim of most EMI problems is typically an electronic component. Although active components are usually the sources

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of EMI, passive components often contribute to it, depending on the signal

frequencies and component's characteristics.

become predominantly capacitive due to the high frequency parasitic coupling between windings. A capacitor can develop parasitic series inductance due to its internal inductance and external lead inductance at high fundamental and harmonic frequencies.

For example, an inductor can

(4) EMI problems involving an active component can be the result of the

device's output transferring the emissions or its input providing the path for

susceptibility.

become a direct radiator or receptor of EMI. Also, the component’s power and ground connections can provide paths for both emissions and susceptibility.

However, at high frequencies the active component may

(5) Although common mode currents are usually small compared to differential mode currents, they can be the main cause of radiated emissions.

(6) Emissions and susceptibility that are typical in single layer, free wired (using power and ground traces instead of planes) PC Board design, can be greatly improved by using multi-layer PC boards with power planes. High capacitance between a forward signal and its return path (ground plane) provides containment of the electric field. Low inductance of the paths provides for magnetic flux cancellation. Although not always realistic in a PCB stack-up design, a trace should be spaced one dielectric layer away from its associated return path and the voltage and ground planes should be as closely spaced as possible.

(7) PCB stack-up design is important in containing the electromagnetic fields, while providing for additional bypassing and decoupling of the power bus and minimizing bus voltage transients. Some of the benefits of multi-layer PC board design with power planes are:

a.

The power planes, if properly designed, will provide an image plane effect. Since the return currents in the power planes are equal and opposite polarity to the associated signal currents, their electromagnetic fields will tend to cancel. Power planes can also reduce the loop areas of signal and power traces, resulting in a decrease of EMI emissions and susceptibility.

b.

A ground plane can lower the overall ground impedance, thus reducing high frequency ground bounce. Also, the impedance between the ground and voltage planes is lowered at the high frequencies and this reduces power bus ringing.

(8) Clocked IC’s with rapid output transitions can be very demanding on voltage and current distribution components such as the power supply,

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power bus, and power planes. The inductance of the power bus can prevent the rapid energy transfer needed to meet the quick output transitions and fast rise times. This can be improved with the placement of decoupling capacitors at the IC’s power pins. The capacitors must be properly selected

in their frequency response to deliver the energy needed at the IC’s output frequency spectrum. However, as the number of decoupling paths increase, so do the number of voltage drops across them and this can result in power

bus transients along with the associated common mode emissions.

problem can be minimized with proper power plane design in the area of the IC’s. The power plane acts as an effective high frequency capacitor, and consequently, as an additional energy source needed for cleaner IC outputs.

This

PCB Layout

(1) Use multi-layer PC boards rather than single-layer boards whenever possible.

(2) If a single layer board must be used, a ground plane should be utilized to help reduce radiation.

(3) Top and bottom ground planes can help reduce radiation from multi-layer boards by at least 10 dB.

(4) Segmented PC board ground planes are useful for reducing cable radiation due to common mode currents.

(5) Power and return planes should be located on opposite sides of a multi-layer PCB. Effective power planes are low in inductance. Therefore, any transients that may develop on the power planes will be at lower levels, resulting in lower common mode EMI.

(6) Connection of the power planes to high frequency IC power pins should be as close to the IC pins as possible. Faster rise times may require connections directly to the pads of the IC power pins.

(7) Analog and digital circuits are susceptible to interaction when located in close proximity to each other. These should be located on different layers of the PC board whenever possible. If the circuits must be located on the same layer, they should be separated into analog and digital areas with proper isolation layout.

(8) High frequency traces, such as those used for clock and oscillator circuits, should be contained by two ground planes. This provides for maximum isolation. The reactance of a trace or conductor can easily exceed its dc resistance as frequency increases. If this trace is run close to its ground plane, the inductance can be reduced by about one third.

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(9) Additional EMI preventive measures for clock/oscillator traces include the utilization of guard traces grounded to the ground plane at several locations. The shielding of clock and oscillator components with foil or small metallic enclosures may also be needed.

(10) Overall circuit cross-talk increases by a factor of two whenever the clock

rate is doubled.

the PC board trace height above the ground plane.

EMI radiation and cross-talk may be reduced by minimizing

(11) PC board edge radiation may be the result of traces being located too close to the board edge. This can be minimized by keeping traces at a distance of at least 3 times the board thickness away from the board edge.

(12) PC board trace stacking should be avoided if possible. Otherwise, it should be limited to one trace height in order to reduce radiation, cross-talk and impedance mismatches.

(13) Parallel traces are often susceptible to cross-talk. These should be separated by at least 2 trace widths for cross-talk reduction.

Decoupling, Bypassing and Filtering

(1) EMI filters can be used as a shunt element to divert electrical currents from a trace or conductor; as a series element to block a trace or conductor current; or they may be used as a combination of these functions. Selection of the filter elements should always be based on the desired frequency range and component characteristics. A low pass filter can be useful for reducing most high frequency EMI problems. It incorporates a capacitive shunt and series resistance or inductance. However, at frequency extremes, the capacitor can become inductive and the inductor can become capacitive

causing the filter to act more like a band-stop filter.

should be based on the overall impedance at the circuit’s point of application for proper match. A T-filter design is effective for most EMI applications and is ideal for analog and digital I/O ports.

The filter design type

(2) Capacitors may be used for signal filtering and power source decoupling within their high frequency performance characteristics. However, their internal and external inductance can limit performance at high frequencies. Ceramic capacitors are recommended for the high frequencies, particularly those in the GHz range. A capacitor providing a reactance of less than 1

Ohm at the frequency of concern should suffice.

lengths must be short at the high frequencies in order to prevent the addition of inductive reactance.

Capacitor lead and trace

(3) PC board bypass capacitors used at high frequencies (greater than 100 MHz) should utilize surface mount technology (SMT) with vias close enough to the mounting pad to minimize or eliminate the traces. The via holes

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should be large (greater than .035 inch in diameter) and the PC board

should be thin enough to bring power and ground planes near the body of

Proper design layout of the bypass

capacitors can greatly reduce the power and ground circuit noise by lowering the overall effective inductance of the capacitors.

the capacitor (less than .030 inch thick).

(4) Wire wound ferrite inductors may be used for EMI emissions and

immunity filtering at lower RF frequencies. These can supply from about 1

microhenry to 1 millihenry of inductance.

capacitor above their resonant frequency and are useless in the most common EMI frequency range of 50 MHz to 500 MHz. Ferrites and ferrite beads are recommended for higher frequency applications where they become lossy and act more like a resistor. Select a ferrite impedance of about 100 to 600 Ohms at the frequencies of concern.

However, they can become a

(5) Shielded I/O cable connectors equipped with bypass capacitors or filter pins should be used whenever possible.

(6) I/O filters should be inside of the I/O connector (as with filter pins) instead of on the PC board.

(7) I/O bypass capacitors should be mounted at the I/O connector instead of on the PC board.

(8) I/O ferrites should be mounted inside of the I/O connector instead of on the PC board.

(9) A snap-on ferrite bead at the I/O cable connector can provide 3 to 5 dB of common mode absorption.

(10) Multiple ferrites may be used to reduce radiation by up to 10 dB depending on their characteristics at the frequency of interest.

(11) Ferrite beads are available in high-Q resonant and low-Q non-resonant (absorptive) types. The low-Q beads are recommended for digital circuits and filtering applications.

(12) External cable or I/O connector filters can provide for a common mode rejection of greater than 10 dB.

Cables and Connectors

(1) Cables should be grouped according to their function such as power, analog, digital, and RF.

(2) Separate connector assemblies should be used for analog and digital signals.

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(3) Analog and digital connectors should be located as far apart as possible.

(4) Analog and digital signal pins should be separated by unused grounded pins when sharing the same I/O connector.

(5) Individual pins should be used inside the I/O connector for each signal return so that all return circuits remain separated.

(6) Connector crosstalk may be reduced by using separate power and ground pins for each signal and by reducing the circuit’s loading and current flow.

(7) Cable shields should be grounded to equipment housing at the I/O points.

(8) Shielded I/O cables are most effective if grounded at both ends.

(9) Cable common mode currents should be removed at the equipment’s metal housing prior to internal connections.

(10) Cables should be routed close to ground planes, shielded structures, and cable trays.

Grounding

(1) Use ground planes instead of vectorial traces.

(2) Ground traces should be as short and thick as possible.

(3) Decouple signal and RF circuit grounds.

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