Low-power design technique for ash A/D converters based on reduction of the number of comparators

Takahide Sato, Shigetaka Takagi and Nobuo Fujii

Graduate School of Science and Engineering, Tokyo Institute of Technology Tokyo, Japan Email: {takahide, takagi, fuj}@ec.ss.titech.ac.jp

Abstract This paper proposes a low-power, small chip area design technique for ash analog-to-digital converters (A/D converters). The proposed technique reduces power consumption of ash A/D converters by 50 % reduction of the number of comparators. Because output signals of ash A/D converters are thermometer code, only a few comparators whose reference voltages are around the input signal are signicant and the other comparators can be removed. A novel track and hold circuit (T/H circuit) which can exchange its two balanced output signals is introduced. Thanks to the T/H circuit, the required input range of the comparator is limited to half of that of conventional one. The proposed A/D converter using the proposed T/H circuit can realize the same accuracy with the conventional one. The proposed technique is applied to a 6-bit 528 Msamples/s A/D converter realization. Its power consumption is evaluated by HSPICE simulations. It is conrmed that the proposed technique can save 34 % of power consumption compared with conventional one.

Vmax Sw1 Vin C R R R R R + R R Vmin + Comparators R

+ + + + + (2N-1) to N digital N bits outputs encoder

T/H Circuit

I. I NTRODUCTION Very high speed analog to digital converters are expected to act an integral part of future wireless communication systems such as Ultra Wide Band (UWB) wireless systems and software defended radios. Flash A/D converters are the standard approach for realizing very high-speed converters, as seen in some recent publications [1] [5]. Moreover ash A/D converters have begun to attract great interests because ash A/D converters do not require operational ampliers and they have a potential for low-voltage operation [6]. Figure 1 shows a basic conguration of a ash A/D converter. A ash A/D converter usually consists of a track and hold circuit, a row of resistors, comparators and following digital circuits [7] [8]. T/H circuits are necessary to prevent an error caused by clock skew especially for high speed A/D converters [9] [10]. T/H circuits keep their output voltage while comparators decide their output voltage level. A row of resistors connected to Vmax and Vmin creates reference voltages where Vmax and Vmin are upper and lower limit of the input range of the A/D converter respectively. 2N 1 comparators are used in an N -bit ash converter and a sampled input signal is fed to 2N 1 comparators in parallel. The comparators compare the input signal and the reference voltages at the same time. They convert the input signal into
1-4244-0921-7/07 $25.00 2007 IEEE.
Fig. 1.

Basic conguration of a ash A/D converter (3 bits, single-end)

a thermometer code. A time required for the conversion is ideally only one clock cycle. The thermometer code is decoded into N -bit binary code easily by digital circuits. NAND gates are often inserted between comparators and a decoder for the error correction, however, they are omitted in Fig. 1. Flash A/D converters are very fast, however, they require a large number of comparators, which typically occupy a large chip area and consume a large power. Especially their power consumption becomes larger and lager as their clock frequency becomes higher. The total parasitic input capacitance of many comparators are also very large. The power consumption of output buffers of the T/H circuits followed by the comparators also becomes large to charge and discharge the large input capacitance of 2N 1 comparators quickly. Therefore, reduction of the power consumption of ash A/D converters becomes one of the most important issue for high speed analog to digital data conversion [11]. Reduction of the number of comparators is particularly effective for low-power operation. This paper proposes a low-power design technique for a ash

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TABLE I

Vmax Input range Vinp(i) V0

R ELATION BETWEEN INPUT SIGNALS AND POSITION OF REDUNDANT

Vinp (i) t1 (ii) Vinm t2 t

COMPARATORS

Vinp < V0 (Vinm > V0 ) Redundant comparators (Vinp ) Redundant comparators (Vinm ) Upper half Lower half

V0 < Vinp (V0 > Vinm ) Lower half Upper half

Vmin
Fig. 2. Input balanced signals of A/D converters

A/D converter by reducing the number of comparators. II. C ONCEPT OF THE PROPOSED LOW- POWER TECHNIQUE Using balanced signals is one of the most effective approach to suppress a common mode noise in analog circuits. Therefore this paper deal with balanced input signals as input signals of A/D converters, however, single-ended comparators shown in Fig. 1 are used for discussion in this section for simplicity. A couple of Fig. 1 can realize a pseudo differential comparator. A differential comparator is introduced in section III. Figure 2 shows an example of balanced input signals for an A/D converter where a solid line and a dashed line indicate two balanced signals, Vinp and Vinm , respectively. It is assumed that their common mode voltage is always equal to the middle of input range (V0 ). Discussions about effects caused by the variation of the common mode voltage will be given in section III. Both input signals are allowed to vary all over the input range, from Vmin to Vmax . The comparators compare the input voltage and the reference voltages as shown in Fig. 1, however, only a few comparators whose reference voltages are around the input signal are important and the other comparators are useless. More than 2N 1 comparators output the same voltage level. They can be omitted to reduce their power consumption. As an example, let us consider the operation of the comparators in a 3-bit ash A/D converter when the input signal shown in Fig. 2 is applied to them. Vinp and Vinm at t = t1 are Vinp(i) and Vinm(ii) respectively. The output voltage levels of each comparator are illustrated in Fig. 3 where it is assumed that Vinp(i) and Vinm(ii) are between V1 and V2 , and between V1 and V2 respectively. The upper half of comparators for Vinp output high or low voltage according to their reference voltage. On the other hand all of the lower half of comparators, namely lower 2N 1 1 comparators, output high level because Vinp is much larger than V0 . The upper and lower half of comparators are dened as shown in Fig. 3. The lower half of comparators might be used for an error correction, however, not all of them are indispensable. The upper half of comparators for Vinm are also redundant because Vinm is less than V0 in contrast with a case of Vinp From the above example it seems that half of comparators for Vinp and Vinm are redundant and should be removed for

low-power operation and compact design. Unfortunately, both upper and lower half comparators are not always redundant. Their roles are changed according to the input voltage. When the input signals go across their common mode level (V0 ) the redundant comparators begin to act as signicant comparators. In case of Fig. 2 comparators which are useless before t = t2 become indispensable after t = t2 . This relation between the input signals and the position of redundant comparators is summarized in Table I. Positions of the redundant comparators are exchanged at Vinp = Vinm = V0 . Because Vinp and Vinm are balanced they do not require the same half of comparators simultaneously. When Vinp requires the upper half of comparators, Vinm is always fed to the lower half of comparator which is redundant half for Vinp . Therefore the comparators can be shared with Vinp and Vinm if two balanced input signals fed to comparators are exchanged at Vinp = Vinm = V0 . A ash A/D converter based on the proposed low-power technique is shown in Fig. 4. The A/D converter does not have redundant comparators and a novel T/H circuit is inserted in order to sharing the comparators with two input signals. The operation of the A/D converter is as followed: At rst, the two input signals are fed to a novel T/H circuit which hold input voltages and select appropriate comparators for the input signals. One of larger input signals is fed to the upper half of comparators and the other is applied to the lower half of comparators. The T/H circuit also outputs the most signicant bit (MSB) which is used at the N -bit binary decoder. The output voltages of comparators and MSB are converted into N -bit binary code in digital domain. III. C IRCUITS CONFIGURATIONS A block diagram of a ash A/D converter based on the proposed technique is shown in Fig. 5. A T/H circuit shown in Fig. 6 is used in the rst stage of the A/D converter. The T/H circuit consists of four switches realized by MOSFETs. The clock signal and the output voltage of a comparator which compares two input signals are applied to NAND gates and their output voltages are used to drive these switches. When Vinp is in the upper half of the input range switches realized by Msw1 and Msw2 are turned on. When Vinp is in the lower half of input range Msw3 and Msw4 are shorted to exchange the input signals. When clock signal is low, all of switches are opened and the output voltage is kept constant. During

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Vmax Vinp

Vmax 2N-1-1 + + + + + + + 2N-1-1 Vinm 0 Upper half of 0 1 1 1 Vinm(ii) 1 1 Lower half of Comparators unnecessary Comparators necessary

Vmax 2N-1-1 + + + + + + + 2N-1-1 Vmin Comparators for Vinm

V3 V2 V1 V0 V0 V-1 V-2 V-3

V3 V2 V1 V0 V-1 V-2 V-3

0 Upper half of 0 0 0 0 Lower half of 1 1 Comparators necessary Comparators unnecessary

Vinp(i)

Vinp(i)

Vinm(ii)

Vmin

Vmin Comparators for Vinp

Fig. 3.

Output voltage level of the conventional ash A/D converter

MSB Vinp Vupper

Vmax 2N-1-1 + (a) + + + + V-1 + + (b) (c) (d) (d) 1 1 0 0 Lower half of 1 (b) 1 necessary Comparators

Clock half Clock Delay MSB Digital Circuit N-1 bits N bits binary

V3 V2 Vinp(i) V1

0 Upper half of 0 Comparators necessary

Balanced inputs

Comparator Switches T/H circuit 2 differential Comparators

N-1

Thermometer codes

Fig. 5.

Block diagram of the proposed A/D converter

clk MSB MSB Vupper Msw3 Msw1

Vinm T/H circuit

Vlower

V0

(c)

Vinm(ii) V-2 V-3

+ - (a) 2N-1-1

Vinp

Comparator

Vmin

Fig. 4. Concept of the proposed low-power technique for a ash A/D converter

Msw4 Vinm Msw2

Vlower

Fig. 6.

Proposed T/H circuit

this term the following comparators evaluate the input signals. The output voltage of one of NAND gates are also used as the MSB of the A/D converter. A differential comparator shown in Fig. 7 is used in Fig. 5 and Fig. 6 [12]. The comparator consists of two differential amplier stages and a latch stage. A pair of single-end comparators used in the above discussion can be replaced by only one differential comparator. The proposed 3-bit ash A/D converter shown in Fig. 4 are realized by 4 differential comparators. Pair of comparators denoted by (a), (b), (c) and (d) are merged respectively. Therefore only 2N 1 + 1 comparators are required for the proposed ash A/D converters where one comparator is used in the T/H circuit. The above discussion is based on an identical condition which the common mode voltage of two input signals is assumed to be equal to the middle of input range. Unfortunately the common mode level usually deviates from its nominal

value in the actual circuit. When the input signals have offset voltages one of input signals might be out of input range of the upper or lower half of comparators and it might cause an error. The input range of the comparators are designed to be lapped over in actual design to prevent this error. IV. S IMULATIONS Performances of the A/D converter using the proposed technique are conrmed by HSPICE simulations. A set of 0.18m BSIM3v3 CMOS parameters is used for the simulations. The specications of the A/D converter and conditions of the simulations are summarized in Table. II Table III shows the power consumption of the conventional ash A/D converter and the A/D converter based on the

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VDD clk RL RL

Vout clk Vinp Vinm Vrefp Vrefm clk clk

Vout

clk

Vbias

Fig. 7.

Differential comparator TABLE II

Flash A/D converters based on the proposed low-power technique consist of only 2N 1 + 1 comparators. On the other hand a conventional N -bit ash converter requires 2N 1 comparators. The proposed technique ideally can reduce 50% of the power and the chip area required for the comparators. The reduction of the number of the comparators also saves the power consumption and the chip area of the previous stages because input capacitance of the comparators are also reduced drastically. As an example a 6-bit 524M sample/s A/D converter using the proposed technique is designed and its power consumption is evaluated by computer simulations. It is conrmed that the proposed technique can save 34 % of power consumption compared with the conventional one. R EFERENCES

S IMULATION CONDITIONS AND SPECIFICATIONS OF THE A/D CONVERTER Supply power voltage Maximum input signal frequency Sampling frequency Output voltage swing (differential) Resolution 1.8V 264MHz 528MHz 500mVpp 6bit

proposed technique at the maximum input frequency. The power consumption of the conventional A/D converter is 213 mW, on the other hand that of the proposed T/H circuit is suppressed to 144 mV. This is 66 % of the conventional A/D converters value. Thanks to the proposed technique, the number of comparators and their power consumption is drastically reduced and a reduction of input capacitor of the comparators brings reduction of the power consumption in the all previous stages, for example, the power consumption at an output buffer of T/H circuit and switches can be half. It should be mentioned that the proposed technique can also reduce the chip area of the A/D converter not only its power consumption. A low-power technique reported in Ref. [11] can reduce its power consumption, however, its chip area is as large as the conventional ash A/D converter. On the other hand our proposed low-power technique can reduce its chip area. This is one of the very important advantage over the conventional low-power technique. It is also conrmed that the A/D converter using the proposed technique shows almost the same DNL and INL characteristics.
TABLE III C OMPARISON OF THE CURRENT CONSUMPTION Power consumption Reduction Ratio Conventional 213 mW Proposed 144 mW 66 %

[1] G. Geelen, A 6 b 1.1 GSample/s CMOS A/D converter, 2001 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.128 - 129 and 438, Feb. 2001. [2] M. Choi, A. A. Abidi, A 6-b 1.3-Gsample/s A/D converter in 0.35m CMOS, IEEE Journal of Solid-State Circuits, Volume 36, Issue 12, pp18471858, Dec. 2001. [3] K. Uyttenhove, M. S. J. Steyaert, A 1.8-V 6-bit 1.3-GHz ash ADC in 0.25-/m CMOS, IEEE Journal of Solid-State Circuits, Volume 38, Issue 7, pp11151122, July. 2003. [4] C. Sandner, M. Clara, A. Santner, T. Hartig, F. Kuttner, A 6-bit 1.2-GS/s low-power ash-ADC in 0.13-/spl mu/m digital CMOS, IEEE Journal of Solid-State Circuits, Volume 40, Issue 7, pp14991505, July. 2005. [5] S. Sheikhaei, S. Mirabbasi, A. Ivanov, A 4-bit 5 GS/s ash A/D converter in 0.18 /spl mu/m CMOS, IEEE International Symposium on Circuits and Systems, Vol. 6, pp. 61386141, May 2005. [6] Nikkei Electronics, no.932, 8-14 2006, Nikkei Business Publications, Inc. (in Japanese) [7] D. A. Johns, K. Martin, Analog Ingegrated Circuit Design, John Willey & Sons, Inc. 1997. [8] Ruby van de Plassche ,CMOS Integrated Analog to Digital and Digital to Analog Converters, Kluwer Academic Publishers, 2003. [9] A. N. Karanicolas , A 2.7-V 300-MS/s Track-and-Hold Amplier, IEEE Journal of Solid State Circuits, vol. 32, pp. 1961-1967, Dec 1997. [10] T. Sato, et al. 4GB/s Track and hold circuit using parasitic capacitance canceler, Proc. of European Solid-State Circuits Conference, pp.347 350, 2004 [11] Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee, Trong-Yen Lee, New power saving design method for CMOS ash ADC The 2004 47th Midwest Symposium on Circuits and Systems, Volume 3, pp. 3714, July 2004. [12] B. Razavi, and B.A. Woody, Design techniques for high-speed, highresolution comparators, IEEE Journal of Solid-State Circuits, Volume 27, Issue 12, pp19161926, Dec. 1992.

V. C ONCLUSIONS This paper proposes a low-power and small chip area design technique for ash analog-to-digital converters. The proposed technique reduces the power consumption of ash A/D converters by reducing the number of their comparators.

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