What are HDLs? HDL stands for Hardware Description Language.

To day the most popular HDLs are VHDL and Verilog. Generally HDLs are used to describe the digital hardware.

What is VHDL? VHDL stands for Very High speed Integrated circuit Hardware Description Language. This is used to describe digital hardware which can be used for computer based simulation and also for Synthesizing a digital circuit either for ASIC of FPGA.

What is Verilog? Verilog is another Hardware Description language which is used in industry for simulating and synthesizing digital hardware.

What are essential things to be taken care while writing the VHDL code? When we are writing VHDL code aiming for synthesis that is important to understand the relationship between the code constructs and actual hardware. That is every VHDL statements should infer some practical hardware. So that kind of VHDL code is synthesizable. But when our requirement is only simulation all the constructs of VHDL can be used.

What are different modeling styles used in writing VHDL code? There are mainly three modeling styles used in VHDL to describe a digital circuit
y y y

Dataflow style of modeling, Structural modeling Behavioral modeling.

In dataflow style of modeling the logic is realized in the form of Boolean expression. In structural style of modeling the required logic is implemented as inter connection between smaller components, where as in behavioral modeling the required logic is implemented in sequential code which is also called behavioral code.

Is the behavioral code can be synthesized? Yes, If the behavioral code is written properly then it is synthesizable, but all constructs of behavioral code are not synthesizable. So even a behavioral code can be synthesizable if it follows some rules.

The code which is used for a FPGA synthesis can we used for ASIC synthesis? Broadly speaking answer is Yes. If the code is written by using general constructs of VHDL then it is useful for even ASIC synthesis, but where as the code written by assuming some special FPGA libraries than it is not synthesizable for ASIC.

Can VHDL and Verilog work together? It is possible while realizing system one module may be implemented in VHDL and the other module we can be implemented in verilog and they can work together.

What is Mixed Signal in VLSI design? Mixed signal VLSI design got different meaning in different contexts for broadly speaking in VLSI design when both analog and digital circuit concepts together are used to implement a circuit then it is called mixed signal in VLSI design. For Example that can be an analog to digital converter. In which one side we have analog issues where as the other side we have digital issues.

Is VHDL used for analog design? The original VHDL is not suitable for analog design but today there are extensions for VHDL which are useful for describing an analog design. But these are only used for simulation up to some level. Ex: AHDL (Analog Hardware Description Language) AMS VHDL (Analog Mixed Signal and VHDL)

Is VHDL is Comparable to Verilog? Since both VHDL and Verilog are Hardware Description languages. There are several constructs in VHDL, which have counter parts in Verilog Ex. The process in VHDL is comparable to always statements in verilog and the signal in VHDL is comparable to wire in verilog. There exists lot many similarities between VHDL and Verilog. Since both are designed for Hardware description.

Is VHDL is Object oriented or structure Language VHDL is object oriented it has the concept of object and several other features which generally we see in object oriented programming languages. So VHDL has to be considered under category of object oriented. The VHDL is derived from programming language ADA which is object oriented language. A lot of concepts in object oriented are even applicable to VHDL. Ex: Operator overloading, the concept of classes and Object etc., VHDL is not fully object oriented because certain important concepts of object oriented programming languages like inheritance is not supported in VHDL. So even VHDL object oriented but it is not fully object oriented languages.

Is Verilog is comparable to C? Yes. Verilog language has lot of similarities with C. The operators, the expressions and several other constructs in verilog are comparable to C.

Which are the most widely used Hardware Description Languages today? Today industry relies on two hardware description languages they are VHDL, Verilog

Why engineers prefer verilog today? The main reason for giving high performance to Verilog is, Its similarity to C programming language. Since most of the engineers are already familiar with c programming language it became easy for them to learn verilog. Today several EDA companies are offering full support to verilog this is also another important reason for prefer verilog in industry. Please read the following article for comparing VHDL, Verilog and C programming languages. http://www.angelfire.com/in/rajesh52/verilogvhdl.html

Is VHDL useful for Simulation or Synthesis? VHDL is useful and both simulation and synthesis. The initial aim while designing the VHDL was only simulation. But later the language is extended and synthesis feature is added. So VHDL code can be used for synthesis of a digital circuit either an ASIC or FPGA.

What is an effort required to convert one VHDL code to make it suitable for synthesis? If the hardware description language code is written in RTL form (Registers Transfer Level) then it is highly suitable for synthesis. Where as if the hardware description language code in behavioral form, which is a lengthy sequence code written to describe the system. Then it may not be suitable for synthesis or lot of effort is required in generating the hardware for that code.

What is RTL? Register Transfer Level (RTL) is a technique in which the logic is described as a dataflow between various registers with appropriate combinational logic in between. RTL is a preferred coding style for synthesis in industry

Does anybody use HDL only for Simulation purpose? Yes. Engineers may use hardware description language only for simulations purpose. In that case they are not worried about the synthesis of the code. Their aim is only to describe the functionality of the logic in hardware description language.

Can we use C for FPGA based design? Yes. Today we have some compliers and Synthesizers which can understand c code and can generate a bit file which can be programmed on to FPGA. But not all the constructs of C are synthesizable. That means only a portion of C language can be used for hardware design.

What is Simulation? Simulation (in the context of VLSI) is the process in which a circuit is the verified by subjecting it with appropriate test input. Typically simulation involves making a model (which can be either a VHDL code or Verilog code) and verifying it with appropriate test inputs.

What is Synthesis?

Synthesis is a process in which the model at higher abstraction level is converted to an implementable form. There are two types of synthesis technologies which are very popular in digital design. If we are generating a layout using cell libraries it is called ASIC synthesis, where as if we are generating a bit file to program an FPGA then it is called FPGA Synthesis. VHDL OPERATION VHDL is commonly used to write text models that describe a logic circuit. Such a model is processed by a synthesis program, only if it is part of the logic design. A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a testbench. VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs (processes) differ in syntax from the parallel constructs in Ada (tasks). Like Ada, VHDL is strongly typed and is not case sensitive. In order to directly represent operations which are common in hardware, there are many features of VHDL which are not found in Ada, such as an extended set of Boolean operators including nand and nor. VHDL also allows arrays to be indexed in either ascending or descending direction; both conventions are used in hardware, whereas in Ada and most programming languages only ascending indexing is available. VHDL has file input and output capabilities, and can be used as a generalpurpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data. There are some VHDL compilers which build executable binaries. In this case, it might be possible to use VHDL to write a testbench to verify the functionality of the design using files on the host computer to define stimuli, to interact with the user, and to compare results with those expected. However, most designers leave this job to the simulator. It is relatively easy for an inexperienced developer to produce code that simulates successfully but that cannot be synthesized into a real device, or is too large to be practical. One particular pitfall is the accidental production

of transparent latches rather than D-type flip-flops as storage elements.[original

research?]

One can design hardware in a VHDL IDE (for FPGA implementation such as Xilinx ISE, Altera Quartus, Synopsys Synplify or Mentor Graphics HDL Designer) to produce the RTL schematic of the desired circuit. After that, the generated schematic can be verified using simulation software which shows the waveforms of inputs and outputs of the circuit after generating the appropriate testbench. To generate an appropriate testbench for a particular circuit or VHDL code, the inputs have to be defined correctly. For example, for clock input, a loop process or an iterative statement is required.[original research?] A final point is that when a VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device such as a CPLD or FPGA, then it is the actual hardware being configured, rather than the VHDL code being "executed" as if on some form of a processor chip. [edit]Advantages The key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is that VHDL allows the description of a concurrent system. VHDL is a dataflow language, unlike procedural computing languages such as BASIC, C, and assembly code, which all run sequentially, one instruction at a time. VHDL project is multipurpose. Being created once, a calculation block can be used in many other projects. However, many formational and functional block parameters can be tuned (capacity parameters, memory size, element base, block composition and interconnection structure). VHDL project is portable. Being created for one element base, a computing device project can be ported on another element base, for example VLSI with various technologies

Objects for a VHDL Compiler

Introduction

This web page publishes a set of C++ objects developed for a VHDL compiler. I developed this software in early 1999, but it was never used in a product (it's a long story). This software consists of about 5K lines of source code and comments. This source code is free for non-commercial use. If you have a commercial appliction in mind, let me know and I'm sure that we can work out a reasonable license. The VHDL compiler was the second hardware design language compiler my colleagues and I developed. The first compiler was for the Verilog hardware design language. The Verilog compiler, like the VHDL compiler we later developed, was targeted at the powerPC microprocessor. We started work on the VHDL compiler because, at the time, about half the designers used Verilog and half used VHDL. Without support for both languages you miss half of the market. VHDL can be used to specify a hardware design (for implementation in a VLSI chip or in an FPGA). The process of compiling VHDL into the logic "netlist" that defines a hardware design is referred to as logic synthesis. VHDL can also be used to define the behavior of a hardware device or a system as well. For supporting behavioral models VHDL provides delays, events and processes. Behavioral VHDL is simulated, usually by compiling VHDL into an abstract instruction set (logically similar to Java byte code) or into machine code for a microprocessor.

APSIC
An application-specific integrated circuit (ASIC) (pronounced / e s k/) is an integrated circuit (IC)

customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Application-specific standard products (ASSPs) are intermediate between ASICs and industry standard integrated circuits like the 7400 or the 4000 series. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (system-on-a-chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilogor VHDL, to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern-day technology for building a breadboard or prototype from standard parts; programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design even in production. The non-recurring engineering cost of an ASIC can run into the millions of dollars.
Contents
[hide]

1 History 2 Standard cell design 3 Gate array design 4 Full-custom design 5 Structured design 6 Cell libraries, IP-based design, hard and soft macros 7 Multi-project wafers 8 ASIC suppliers

o o

8.1 IDM ASIC suppliers 8.2 Fabless ASIC suppliers

9 See also 10 Further reading

[edit]History The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. An early successful commercial application was the ULA circuitry found in the 8-bit ZX81 and ZX Spectrum low-end personal computers, introduced in 1981 and 1982. These were used by Sinclair Research (UK) essentially as a low-cost I/O solution aimed at handling the computer's graphics. Some versions of ZX81/Timex Sinclair 1000 used just four chips (ULA, 2Kx8 RAM, 8Kx8 ROM, Z80A CPU) to implement an entire mass-market personal computer with built-in BASIC interpreter. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements. [edit]Standard

cell design

Main article: standard cell

In the mid 1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers ended up using factory-specific tools to complete the implementation of their designs. A solution to this problem, which also yielded a much higher density device, was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, that could also be represented in third-party tools. Standard Cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost. By the late 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist. Standard-cell Integrated Circuits(ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice. 1. A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from Requirements analysis. 2. The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (Register transfer level) design. 3. Suitability for purpose is verified by functional verification. This may include such techniques as logic simulation, formal verification, emulation, or creating an equivalent pure software model (see Simics, for example). Each technique has advantages and disadvantages, and often several methods are used. 4. Logic synthesis transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates (such as 2 input nor, 2 input nand, inverters, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist. 5. The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. 6. The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a sufficient rather than globally optimal solution. The output is a file which can be used to create a set

of photomasks enabling a semiconductor fabrication facility (commonly called a 'fab') to produce physical ICs. 7. Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a digital circuit, this will then be further mapped into delay information, from which the circuit performance can be estimated, usually by static timing analysis. This, and other final tests such asdesign rule checking and power analysis (collectively called signoff) are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. The design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than full custom design. Standard Cells produce a design density that is cost effective, and they can also integrate IP cores and SRAM (Static Random Access Memory) effectively, unlike Gate Arrays. [edit]Gate

array design

Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization in other words, unconnected. The physical design process then defines the interconnections of the final device. For most ASIC manufacturers, this consists of from two to as many as nine metal layers, each metal layer running perpendicular to the one below it. Non-recurring engineering costs are much lower, as photolithographic masks are required only for the metal layers, and production cycles are much shorter, as metallization is a comparatively quick process. Gate array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the interconnect. Pure, logic-only gate array design is rarely implemented by circuit designers today, having been replaced almost entirely by field-programmable devices, such asfield-programmable gate arrays (FPGAs), which can be programmed by the user and thus offer minimal tooling charges (non-recurring engineering (NRE)), only marginally increased piece part cost, and comparable performance. Today, gate arrays are evolving into structured ASICs that consist of a large IP core like aCPU, DSP unit, peripherals, standard interfaces,

integrated memories SRAM, and a block of reconfigurable, uncommited logic. This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and "system-on-a-chip" requires far more than just logic blocks. In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous. Process engineers more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers. [edit]Full-custom

design

Main article: Full custom By contrast, full-custom ASIC design defines all the photolithographic layers of the device. Full-custom design is used for both ASIC design and for standard product design. The benefits of full-custom design usually include reduced area (and therefore recurring component cost), performance improvements, and also the ability to integrate analog components and other pre-designed and thus fully verified components, such as microprocessor cores that form a system-on-chip. The disadvantages of full-custom design can include increased manufacturing and design time, increased nonrecurring engineering costs, more complexity in the computer-aided design (CAD) system, and a much higher skill requirement on the part of the design team. For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-limiting aspect of the design. [edit]Structured

design

Main article: Structured ASIC platform Structured ASIC design (also referred to as "platform ASIC design"), is a relatively new term in the industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). One definition states that In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be customproduced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than

"standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.
[citation needed]

This is effectively the same definition as a gate array. What makes a structured ASIC different is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC, the use of predefined metallization is primarily to reduce cost of the mask sets as well as making the design cycle time significantly shorter. For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves; these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array. Likewise, the design tools used for structured ASIC can be substantially lower cost and easier (faster) to use than cellbased tools, because they do not have to perform all the functions that cell-based tools do. In some cases, the structured ASIC vendor requires that customized tools for their device (e.g., custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly. One other important aspect about structured ASIC is that it allows intellectual property (IP) that is common to certain applications or industry segments to be "built in", rather than "designed in". By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC

CPLD
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. Features in common with PALs:  Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up.  For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families. Features in common with FPGAs:

Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.

Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip nonvolatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory. The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded bystandard logic products, that offered no programmability and were "programmed" by wiring several standard logic chips together. The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on Look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (e.g. sum of products).