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  • VLSI Circuits Physical Design and Layout Techniques

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    siva_pothi
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    This document provides an overview of the key concepts and methodologies in the physical design of very large scale integrated (VLSI) circuits. It discusses the layout rules and approaches for standard cells, gate arrays, and field programmable gate arrays (FPGAs). Placement techniques include partitioning, floorplanning, and placement using simulated annealing. Routing methods include maze routing, line searching, Steiner trees, and multi-commodity flow techniques. The document also covers performance issues like timing-driven placement and routing, delay models, and single layer routing approaches.

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    Physical Design of VLSI Circuits

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    This document provides an overview of the key concepts and methodologies in the physical design of very large scale integrated (VLSI) circuits. It discusses the layout rules and approaches for standard cells, gate arrays, and field programmable gate arrays (FPGAs). Placement techniques include partitioning, floorplanning, and placement using simulated annealing. Routing methods include maze routing, line searching, Steiner trees, and multi-commodity flow techniques. The document also covers performance issues like timing-driven placement and routing, delay models, and single layer routing approaches.

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    Attribution Non-Commercial (BY-NC)
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    792 просмотров1 страница

    VLSI Circuits Physical Design and Layout Techniques

    Загружено:

    siva_pothi
    This document provides an overview of the key concepts and methodologies in the physical design of very large scale integrated (VLSI) circuits. It discusses the layout rules and approaches for standard cells, gate arrays, and field programmable gate arrays (FPGAs). Placement techniques include partitioning, floorplanning, and placement using simulated annealing. Routing methods include maze routing, line searching, Steiner trees, and multi-commodity flow techniques. The document also covers performance issues like timing-driven placement and routing, delay models, and single layer routing approaches.

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате DOCX, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 1

    L PHYSICAL DESIGN OF VLSI CIRCUITS 3

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    INTRODUCTION TO VLSI TECHNOLOGY Layout Rules-Circuit abstraction Cell generation using programmable logic array transistor chaining, Wein Berger arrays and gate matrices-layout of standard cells gate arrays and sea of gates, field programmable gate array(FPGA)-layout methodologies-Packaging-Computational ComplexityAlgorithmic Paradigms PLACEMENT USING TOP-DOWN APPROACH Partitioning: Approximation of Hyper Graphs with Graphs, Kernighan-Lin Heuristic- Ratio-cutpartition with capacity and i/o constraints; Floor planning: Rectangular dual floor planninghierarchical approach- simulated annealing- Floor plan sizing; Placement: Cost function- force directed method- placement by simulated annealing- partitioning placement- module placement on a resistive network regular placement- linear placement ROUTING USING TOP DOWN APPROACH Fundamentals: Maze running- line searching- Steiner trees; Global Routing: Sequential Approaches- hierarchical approaches- multi-commodity flow based techniques- Randomised Routing- One Step approach- Integer Linear Programming; Detailed Routing: Channel RoutingSwitch box routing; Routing in FPGA: Array based FPGA- Row based FPGAs PERFORMANCE ISSUES IN CIRCUIT LAYOUT Delay Models: Gate Delay Models- Models for interconnected Delay- Delay in RC trees. Timing Driven Placement: Zero Stack Algorithm- Weight based placement- Linear Programming Approach Timing Driving Routing: Delay Minimization- Click Skew Problem- Buffered Clock Trees. Minimization: constrained via Minimization- unconstrained via Minimization- Other issues in minimization SINGLE LAYER ROUTING, CELL GENERATION AND COMPACTION Planar subset problem (PSP) - Single layer global routing- Single Layer Global Routing- Single Layer detailed Routing- Wire length and bend minimization technique Over The Cell (OTC) RoutingMultiple chip modules (MCM)- Programmable Logic Arrays- Transistor chaining- Wein Burger Arrays- Gate matrix layout- 1D compaction- 2D compaction REFERENCES 1. Sarafzadeh, C.K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1995 2. Preas M. Lorenzatti, Physical Design and Automation of VLSI systems, Benjamin Cummins Publishers, 1998. 3. Ban Wong, et.al. , Nano CMOS Circuit and Physical Design Wiley 2004. 4. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic, 2002 5. Sadiq M. Sait, Habib Youssef, VLSI Physical Design Automation, Theory and Practice World Scientific Publishing Company, 2003 6. Bryan T. Preas Publishers,1998 Physical Design Automation of VLSI system, Benjamin Cummings

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