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Low Voltage Single-Stage Amplifier with Wide Output Range

Yang WANG Peking University, Beijing 100871, China ywang @pkmedu.cn Abstract: A single-stage wide output amplifier capable of operating at minimum supply voltage has been described. The simple circuit with low voltage current mirrors is placed between both input differential pair and push-pull output for achieving internal low impedance nodes and minimum supply voltage. This amplifier can be available to work at supply voltage around 1 V for standard CMOS processes. The block diagram of the low voltage amplifier is given in Fig.1, which consists chiefly of the input differential pair, intermediate circuit and push-pull output. To achieve the minimum supply voltage, the amplifier requires the intermediate circuit to be able to operate at the low supply voltage satisfied Eq. (1). Also, to have first-order frequency response, i.e., to form single-stage structure, the amplifier has to involve the intermediate circuit with internal low impedance nodes with respect to small signals. Thus a high impedance node can be kept only at the output terminal.
V DD

I. Introduction
As feature size of transistors is scaling down step by step and portable systems are gaining more importance in electronic products, more and more circuits are being demanded to be able to operate in low supply voltage environments, which has resulted in researchers' attention paid to 1-Volt electronics"]. Theoretically, the minimum supply voltage can be reduced to a threshold voltage (V,) plus two saturation voltages (VDSat) for well-design CMOS low voltage circuits, i.e.,

- 8 .

.t.

. . .

,Intermediate Circuit
.I
. . . . . .

. .

:+< Ts

GND

This value turns out to be around 1V for standard CMOS processes. Amplifiers as the most commonly basic building block in analog and mixed-mode circuits have been extensively investigated for quite a long time. A typical amplifier that can meet the demand for the minimum supply voltage is the folded cascode structure in the existing simple amplifier^[^-^^. However, class-A output is employed and output voltage swing is limited to no more than VDD-3VDS- for this structure. A single-stage amplifier with low voltage current mirrors (LVCMs) and push-pull output has been described in this paper so as to obtain the minimum supply voltage, large output range and wide bandwidth. After brief description of fundamental working principle, analyses on characteristics have been carried out and some approximate relations among the performance and design parameters have been given. Moreover, several of major issues relating to design have been discussed. As a specific example, a 1-V amplifier has been designed and simulated with SPICE. II. Topology of the Amplifier

Fig. 1. The block diagram of structure The typical building blocks applied to the intermediate circuit are usually current mirrors. Since the input circuit is composed of a differential pair loaded by the diode connected MOS transistors in the conventional balanced amplifier with three simple current mirrors and a single-ended the minimum supply voltage of this input differential pair is determined by VDDmin=VGSload+lVDSsatlI+lVDSsatld where VGsloadis gate-source voltage for the diode connected MOS transistor (not to draw out in Fig.l), V D S ~ ~ I VDSsatl3 are the saturation voltages for input and and tail current transistors respectively. Therefore, the minimum supply voltage for this conventional balanced amplifier is at least V+3VDssat. It is larger than that given by Eq. (1) even though this structure can meet the requirement of single-pole well. Fig. 2 represents the overall amplifier working at minimum supply voltage. Transistors, T3, T5, T9 and TI,, constitute a LVCM"'*' with multiplication factor B, and so do transistors, T4, T6, Tlo and TI*. The LVCM instead

0-7803-6677-8/01/$10.0002001 IEEE.

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of the simple current mirror in the conventional balanced amplifier acts as the load of the input differential pair. Because the voltages at nodes, 4 and 5, are reduced from Vosld to V D S ~ ~ ,minimum supply voltage needed by the the input differential pair is VDDmin==(Vl+2VDSsar,
3vDSsatl

For standard CMOS processes, V, is generally larger so than VDS~~,,the VDD- satisfies Eq.(1). The minimum supply voltage of the intermediate circuit is the same as that of the input differential pair owing to LVCMs. The minimum supply voltage of push-pull output is ~ ~ x { V GIVcssl, ~VDSS~~}. normally smaller than S~, It is that of the input and intermediate circuits. As a result, the minimum attainable supply voltage of this amplifier is consistent with the Eq.(l), only V, is determined by maximum of VTnand IVTpl.
.
. . . .

VDD

- . . . .

Node

4,5
8,9

Node Resistance l/[gm9gm3(rdss//rdsll)l l/gni3 7

Resistance 1 /gm7 rdsd/rds8

. . . . . . . . . . . . . . . . . . -

GND Fig. 2. The low voltage amplifier

III. Analyses of Properties


Being in the saturation region, transistors, TI, and Tz TI3,demand that input common-mode voltage (V,,) has to be in the range:

& G C F E - ~ v r i1 vIcM v,, - Jzr,rS;;- JK'Z-lvnl 5


Keeping output transistors, Ts and Ts, in saturation restricts the output voltage to the range:

jzB7;r/-s;;vent 5 5

vDD

- J%ZG

For LVCM, an often concerned problem is the maintenance of T3 and T9 in saturation due to the cascode transistor. It is unnecessary that Tg is large size as long as its biasing current (Ill) is a small constant. However, making T3 in saturation must limit its drain current to the range:

-1 (2) 2 < +VG9 -vr9E P


where p=clC,(W/L). In other words, for a given tail current (Il3). the T3 ought to have aspect ratio enough to keep it in the saturation region. In addition, to ensure T3

- tan-' (

2nC6GBW
gml

)+tad(---

7cc6GBW
gm1

where C,, is parasitic capacitance at node n. In comparison with the conventional balanced amplifier, the Ill and 112 biasing LVCMs will impose on the phase

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margin owing to gm9(rdsbs4//Idsl relevant to them. The phase shift caused by node 4(5) reaches the minimum when Tg and Tlo arrive to the weak inversion. For the noise sources, the cascode transistors, Tg and Tlo, may be visualized as source followers, the drain currents of which are directly controlled by the bias currents, so output noise currents of the cascode transistors are zero. Moreover, the noise generated by TI3 is common-mode signal. With canceled by taking a differential output, it does not contribute to the output voltage. Consequently, the transistors contributing to the output voltage are TI,^, T3,4, T5,6, T7,8, and T11.12. For thermal noise, V:l is equal to 8kTAf/3gml. The total equivalent input noise level is given by

where AV1=(v8-v9)/vin=gml/gd. Notice that the T II noise The total contributing to output is dependent on gmll/gml. equivalent input noise can be reduced as increasing A,] and/or B. A summary of key properties of this amplifier, when all transistors operate in the saturation region, is given by the approximate expressions in Table 2. Table 2. Key properties of the amplifier Avo Bgml(rdsd/rdsd G, Bgml rout rdsd/rdsa SR BWCL GBW B~~I/~NC~+CL) fnd89 gd27G fnd45 gm9gndrds9//rdsl 1)/27Cc4 fndFfzd2 gmd2xc6 fd7 12 C (CL+c7)(rdsd/rdsd /7 PM Eq. (4) VDD~v+2vDSsat VICM,rmge VDD'~VDSsat13~-VDSsaO-~vDSsatl I VDD'2VDSndn vout, swing, max (lfB)(I13+2II 1)VDD Pstatic NnenlwJ Eq. (5) HJ33 PiV?/(32113)
B is current ratio of load current mirrors

enough to ensure VDs5>VGss-VT5for a given multiplication factor B. Notice that (W/L), and (WQ, if too large, make A,] decrease, and this will cause performance deterioration of the total DC gain and noise. For the simple current mirror composed of T7 and T8, the larger the (W/L)7 and (W/L)g become, the easier it is to keep T5 in saturation due to a rise of voltage at node 6. With due regard for appropriate gain and power dissipation, the current Ill equal to II2is usually biased to a small constant. Also, one of input transistors will be off when input differential voltage is large. The smallest current through output transistors is equal to BII1. The minimum V D of output transistors depends in part on ~ BIII. In order to have maximum output swing, both Ill and II2 should be designed as small as possible too. Another merit of the decrease in Ill is the increase in gmgrdsg. This is beneficial to the phase margin (see Eq44)). The voltages at nodes, 4 and 5, which have a bearing on the operating region of T3 and TA, are partially determined by the gate voltages of Tg and Tlo.The body biasing effects do not occur if the substrates of T9 and Tlo are connected to the sources for P-well process. It is ease to make T3 and T4 in saturation that VDS, and VDs4 are increased in this case. SR (slew rate) and GBW are directly proportional to B. With increasing B, we can obtain a large SR and GBW, but PM will decrease if B is taken too large. In addition, in order to guarantee the output noise dominated by the noise of input differential pair, the larger the gain AV1, the better. On the contrary, the reduction in gd will increase resistance at node 4 and degrade the phase margin. For those reasons a compromise should be made for parameters of B and AV1 during design. The DC gain is relevant to transconductance (g,,) of input transistors and output resistance (rout). To have adequate gain, the amplifier should possess enough gml and channel length of output transistors. In careful consideration of power dissipation, the configuration of amplifier may be employed that has (W/L)3=(W/L)5 and (W/L)s=B(W/L)7 under the ideal conditions. Nevertheless, the precision of current mirrors becomes worse for low supply voltage. This asymmetric configuration will dramatically affect the performance of the amplifier.

IV.Design Considerations
With the intention of maintaining the current source transistors, TI1 and Tlz, in saturation, the large aspect ratios of T3 and T4have to be taken for reducing voltages at nodes, 8 and 9. On the other hand, considering the T5 in saturation, (W/L)3 should also be designed large

V. Design Example and Simulation Results


A 1-V amplifier has been designed as an example using parameters of the MOSIS P-well 2.0um-CMOS process. The threshold voltages are -0.7V and 0.W for PMOS and nMOS respectively. For a given SR=IV/us, BII3 should be equal to CLSR=~OUA a rough as

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estimation for capacitance load C,=lOpF. Having a trade-off between the transconductance and phase margin, we took B=2. Thus II3 was about 5uA. If the designed GBW was 3M&, the aspect ratio of input transistors was estimated to be about 100 for KP,=18uAN2. After a compromise between phase margin and noise was made, the gain A,] was chosen as 2, i.e., g,,-,=g,,12. Supposing I1 was approximately equal to I3 and KP,,=2.5KPp, the (WLJ3 was about 10. Due to B=2, the (W/L)5 was equal to 20. If Ill=112=113/10=0.5uA ~ and (W/L)9=6,the feasible gate voltages ( V G and VGIO) of cascode transistors in the LVCMs were from 1.OV to 1.5V by Eq. (3). Vm and VGlo were therefore taken as IV(=VDD).The maximum input current for LVCM was 9uA from Eq. (2). This was larger than II3+Ill=5.5uA. Consequently, the LVCMs could always be available for the bias currents. Table 3. Transistor sizes Transistor W/L Transistor W/L

Nh r a t em l

20nVm/./Hz
28dB(f=GBW) 48dB(f=GBW) 6uA

PSm'
Gm

41dB 217uAN

Psm-

vTn=o.8v,vTp=-o.7v. CL=lOpF, VDD=lv

VI. Conclusion
Because a circuit with low voltage current mirrors is placed between both input differential pair and push-pull output, the amplifier with minimum supply voltage has been obtained, which has first-order frequency response and symmetrical loads for the input transistors. The amplifier working at 1V has been designed and simulated by SPICE for standard CMOS processes. Despite the fact that low voltage current mirrors lead in two extra nodes and rise slightly up in power dissipation, those weaknesses can become so small by means of optimal design that they have a weak influence on the main performances as illustrated in our example.

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References
[l] J. Huijsing, R. Plassche, and W. Sansen., Eds., Analog Circuit Design: 1-Volt Electronics, MixedMode System, Low-Noise and RF Power Amplij?ers for Telecommunication, (Kluwer Academic Publishers, Boston/Dordrecht/London, 1999), p.1 [2] R. Castello, F. Montecchi, F. Rezzi, and A. Baschirotto, IEEE Trans. On CAS-I, 42, 11, 827 (1995) [3] S. Rabii and B. A. Wooley, IEEE J. Of SSC, 32,6, 783 (1997) [4] Y. Wang, Proc. of China Fifieenth Con$ on Circuits and Systems, (Guangzhou,China,l999), p.159 [ 5 ] E. Sanchez-Sinencio and J. Silva-Martinez, IEE Proc.-CDS, 147,1, 3(2000) [6] K. Laker and W. Sansen, Design of Analog Integrated Circuits and Systems, (McGraw-Hill Inc. 1994), p.575 [7] A. Baschirotto and R. Castello, in Analog Circuit Design, eds., J. Huijsing, R. Plassche and W. Sansen (Kluwer Academic Publishers, Boston/ Dordrechu London, 1999), p.69 [SI V. Peluso, M. Steyaert, and W. Sansen, Design o f Low-Voltage Low-Power CMOS Delta-Sigma A D Converters, (Kluwer Academic Publishers, Boston/ Dordrechtl London, 1999), p.61

All transistor sizes for the design are shown in Table 3. The simulated frequency response is shown in Fig. 3.
60
40-

[ 1 a
20
0 -

-20 -

-40
-60

Fig. 3. Frequency response The chief simulation results predicting performances of the amplifier are summarized in Table 4 for 1V supply voltage.

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