A Brief History

1958: First integrated circuit

Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2003
Intel Pentium 4 uprocessor (55 million transistors)
512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
VLSI Applications
VLSI is an implementation technology for electronic circuitry - analog or
digital
It is concerned with forming a pattern of interconnected switches and
gates on the surface of a crystal of semiconductor
Microprocessors
personal computers
microcontrollers
Memory - DRAM / SRAM
Special Purpose Processors - ASICS (CD players, DSP applications)
Optical Switches
Has made highly sophisticated control systems mass-producible and
therefore cheap
Invention of the Transistor
Vacuum tubes ruled in first half of 20
th
century
Large, expensive, power-hungry, unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Semiconductors and Doping
Adding trace amounts of certain materials to semiconductors
alters the crystal structure and can change their electrical
properties
in particular it can change the number of free electrons or holes
N-Type
semiconductor has free electrons
dopant is (typically) phosphorus, arsenic, antimony
P-Type
semiconductor has free holes
dopant is (typically) boron, indium, gallium
Dopants are usually implanted into the semiconductor using
Implant Technology
1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit uProc
Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Year
T
r
a
n
s
i
s
t
o
r
s
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro
Pentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
(b)
+
-
0 < V
g
< V
t
depletion region
(c)
+
-
V
g
> V
t
depletion region
inversion region
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
V
g
V
s
V
d
V
gd
V
gs
V
ds
+
-
+
-
+
-
nMOS Cutoff
No channel
I
ds
= 0
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
nMOS Linear
Channel forms
Current flows from d to s
e
-
from s to d
I
ds
increases with V
ds
Similar to linear resistor
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s
d
b
g
s
d
I
ds
nMOS Saturation
Channel pinches off
I
ds
independent of V
ds
We say current saturates
Similar to current source
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s
d
I
ds
pMOS Transistor
Similar, but doping and voltages reversed
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
Power Supply Voltage
GND = 0 V
In 1980s, V
DD
= 5V
V
DD
has decreased in modern processes
High V
DD
would damage modern tiny transistors
Lower V
DD
saves power
V
DD
= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to
drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?
Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
=
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
Channel Charge
MOS structure looks like parallel plate
capacitor while operating in inversion
Gate oxide channel
Q
channel
= CV
C =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V =
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
Channel Charge
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide channel
Q
channel
= CV
C = C
g
= c
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator, c
ox
= 3.9)
polysilicon
gate
C
ox
= c
ox
/ t
ox
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = uE u called mobility
E =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = uE u called mobility
E = V
ds
/L
Time for carrier to cross channel:
t =
Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = uE u called mobility
E = V
ds
/L
Time for carrier to cross channel:
t = L / v
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
ds
I =
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ds
Q
I
t
=
=
nMOS Linear I-V
Now we know
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W
V
C V V V
L
V
V V V
u
|
=
| |
=
|
\ .
| |
=
|
\ .
ox
=
W
C
L
| u
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
ds
I =
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
2
dsat
ds gs t dsat
V
I V V V |
| |
=
|
\ .
nMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V
|
|
| |
=
|
\ .
=
nMOS I-V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V
|
|

<

| |
= <
|
\ .

>

Shockley 1
st
order transistor models
pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility u
p
is determined by holes
Thus pMOS must be wider to provide same
current
Channel Length Modulation
Reverse-biased p-n junctions form a
depletion region
Region between n and p with no carriers
Width of depletion L
d
region grows with reverse
bias
L
eff
= L L
d
Shorter L
eff
gives more current
I
ds
increases with V
ds
Even in saturation
n+
p
Gate Source Drain
bulk Si
n+
V
DD
GND
V
DD
GND
L
L
eff
Depletion Region
Width: L
d
Chan Length Mod I-V
= channel length modulation coefficient
not feature size
Empirically fit to I-V characteristics
( )
( )
2
1
2
ds gs t ds
I V V V
|
= +
I
ds
(uA)
V
ds
0 0.3 0.6 0.9 1.2 1.5 1.8
100
200
300
400
V
gs
= 0.6
V
gs
= 0.9
V
gs
= 1.2
V
gs
= 1.5
V
gs
= 1.8
0
CMOS DC Response
DC Response: V
out
vs. V
in
for a gate
Ex: Inverter
When V
in
= 0 -> V
out
= V
DD
When V
in
= V
DD
-> V
out
= 0
In between, V
out
depends on
transistor size and current
By KCL, must settle such that
I
dsn
= |I
dsp
|
We could solve equations
I
dsn
I
dsp
V
out
V
DD
V
in
Transistor Operation
Current depends on region of transistor
behavior
For what V
in
and V
out
are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
gsn
>
V
dsn
<
V
gsn
>
V
dsn
>
I
dsn
I
dsp
V
out
V
DD
V
in
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
V
tn
V
gsn
> V
tn
V
dsn
> V
gsn
V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
gsn
> V
tn
V
dsn
< V
gsn
V
tn
V
gsn
> V
tn
V
dsn
> V
gsn
V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
nMOS Operation
Cutoff Linear Saturated
V
gsn
< V
tn
V
in
< V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
< V
gsn
V
tn
V
out
< V
in
- V
tn
V
gsn
> V
tn
V
in
> V
tn
V
dsn
> V
gsn
V
tn
V
out
> V
in
- V
tn
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
gsp
<
V
dsp
>
V
gsp
<
V
dsp
<
I
dsn
I
dsp
V
out
V
DD
V
in
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
V
tp
V
gsp
< V
tp
V
dsp
< V
gsp
V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
gsp
< V
tp
V
dsp
> V
gsp
V
tp
V
gsp
< V
tp
V
dsp
< V
gsp
V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
V
tp
V
out
> V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
V
tp
< 0
I-V Characteristics
Make pMOS is wider than nMOS such that |
n
= |
p
V
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0
Current vs. V
out
, V
in
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
Load Line Analysis
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in
:
Plot I
dsn
, I
dsp
vs. V
out
V
out
must be where |currents| are equal in
I
dsn
I
dsp
V
out
V
DD
V
in
Load Line Analysis
V
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0
Load Line Analysis
V
in1
V
in1
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.2V
DD
Load Line Analysis
V
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.4V
DD
Load Line Analysis
V
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.6V
DD
Load Line Analysis
V
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= 0.8V
DD
Load Line Analysis
V
in5
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in
= V
DD
Load Line Summary
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
DC Transfer Curve
Transcribe points onto V
in
vs. V
out
plot
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A
B
C
D
E
Operating Regions
Revisit transistor operating regions
C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Noise Margins
How much noise can a gate input see before it
does not recognize the input?
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range