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JMR-SB-99031

Ver 1.10
08. Dec. 1999

English version
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RTL/Logic Synthesis Guide

RTL/Logic Synthesis Guide for high speed design

Preface
This guidelines describes essential rules to design high speed circuits based on conditions that are listed below:

JMR-SB-99031

Target circuit size Target frequency OpenCAD

: < 2MGates : > 100MHz : V5.3b or later


RAM
TOP_LEVEL
LAYOUT_LEVEL

Design hierarchy name


This guidebook uses the following special phrases: TOP_LEVEL : chip level circuit LAYOUT_LEVEL macro : Group for layout SYNTHESIS_LEVEL macro : Group for logic synthesis module : HDL unit for functionality

SYNTHESIS_LEVEL

HDL format

: Verilog/VHDL
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RTL/Logic Synthesis Guide

Target technology

: CB-C9VX, CB-C10, CB10-VX

(Specify technology name if the rule depends on technology)

Preface
Layout methodology
CTS Buffer tree insertion Gate sizing, repeater insertion Buffer tree insertion for hold time violation

JMR-SB-99031

Explanatory notes : (M) Mandatory Rules for high speed designs. (R) Recommend Rules

: avoid
O : good : not recommended

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RTL/Logic Synthesis Guide

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Rule 1 (R)

[ RTL: Coding Technique ]

For VerilogHDL, use constant values describing bit width and base character. For VHDL, define bit vector ranges using integer.

Reason
For VerilogHDL language specification, default bit width of constant is 32. Useless circuit will be created, because output bit width of operator is adjusted to maximum bit width of expression. VHDL is similar to VerilogHDL.

Example Note

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Rule 2 (R)

[ RTL: Coding Technique ]

Reason
Avoiding redundant logic speeds up the design and minimizes it area. s

Example
Description that priority circuit is generated.

if else if else if else if else if

( X[4] == 0 ) out1 = 4 d0; ( X[3] == 0 ) out1 = 4 d1; ( X[2] == 0 ) out1 = 4 d2; ( X[1] == 0 ) out1 = 4 d3; ( X[0] == 0 ) out1 = 4 d4;

case (1 ) d0 X[4] : out1 = 4 d0; X[3] : out1 = 4 d1; X[2] : out1 = 4 d2; X[1] : out1 = 4 d3; X[0] : out1 = 4 d4; default: out = 4 bxxxx;

Note
For VerilogHDL, using parallel_case directive for non parallel logic may cause simulation mismatch between pre- and post-synthesis.
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Describe RTL carefully when priority encoder is generated with if statements. If there are more than 3 if-branches, use case statements with no overlapping conditions. For VerilogHDL, use parallel_case directive to avoid priority encoder.

JMR-SB-99031

Rule 3 (R)

[ RTL: Coding Technique ]

Reason
To generate high speed and small circuit.

Example
case(sel[9:0]) 10 b0000000000 : 10 b0000100000 : 10 b0000100001 : 10 b0000110000 : 10 b0000100011 : 10 b0000111111 : default : endcase

.. .. .. .. .. ..

case(sel[5:0]) 6 b000000 : if (sel[9:6]!=4 b0000) .. 6 b100000 : if (sel[9:6]!=4 b0000) .. .. default endcase

if (sel[9:6]!=4 b0000) case(sel[5:0]) 6 b000000 : .. 6 b100000 : .. .. default : endcase else endif

Note
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RTL/Logic Synthesis Guide

Don describe large table of case statement but extract t common conditions and divide table using if statement.

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Rule 4 (M)

[ RTL: Coding Technique ]

Reason
To avoid intent-less latch.

Example
if (sel=1 b0) .. else .. endif case (sel[3:0]) 4 b0000 : .. 4 b1000 : .. .. default : .. endcase

Note
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RTL/Logic Synthesis Guide

When you use if or case statements in RTL, always use else and default branches.

JMR-SB-99031

Rule 5 (R)

[ RTL: Coding Technique ]

Separate signals that have no relation to other signals into another always statement (for VerilogHDL) or process statement (for VHDL).

Reason
Describing large process/always blocks or putting together relation-less signal assignments, causes difficulties for delay optimization.

Example Note
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Rule 6 (R)

[ RTL: Coding Technique ]

Reason
To avoid WIRED-AND logic.

Example
O

always @ (a or b or c or d or e) begin if (c) x = a; else if (d) x = e; else x = b; end

always @ (a or b or c) begin if (c) x <= a; else x = b; end always @ (d or e) begin if (d) x <= e; end

Note
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Avoid assignments to one signal in different always or process statements.

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Rule 7 (R)

[ RTL: circuit structure ]

Avoid any latches.

Reason
Timing analysis becomes difficult. Generally reduces design testability.

Example Note

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Rule 8 (M)

[ RTL: circuit structure ]

Don use internal 3-state buffers. Instead use selector-type Bus. t

Reason
Buffer insertion for timing optimization is impossible in internal bi-directional signal paths.

Example
(avoid RTL description to generate a 3-state signal)

always @( EN or IN1) begin if (EN ) OUT1 = IN1; else OUT1 = 1 bZ; end

Note
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Rule 9 (M) Reason

[ RTL: circuit structure ]

Use selector type bus on bus structures. To speed up the bus.

Example
Bad example CPU MEMC RAM
Arbiter Selector

Good example

MEMC

RAM

Arbiter I/O -I/F CONV1 . . . CONVN CPU I/O -I/F CONV1 . . . CONVN

Note
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Rule 10 (M)

[ RTL : circuit structure ]

Reason
To avoid wire congestion.

Example
external RAM RAM I/F
request

sel_1 Arbiter selector sel_3


accept

sel_2

Note
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RTL/Logic Synthesis Guide

If net count of the bus selector macro is more than (1000 x L), divide large selector into several small multi-level sub-selectors. ( L is half of outline length of selector macro)

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Rule 11 (R) [ RTL: circuit structure ]


Describe RTL code considering delay and area trade-off and resource sharing in synthesis.

Example
A B C D sel + X +
if (sel = 1 b1) X= A + B; else X= C + D;

A C sel B D

Y + Z

X
if (sel = 1 b1) Y= A; else Y = C; if (sel = 1 b1) Z = B; else Z = D; X = Y + Z;

priority on delay (when signal sel arrives late)

priority on area (when selector is smaller than adder)

Note
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Rule 12 (R)

[ RTL: Datapath ]

Reason
Improve performance by reducing or balancing logic levels.

Example
A B A

+ +
C X

+
B C D

Y Z

+
Y = A + B; Z = C + D; X = Y + Z;

+
D

X = A + B + C + D;

Note
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RTL/Logic Synthesis Guide

For expressions that have more than two operands, and that might be in the critical path, change expression by specifying operating order or separating expression or dividing to another clock stage (insert register).

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Rule 13 (R)

[ RTL : Datapath ]

Separate blocks like multipliers into one module from another circuit.
SYNTHESIS_LEVEL module module multiplier

Reason
Easy to operate (grouping in layout, specifying dump points in simulation, etc.).

Note

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RTL/Logic Synthesis Guide

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In case of datapath design, execute pre-synthesis for each operator in both delay mode and area mode, and get delay and area of each mode synthesis. Using this results, examine the architecture of datapath.

Reason Example Note

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RTL/Logic Synthesis Guide

Rule 14 (R)

[RTL : Datapath]

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Rule 15 (M)

[ RTL: Partitioning ]

Please make sure that the size of the LAYOUT_LEVEL macro is appr. 500K grids.

Example
TOP top level

I/F

I/F

MA1 <500K

MA2

MA3

MA4 <500K

...

MAX <500K

1st level

MO11

MO1N

SYNTHESIS_LEVEL LAYOUT_LEVEL

2nd level

Note
It is possible to merge several small size SYNTHESIS_LEVEL macros into one LAYOUT_LEVEL macro which size is appr. 500K grid.
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RTL/Logic Synthesis Guide

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Rule 16 (M)

[ RTL: Partitioning ]

LAYOUT_LEVEL macros have to have an identical SYNTHESIS_LEVEL.

Reason
If not, it is difficult to identify cause of timing error. Generated LAYOUT_LEVEL SDF has to match with logical netlist of SYNTHESIS_LEVEL.

Reason Note
Make sure SYNTHESIS_LEVEL macro and LAYOUT_LEVEL macro are identical.
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RTL/Logic Synthesis Guide

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Rule 17 (M) Reason

[ RTL: Partitioning ]

Don place any logic in top level except FCTS buffer and hard macros. t To enable first timing convergence between SYNTHESIS_LEVEL (LAYOUT_LEVEL) macros.

Example
SYNTHESIS _LEVEL SYNTHESIS _LEVEL

top
SYNTHESIS _LEVEL SYNTHESIS _LEVEL SYNTHESIS _LEVEL

top

SYNTHESIS _LEVEL

NG

OK

Note
When module instantiation, don use inverted signal directly in port connection part. t Otherwise, some logic synthesis tool creates glue logic outside of module. Signal inversion description must be included in lower module.
NG: .RB( ~RESET ) OK: .RB( RESET ) assign RESET_BAR = ~RESET
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RTL/Logic Synthesis Guide

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Rule 18 (R)

[ RTL: Partitioning ]

Separate timing-critical circuit and non-timing-critical circuit into different modules.

Reason
There are different synthesis strategies for timing critical an non-timing critical circuits. To easily distinguish between synthesis strategies follow this rule.

Example Note

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RTL/Logic Synthesis Guide

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Rule 19 (R) [ RTL: Partitioning ]


Register all input/output signals of LAYOUT_LEVEL macro.

Reason
To fix timing violation between LAYOUT_LEVEL macros in layout easily.

Example
LAYOUT_LEVEL SYNTHESIS_LEVEL SYNTHESIS_LEVEL LAYOUT_LEVEL = SYNTHESIS_LEVEL

Note
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RTL/Logic Synthesis Guide

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Rule 20 (M)

[ RTL: Partitioning ]

Reason
It is easier to optimize pure synchronous circuits. Additionally, timing model extraction (needed for hierarchical design flow) gets easier.

Example
module module (asynchronous circuit) module

CLK1 CLK2

Note
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RTL/Logic Synthesis Guide

Connected flip-flops driven by different clock sources have to be separated into one module

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Rule 21 (R)

[ RTL: Partitioning ]

(1) Related combinational circuits have to be combined into the same logical and physical module. (2) FSM and datapath circuit have to be separated into different modules or blocks.

Reason
(1) To keep related logic also physically together (especially relevant for Hierarchical Design Flow). (2) To distinguish synthesis strategy easily.

Example Note

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RTL/Logic Synthesis Guide

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Rule 22 (R)

[ RTL: Partitioning ]

Reason
To synthesize IO part and functional block using separate constraints and to consider floorplaning. Elements of IO part can be placed nearly together.

Example
IO buffer

external bus Grouping Chip

Note
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RTL/Logic Synthesis Guide

Group all timing critical IO parts (e.g.: JTAG muxer and register) into one separate module for each port.

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Rule 23 (M)

[ RTL/Synthesis: Partitioning ]

Reason
It is easier to fix timing violation around hard macros.

Example
Top
SYNTHESIS _LEVEL

Top or

SYNTHESIS_LEVEL

RAM Chip TOP level constraints

RAM Chip

Note
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RTL/Logic Synthesis Guide

Separate hard macros (including RAM/ROM) into another module. Use top level timing constraints between hard macro and the circuit connected to hard macro in logic synthesis.

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Rule 24 (M)

[ RTL: Clock ]

Avoid inverters in the clock line in general.

Reason
It is difficult to adjust skew between both edge in CTS.

Example

LOGIC LOGIC

clk

Note
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Rule 25 (R)

[ RTL: Clock ]

Reason
CTS becomes difficult. Timing specification are also difficult.

Example
It is difficult to adjust clock phase between before and after clock generator in layout. f
clock generator

1/2f
CTS cell

f 1/2f clock phase adjustment

Note

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RTL/Logic Synthesis Guide

(1) Avoid gated clocks. (2) Minimize the number of internally gated and derived clocks. Insert a CTS cell after each internally gated or derived clock.

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Rule 26 (R)

[ RTL: Clock ]

Reason
Timing analysis and CTS become difficult.

Example

LOGIC

preset
LOGIC

data clock clear

Note

LOGIC

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RTL/Logic Synthesis Guide

Clock signal are only connect to clock pin of flip flops, not to connect data/preset/clear pin.

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Rule 27 (M)

[ RTL: Clock ]

Reason
To cope with metastable.

Example

fA
LOGIC

fB
synchronization circuits

fA fB
synchronization circuit

fA

fB

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RTL/Logic Synthesis Guide

In synchronization circuit, connect flip flop directly 2 or more levels (not insert logic) after read data.

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Rule 28 (R)

[ RTL: Clock ]
RAM

TOP_LEVEL LAYOUT_LEVEL

Place CTS cell on top level, not not SYNTHESIS_LEVEL macro or module. In case of using clock generator or gated clock, insert a CTS cell at the output of the clock generator.

clock generator

CTS cell module

CTS cell

Reason
The number of CTS cells will be reduced

Note
In some cases it is better to insert a separate CTS cell in the clock line of SDRAM, PCI and CPU.

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Rule 29 (M)

[ Synthesis: Clock ]

Make sure that the constrained period of derived clocks is a power of two.

Reason
Using actual period causes a little error between clock edges, optimization runs to fix timing violation under tight constraint.

Example
Example of 27 MHz and 54 MHz clock : 27 MHz: 54 MHz: use 18 ns * 2 as clock period: (actually, 37 ns) use 18 ns as clock period: (actually, 18 ns)

Note
Assume to adjust clock edges in CTS. When considering margin to clock period, a period including margin are used for base period.
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Rule 30 (M)

[ Synthesis: Clock ]

Considering CTS, set the following constraints to clock. dont_touch_network set_drive 0 set_max_capacitance 9999

Reason
Prevent buffer insertion in clock networks.

Example Note

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Rule 31 (M)

[ Synthesis: Clock ]

CBC10

Add the following timing margin to clock constraint, Logic levels: ~10 1.0 ns ~30 1.5 ns ~40 2.0 ns Skew: MAX condition 0.1ns + PLL jitter MIN condition 0.1ns Need to adjust skew of multiple PLLs. Check PLL jitter individually.

Reason
To correct an error against statistical WLM.

Note
Use report_qor command of Design Compiler to get logic levels.

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Rule 32 (M)

[ RTL: set/reset ]

Reason
To avoid hazards.

Example
CTS cell

(1)

global reset
LOGIC

global reset

LOGIC

LOGIC

LOGIC

(2)
LOGIC

CTS cell

local reset

local reset

LOGIC

LOGIC

LOGIC

Note
Place CTS cell at root of the reset network for inserting buffer tree in layout.
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RTL/Logic Synthesis Guide

Don place combinational circuit between reset signal and t the circuit (flip flops) to be reseted. (1) global reset signal (2) internally generated reset signal

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Rule 33 (R)

[ Synthesis: set/reset ]

Reason
Buffer tree insertion is executed in layout, not in logic synthesis, on reset network.

Example

LOGIC

infinite-drivability cell

Layout

LOGIC

Note
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RTL/Logic Synthesis Guide

Set false_path and set_drive 0 (assume infinite-drivability cell is connected to the input of the module reset port) on reset signals. Use set_dont_touch_network on global reset net within the macro.

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Rule 34 (R)

[ Synthesis: DW ]

Reason
Create high speed operator which is on critical path, consciously.

Example
command : set_implementation BLC adder directive : /* synopys dc_script_begin set_implementation BLC adder */ NEC_SM01_ADD #(32) adder (A, B, CIN, Y, COUT) ;

Note
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RTL/Logic Synthesis Guide

Use DesignWare for operators. To design high speed operators, (1) Set dont_use attribute on slow implementations like rpl/CLA/CSA, and fast implementations like CLF will be used (2) Specify implementation by command or directive.

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Rule 35 (R)

[ RTL: Fanout ]

(1) Connect one output port and one input port between LAYOUT_LEVEL macros. (2) Each output cell on macro level should drive just ONE top level net.

Reason
(1) To reduce delay dependency for top level wires. (2) To reduce delay dependency on macro level in respect to top level wires.

Example

Note

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RTL/Logic Synthesis Guide

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Rule 36 (M)

[ Synthesis: Fanout ]

Reason
(1) To reduce pinpair of the net between LAYOUT_LEVEL macro. For easier control of inter-LAYOUT_LEVEL net delay. (2) To drive each intra-LAYOUT_LEVEL macro net independently from inter-LAYOUT_LEVEL macro nets.

Example
(1)

(2)

:Function block
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RTL/Logic Synthesis Guide

Set fanout constraint for LAYOUT_LEVEL macro ports. (1) Limitation of Fanout number of input: set_max_fanout 1 all_inputs() (2) To insert buffer after last DFF of macro(after diverging point and immediately before output port): set_load 1pF

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Rule 37 (M)

[ RTL: Floorplan ]

CBC10

Reason
Set boundary constraint regarding result of floorplan. For synthesis on LAYOUT_LEVEL macros take huge top level wire delay into account.

Example
set_output_delay set_load set_input_delay

Center of LAYOUT_LEVEL macro

chip

Note
Design Planing is the best way to calculate top level wire delay for complex high speed designs. Regarding this issue, get in contact with NEC !
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RTL/Logic Synthesis Guide

Estimate wire length of the net between LAYOUT_LEVEL macros using model of net connecting center of each macro before layout. Calculate wiring delay using wire length and parameter of 0.25ns/mm, and set this value as constraint of boundary in logic synthesis. The reference of the macro size is 2 mm for 350K grids.

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Rule 38 (R)

[ Synthesis: Fix Hold ]

For initial synthesis, all clocks should have an ideal clock latency and uncertainty level specified. There is no need to fix hold violations based on the specified uncertainty value !

Reason
As latency and uncertainty are just estimates there is no need to fix this during pre-layout synthesis.

Example Note
After layout when real latency and skew values of the clocks are known, hold violations can be fixed via IPO or LBO (Synopsys). Another possibility is fixing these violations during Timing Driven Layout.

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Rule 39 (M)

[ Synthesis: WLM ]

Reason
(1) To adjust delay calculation to NEC s inhouse delay calculator. (2) To calculate wire delay between LAYOUT_LEVEL macros. (3) To calculate wire delay within LAYOUT_LEVEL, considering LAYOUT_LEVEL macro area.
LAYOUT_LEVEL Mxxxx

TOP LAYOUT_LEVEL

SYNTHESIS LEVEL

Txxxx

Note
For usage of customized WLMs please get in contact with NEC.
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RTL/Logic Synthesis Guide

Set following wire load model auto_wire_load_selection=false // (1) update_lib <library_name> -over_write WIRE_<master_name>.lib // (2) top set_wire_load T**** -mode top set_wire_load M**** -mode enclosed // (3) LAYOUT_LEVEL Use custom WLM for timing critical LAYOUT_LEVEL macro.

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Rule 40 (R) [ Synthesis: Constraint ]

CBC10 (OPC5.3b ~)

Use script to reduce variety of primitive cells (mainly use high drive cells for initial synthesis).

Reason
To adjust to layout method (drivability optimization, hold BUFFER insertion). For synthesis of complex high speed designs,where the average wire length is high, it is not recommended to use low drive cells for initial synthesis.

Example Note
Script is provided by NEC.

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Rule 41 (M)

[ Synthesis: Constraint ]

(1) Describe all timing exeptions. (2) For non timing critical SYNTHESIS_LEVEL macro, use set_max_area 0 command in logic synthesis.

Reason
(1) Not to optimize false path. (2) To reduce circuit area.

Example
set_false_path set_multicycle_path

Note
In TDL flow not all timing exeptions are allowed ! Please refer to TDL Application Note.
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Rule 42 (R)

[ Synthesis: Constraint ]

Set path group when clock or constraint of a module are complex. (1) Give weight to path groups. (2) Set critical range. (Maximum : about 10% of clock cycle)

Reason
To focus on specific critical path.

Example
(1) group_path -name group3 -from xxx -to yyy -weight 2.5 (2) set_critical_range 2.0 current_design

Note
slews down runtime.

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Rule 43 (R)

[ Synthesis: Constraint ]

Reason
(1) To set constraints same as the result of layout drivability optimization. (2) To assume difference between wire capacitance and top level WLM in synthesis for easy layout.

Example
(1) set_driving_cell -cell F158K -pin N01 all_inputs () (2) SYNTHESIS_LEVEL
load=0.1 load=1
LAYOUT_LEVEL

Note
Assume hierarchical design.
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Compiling SYNTHESIS_LEVEL macro separately (1) Set set_driving_cell on SYNTHSIS_LEVEL macro port. (2) Set set_load 0.1 on port that connecting net is enclosed in one LAYOUT_LEVEL macro. Set set_load 1 on port that connecting net goes to another LAYOUT_LEVEL macro.

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Rule 44 (R)

[ Synthesis: Optimization ]

It is recommended that average of pin pair is smaller than 2.5.

Reason
To improve routability.

Example Note
To get average of pin pair, use report_net command of DesignCompiler.

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Synthesis to reduce pin pair : set parameter of wiring area a little larger than 0 (already done in NEC statistical WLMs). if not timing critical, try compile_new_boolean_structure = true set_structure true -boolean_effort medium

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Rule 45-1 (R)

[ Synthesis: Optimization ]

Reason
(1) To spread optimization space. (2) To improve throughput of the deep logic level circuit.

Example
(2) set_balance_registers true

Note
(2) Use retiming carefully because it cause to mismatch of verification point in formal verification !

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If timing violation remains, try following option (1) ~ (4). (1) Try ungroup command except operators. (2) Try retiming to balance between paths before and behind the register.

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Rule 45-2 (R)

[ Synthesis :Optimize ]

Reason
(3) Area become small, but speed decreases, because of increasing logic levels. (4) Speed becomes fast but area becomes large because of transforming to AND-OR 2 level circuit by this command. It is available for random logic circuit.

Note
Use flatten and structure at the same time. Don use boolean optimization option -boolean true, when execute structuring t for delay critical circuit.
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(3) For non-timing critical module, use set_structure true -boolean true command to structure logic. (Default : set_structure true) (4) Use set_flatten command to flatten logic. Size of the module to be flattened must be less than 2K gate. Don use flatten on datapath and operator, but effective on encoder and decoder. t

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Rule 46 (R)

[ Synthesis: Optimization ]

Synthesize in following steps: (1) In logic synthesis, set path group into two types: circuit between internal registers circuit between register and input/output port. (2) Re-synthesis, after ungroup,or propagate constant value of module boundary and delete floating output. (3) Optimize critical path. (compile -incremental_mapping -map_effort high)

Reason
(1) Is a step to optimize between internal FFs for the case of severe module boundary constraint of the circuit. (2,3) are steps for more timing optimization.

Example Note
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Rule 47 (R)

[ Synthesis: Optimization ]

Uniquify module referred to multiple times before incremental optimization.

Reason
To synthesize based on individual constraints of each module.

Example

Note
To reduce first synthesis runtime execute uniquify just before incremental optimization.
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Rule 48 (R)

[ Synthesis: Optimization ]

Optimization of control circuit (FSM) : For timing critical FSM circuit, try state code assignment in two way, auto and one-hot, and after optimization, adopt the better code assignment for the FSM circuit.

Reason
To generate high speed circuit.

Example
set_fsm_encoding_style one_hot

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Rule 49 (R)

[ Synthesis: Optimization ]

Reason
To reduce area of module boundary.

Example
boundary optimization

module boundary

module boundary

Note
Use boundary optimization carefully, because it changes the original module port meaning.
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NEC Corporation 1999

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RTL/Logic Synthesis Guide

Boundary Optimization: By optimizing module boundary, constant value, unconnected port, complement are propagated. (Example) compile -boundary_optimization set_boundary_optimization

JMR-SB-99031

Revision History

NEC CONFIDENTIAL

NEC Corporation 1999

54

RTL/Logic Synthesis Guide

Version V1.00 V1.10

Modified contents Initial release 1st general modifications

Date 30.09.99 08.12.99

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