A critical word on higher order hold devices

Robert Cloudt Consider the continuous-time design method for digital controller design. When this method is employed, a continuous-time controller is designed for the continuous-time plant using familiar continuous-time techniques such as frequency domain controller design techniques. The continuous time control action described a differential equation is approximated by a difference equation by using an integration formula, e.g. backward Euler or trapezoid integration formula (Tustin transform). The step size or sampling time is chosen using a rule of the thumb: the sampling rate (in Hz) should be higher than 20 times the closed loop bandwidth in Hz. This controller design method may fail in designing high performance controllers (controllers which achieve a high closed-loop bandwidth) with a relatively low sampling frequency. The phase loss of the zero order hold (ZOH) device is blamed. In the regular continuous-time control systems a phase loss is indeed destabilising and limits the achievable closed-loop bandwidth. The first order hold (FOH) is frequently mentioned as an alternative. The first order hold applies first order signal extrapolation as opposed to zeroth order extrapolation in the zero order hold device. This results in less phase loss at low frequencies. It is believed that this reduction of phase loss allows a reduction of the sampling frequency. However, the implementation of the first order hold device (or higher order hold devices) requires some serious hardware changes. The need for interpolation hardware emerges. The restriction of piecewise constant signals is a natural choice in the majority of digital control systems. The question arises whether it is possible to use a hold device which generates a piecewise constant output signal and which suffers from less phase loss. The key idea behind reducing the phase loss of a hold device seems predicting future control samples. If it is possible to perfectly predict the next control sample, the hold device can output the average of the current control sample and the predicted next control sample. This kind of hold device has an acausal symmetric impulse response, which results in zero phase loss. Inspired by this observation, a hold device is designed which outputs the average of the current control sample and the predicted next control sample: y?k A! 1 u?k A 1 u ?k  1A. 2 2 The prediction of the next control sample is obtained from first order signal extrapolation: u ?k  1A! u ?k A u ?k A u?k  1A! 2u?k A u?k  1A. The impulse response describing this hold circuit becomes:
3 for 0 t e h 2 ht !  1 for h t e 2h . 2 elsewhere 0

(1)

(2)

(3)

where h is the sampling time. This piecewise constant hold circuit was already mentioned in 1971. In [1] this hold device is called the one half order hold (HOH). Figure 1 shows a comparison of the reconstruction of a sine wave through the zero order hold device and the half order hold device. It is clear that the fundamental component of the HOH reconstruction suffers less phase loss than the ZOH reconstruction. The frequency responses of several hold devices are compared in figure 3 and 4. The HOH has less phase loss for low frequencies than the ZOH and FOH and the HOH shows less magnitude distortion than the FOH. So, based on these observations one could conclude that the HOH is preferred over the FOH. Furthermore, the implementation of the half order hold device requires no extra interpolation hardware.

1.5 original H O H reconstruction ZO H reconstruction

0.5

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-1

-1.5 20

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Figure 1. Signal reconstruction

References 2 and 3 treat piecewise constant hold devices which achieve even less phase loss. They employ higher order signal extrapolation. The higher order piecewise constant hold devices suffer from magnitude distortion but the magnitude distortion can be traded of against an increase of phase loss ([1], [3]). None of these piecewise constant hold devices requires interpolation hardware. They can be implemented through small changes in the controller software. So, the need for hold devices with less phase loss does not necessarily have to lead to higher order hold devices that require interpolation hardware! One might have noticed that the piecewise constant hold devices are in fact a series connection of a digital filter and a zero order hold. The difference equation of the digital filter can be embedded in the difference equation describing the control action. This yields a combination of a different controller with a zero order hold device, which is equivalent to the original controller with the piecewise constant hold device. For example, a certain controller combined with a half order hold can be transformed to an equivalent situation with a zero order hold device and a different controller which has one extra state compared to the original controller. The distinction between controller action and hold action is not clear for these piecewise constant hold devices. The preferred viewpoint is dependent on the situation: if the continuous-time controller design method is applied, the concept of piecewise constant hold devices may be more natural, whereas in discretetime controller design the situation with an ordinary zero order hold device is preferred. This last situation allows more freedom in controller design. The digital filter part in the piecewise constant hold devices is based on signal extrapolation. Design in the z-domain allows the adaptation of this digital filter part (embedded in the controller equations) to the specific application. Besides more design freedom, design in the z-domain has more advantages. In the z-domain, one is able to decide whether a digital control loop is stable. The continuous-time controller design method is easy to use, because it is based on familiar continuous-time techniques, but it is only approximate. The accuracy of the approximation of differential equations by difference equation is questionable if the sampling time increases. Moreover, an open loop gain larger than one at a phase angle of -180r is not a sufficient condition for instability of the sampled-data system! The continuous-time design method for digital controllers conceals the delicacy of sampled-data control systems. If one sticks to continuous-time controller design, one might get better results when the phase loss or delay of the hold device is incorporated in the plant model, for which a controller is being designed. In this way, one can anticipate on the phase loss. The piecewise constant hold devices in [1], [2] and [3] are a series connection of finite impulse response (FIR) filter with a zero order hold. These FIR filters have no counterpart in continuous-time. This fact again expresses the extended design freedom in the z-domain. The question arises if there are any arguments in favour of higher order hold devices, which apply higher order extrapolation/interpolation. Well, those higher order hold devices have the potential of

generating smooth signals. Smoother actuator signals mean less actuator wear, and smoother signals induce less high frequency components that excite the (possibly unmodelled) high frequency dynamics of the plant, resulting in an overall more robust control system. However, the smoothness of the generated signals is highly dependent on the prediction and extrapolation capabilities of the hold device. One way of predicting the future is signal extrapolation. But this approach does not necessarily result in smooth signals (compare the magnitude responses of the ZOH and FOH in figure 3). Another way of predicting the future, is to incorporate model information into the prediction. This leads to (closed-loop) observer/predictor structures like in the figure below.
Hold device u?k  1A K
u?k A x?k A

Plant

x?k  1A Predictor

Observer

Figure 2. Observer/predictor structure

The introduction of exogenous inputs poses a problem in the proposed structure, because they are generally unpredictable, unless extra information is available. The reference signal, for example, can be applied in advance (preview control), provided that the reference profile is fixed and known in advance. If information on the nature of disturbances is available (e.g. sine waves, steps, white noise), then an elegant solution may exist to predict the effect of the disturbances, but if no disturbance model is available, the quality of the predicted next control sample degrades. The proposed control structure needs further investigation, for example into stability, robustness and disturbance rejection properties. If the frequency content of the actuator signal is of importance, then the analysis has to be carried out in a sampled-data framework. The sampled-data approach takes the mixed continuous-time/discrete-time dynamics into account. This is the only approach which allows a fair judgement of the frequency content of the actuator signal. The continuous-time analysis is not suited because of its approximate nature. Discrete-time analysis in the z-domain does not account for intersample information, so it is not suited to study the high frequency content of the actuator signal. Such a sampled-data analysis is carried out in [4]. The conference paper considers the predictive first order hold (PFOH) device. It has an acausal impulse response as it requires the next control sample to be known, one sampling time in advance. The current and next control sample are connected through linear interpolation. The acausality seems to prevent the implementation of this hold device, but it is physically realisable if the controller is strictly proper (at least, if the computation delay is neglected). In the paper, an initial state disturbance of an integrator plant is studied in an LQR setting. The cost function contains a term containing the integrator output signal and a term which contains the frequency weighted actuator signal. The minimal cost function for optimal biproper ZOH controllers and optimal strictly proper PFOH controllers are compared. It turns out that the optimal strictly proper controllers with a PFOH device are in favour, if the penalty on high frequency actuator signals is high enough. If the high frequency components in the actuator signal are really of concern, then there is a solution which does not require higher order hold devices. The solution consists of placing an analog lowpass post-filter in front of the actuator. This implementation seems to be cheaper than the introduction of interpolation hardware. The analog filter will introduce some phase lag, but placing a digital filter in front of the zero order hold introduces a lot of design freedom, and can probably cancel some phase loss (of course, the filter equations can be absorbed into a digital controller). One point in which a higher order hold circuit can excel, is the generation of feedforward signals. Suppose, a discrete feedback controller is designed to supply a certain level of stability, robustness and disturbance rejection. A suited sampling frequency is chosen in order to satisfy these control

aims. A feedforward is added to improve the tracking performance with respect to tracking a prespecified setpoint profile. The ideal feedforward signal is taken as the signal that results form applying the setpoint profile to the inverse plant. The bandwidth of this ideal feedforward signal might be high relative to sampling frequency. If this is the case, then the zero order hold reconstruction will be a coarse approximation of the ideal feedforward signal. In such a situation, higher order holds offer a more accurate signal approximation. There are however solutions which offer richer feedforward signals which may be more natural in the context of embedded systems. For example, the feedforward signal can be generated at a higher rate than the sampling frequency of the feedback controller (multirate control). Or, one can switch to a kind of asynchronous, event driven controller implementation, which determines the sampling instants based on the tracking error. Conclusion The call for higher order hold devices is put into perspective. Higher order hold devices have indeed some desirable properties (less phase loss, potentially smooth signals, richer signals), but they require extra interpolation hardware. Alternatives were presented which do not require expensive hardware additions. The search for alternative hold devices was motivated by the phase loss of a zero order hold circuit, as this phase loss is often identified as the major limitation in obtaining a high bandwidth or low sampling frequency. In the context of continuous-time design methods for digital controllers, it turns out that in a certain sense the zero order hold is indeed a limitation, but the piecewise constant signal offers no major limitation. Piecewise constant hold devices can reduce the phase loss of the hold operator, when compared to a zero order hold. The continuous-time design method for digital controllers conceals the delicacy of sampled-data control systems. In the context of discrete-time controller design, the zero order hold offers no major limitation. Moreover, the discrete-time controller design method offers more design freedom and it allows to study the stability of the digital control loop. Whether it is worthwhile to implement a higher order hold device, might be application dependent and it has to be analysed thoroughly in the sampled-data framework. Sampled-data analysis takes the mixed continuous-time/discrete-time dynamics into account and it offers a fair way of comparing zero order hold and higher order hold operators.

References 1. Pitkin, E.T. AN IMPROVED SAMPLE-AND-HOLD UNIT. IEEE Transactions on Automatic Control, Vol. 16 (1971), No. 5, p. 516-518. 2. Yekutiel, O. A REDUCED-DELAY SAMPLED-DATA HOLD. IEEE Transactions on Automatic Control, Vol. 25 (1980), No. 4, p. 847-850. Beliczynski, B. and W. Kozinski. A REDUCED-DELAY SAMPLED-DATA HOLD. IEEE Transactions on Automatic Control, Vol. 29 (1984), No. 2, p. 179-181. Berhardsson, B. THE PREDICTIVE FIRST ORDER HOLD CIRCUIT. Proc. of the 29th Conference on Decision & Control, Honolulu, Hawaii USA, 5-7 December 1990. Piscataway, NY USA: IEEE, 1990, Vol 3, p.1890-1891.

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Table 1. Hold transfers

Zero order hold (ZOH) First order hold (FOH)

1  e  sh s 1  hs 1  e  sh h s
2

Half order hold (HOH) Predictive first order hold (PFOH)

3  4e  sh  e 2 sh 2s e sh  2  e  sh hs 2

1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0

ZO H FO H HOH P FO H

M agnitude

0.5

1.5 2 2.5 N orm alised frequency

3.5

Figure 3. Magnitude response

0 -20 -40 le ( e ees) hase a -60 -80 -100 -120 -140 -160 -180 0 H H H H

0.1

Figure 4. Phase response

    

H 0.2 0.3 0.4 alise f e e c y 0.5 0.6 0.7