7.

Complementary MOS (CMOS) Logic Design

Institute of Microelectronic Systems

Basic CMOS Logic Gate Structure

VDD

PMOS and NMOS switching networks are complementary Either the PMOS or the NMOS network is on while the other is off No static power dissipation
Logic Inputs

PMOS Switching Network

NMOS Switching Network

7: CMOS Logic

Institute of Microelectronic Systems

CMOS NOR Gate

VDD = 5 V 10 1 v
I

VDD = 5 V MP 5 1 vo MN 2 1 Z

10 1

NOR Gate Truth Table AB 0 0 1 1 0 1 0 1 Z=A+B

2 1

2 1

1 0 0 0

7: CMOS Logic

Institute of Microelectronic Systems

Transistor Sizing for CMOS Gates: Review

Goal: To maintain the delay times equal the reference inverter design under the worst-case input conditions Example: 2 input CMOS NOR gate - Each transistor of the NMOS network is capable of discharging individually the load capacitance C Same size as NMOS transistor of reference inverter - PMOS network conducts only when AB = 00 (Transistors in serie) Each PMOS must be twice larger ( On-resistance proportional to (W/L)-1 )

7: CMOS Logic

Institute of Microelectronic Systems

CMOS NAND Gate

NAND Gate Truth Table
V =5V
DD

5 1

5 1 Z V =5V
DD

AB 0 0 1 1
v
O

Z = AB 1 1 1 0

4 1 A

M v
I

5 1

0 1 0 1

4 1 B

2 1

7: CMOS Logic

Institute of Microelectronic Systems

Multi-Input NAND Gate

V
DD

=5V

5 1

5 1

5 1

5 1

Y= ABCDE
5 1 Y

Y 10 1 A C

10 1 B 10 1 C

Why should one prefer a NAND gate rather than a NOR gate?

10 1

10 1

7: CMOS Logic

Institute of Microelectronic Systems

Steps in Constructing Graphs for NMOS and PMOS Networks (I)

+5 V A B C D PMOS Switch Network Y B MB

B (C + D)
A MA C MC D MD

C+D

A + B (C + D)

Y = A + B (C + D)

7: CMOS Logic

Institute of Microelectronic Systems

Steps in Constructing Graphs for NMOS and PMOS Networks (II) +5 V 3

A B C D PMOS Switch Network Y B MB 1 A MA 2 1 1 2 C MC D 4 1 0 4 1

(d) Graph with PMOS Arcs Added 3

B
4

(a)

1 5

2 4

C
4 1

MD

D
0 (c) NMOS Graph with New Nodes Added 2 3

B
(b) NMOS Graph

B
1

3 2

C D
0

1 5

C
Institute of Microelectronic Systems

D
0
8

7: CMOS Logic

Steps in Constructing Graphs for NMOS and PMOS Networks (III)

Final CMOS Circuit

3
A

+5 V 15 1

Graph with PMOS Arcs Added 3

4 2

B
4

4 B 7.5 1

15 1

5
D 15 1

1 5

D
0
B MB

1
A MA 2 1
Institute of Microelectronic Systems

4 1 MD 4 1

MC D 4 1

7: CMOS Logic

Summary
+5 V 15 1

AND - serially connected FET OR - parallel connected FET NMOS network implements zeros PMOS network implements ones W/L ratio has to be determined as a design parameter
A B

C 7.5 1 D

15 1

15 1

Y B MB 4 1 MD 4 1

MA 2 1

MC D 4 1

7: CMOS Logic

Institute of Microelectronic Systems

10

CMOS Gate Design: Minimum Size Vs. Performance (I)

CMOS circuit with only minimum size transistors Example: Considerable savings in chip area, but increased logic delay

7: CMOS Logic

Institute of Microelectronic Systems

11

CMOS Gate Design: Minimum Size Vs. Performance (II)

(W/L) for PMOS network = 2/3

PLH

PLHI = PLH
For NMOS network

5 1 = PLHI = 7 . 5 PLHI 2 3

of reference inverter

PHL = 2 PHLI
+ 7 .5 PLHI ) 9 .5 PLHI = = 4 .75 PLHI 2 2

The average propagation delay of the minimum size logic gate is:

P =

( PHL + PLH ) = (2 PHLI

2

Mininimum size gate will 4.75 times slower than reference inverter when driving the same load capacitance
7: CMOS Logic Institute of Microelectronic Systems 12

Power-Delay Product (PDP)

The PDP is an important figure of merit for a logic technology

PDP = PAV P
For CMOS:

P AV = CV

2 DD

with

f =

1 T

CMOS switching waveform

7: CMOS Logic Institute of Microelectronic Systems 13

Power-Delay Product (contd)

The period T must satisfy:

T tr + ta + t f + tb

Assumptions: At high frequencies ta 0 and tb 0, tr and tf account for approximately 80 % of the total transition time For symmetrical inverter:

2 t r 2 (2 P ) = = 5 P 0 .8 0 .8

2 2 CV DD CV DD P = PDP 5 P 5

7: CMOS Logic

Institute of Microelectronic Systems

14