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Clocking
For modern processors, cycle time is around 1620 FO4 delays, of which registers take 2-4 FO4 delays Power consumption dominated by clock load, both distribution network and end loads (latches, prechargers)
70% of total power in IBM POWER4 design
Simple single-edge triggered registers are fine for most ASIC designs. This lecture well examine what is happening in high performance designs.
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Slow path timing constraint Tcyc TCQmax + TPmax + Tsetup+ Tskew Fast path timing constraint TCQmin + TPmin Thold + Tskew
Fast path constraint cannot be fixed by slowing clock fatal to chip design Skew reduces cycle time
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Latches driven by two non-overlapping clocks Can guarantee no fast path problems with larger non-overlap
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phase 2 latches can only sample values generated from phase 1 latch outputs, and vice versa.
Time Borrowing
Combinational Logic 1 TNO Tsetup TCQmax TP1max TNO B CLK2 C C.L. D 2
In steady state, Tz Tx, therefore minimum cycle time Tcyc TP1max + TP2max + 2TDQmax Non-overlap time, TNO, can be adjusted such that no hold time violations are possible: TNO + TCQmin - Tskew Thold
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Can place latches where convenient in logic path Maximum time in one combinational logic block is TP1max Tcyc TCQmax Tsetup TNO Tskew
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CLK Q X
precharge
eval.
Two phase non-overlapping system requires distribution of two clocks. Can distribute single clock signal, and invert locally at latch. Clock skew can cause overlap between transparent phases of CLK and inverted CLK, so must check for fast path hold time violations. Very common clocking scheme for full custom chips, works well with pipelined domino logic.
CLK
precharge
CLK
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Pulse Latches
By using narrow clock pulses, can have only a single latch in any combinational loop. Used in Cray-1, and in many high-performance (Pentium-4) and low-power microprocessors (XScale).
Tw B A TCQmin TPmin TPmax Thold Thold Tsetup CLK A B
Combinational Logic
1 Q
CLK
D
B
CLK
A B Q Latch Sample Latch Sample Sample Latch Sample A B A Latch B
Cycle time, Tcyc,min TDQmax + TPmax + Tsetup + Tskew Tw Tw is pulse width, and gives maximum time borrowing for previous cycle Two-sided timing constraint on pulse width
Tsetup < Tw < TCQmin + TPmin - Thold - Tskew
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CLK
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Flip-Flops Timing
GCLK
PCLK
Metastability
Voltage CLK
metastable
Feedback
TCLK
RCLK
Sampling latch
Probability of failure (i.e., not valid 1 or 0) when observed time t after clock edge - t r F(t) = k e Parameters k and r functions of latch design. r is called the time constant of resolution and is primarily controlled by the gain-bandwidth product of the feedback loop (dont use dynamic latches as synchronizers!). Error probability decreases exponentially with t but always some chance of failure.
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If setup and hold times are violated, flip-flops might hang in a metastable state.
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Synchronizers
RCLK
Use pipelined registers to give full RCLK cycle to resolve asynchronous input.
TCLK CLKA
CLKB
Use N interleaved registers, each clocked at 1/N of RCLK rate, to increase resolution interval by factor of N without decreasing signal bandwidth.
RCLK
RCLK CLKA CLKB CLKC
CLKC
Rotating Select
Observation Interval
Repeat Interval
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