Product Reed-Solomon Codes for Implementing NAND Flash Controller

on FPGA chip

Changgeun Kim
Department of Electronic Engineering
Sogang University
Shinsoo-dong, Mapogu, Seoul, 121-742, Korea
hakingdie@sogang.ac.kr

Juhee Kim
Department of Electronic Engineering
Sogang University
Shinsoo-dong, Mapogu, Seoul, 121-742, Korea
mika8614@sogang.ac.kr

Sunwook Rhee
Department of Electronic Engineering
Sogang University
Shinsoo-dong, Mapogu, Seoul, 121-742, Korea
sunuk@sogang.ac.kr

Yong Jee
Department of Electronic Engineering
Sogang University
Shinsoo-dong, Mapogu, Seoul, 121-742, Korea
yongj22@sogang.ac.kr
Abstract In this paper, we propose a (255, 231) product Reed-
Solomon(RS) code for non-volatile NAND flash memory systems.
Reed-Solomon codes are the most diversely used in data storage
systems, but powerful for burst errors only. In order to correct
multiple random errors and burst errors, another efficient
decoding algorithms are required. The product code composing
of column-wise Reed-Solomon codes and row-wise Reed-Solomon
codes may allow to decode multiple errors beyond their error
correction capability. The proposed code consists of two
shortened Reed-Solomon codes and a conventional Reed-
Solomon code. We implement the proposed coding scheme on a
FPGA-based simulator with using an Altera Stratix II FPGA
device. The proposed code can correct 16 symbol errors. For 8-bit
symbol memory system, the code has the coding gain of 1.8 dB
and the bandwidth of 1.07 Gbps when operated at 290 MHz with
the power consumption of 26.4 mW.
Keywords-Reed-Solomon code; Product code; NAND
flash memory; error correction code; FPGA

I. INTRODUCTION
Non-volatile NAND flash memory systems are widely
used in the mobile and wireless systems. The requirement of
high density and low cost makes the operation speed increased
and simultaneously creates various types of errors. Charge
leakages give retention errors. With device scaling, each
NAND flash cells are vulnerable to physical errors by
coupling noises. As the memory density increases, its
durability is weakened. These cause gate oxide degration that
the bonding is easily broken. The multi-leveling cell (MLC),
even though supplying powerful solutions, increases the
performance of memory storage systems and causes many
errors. [1][2] In MLC, multiple bits are stored per a memory
cell by each programming cell with multiple threshold levels.
The errors are often generated with the shift of threshold
voltages during the operation.[3] Therefore, the data reliability
has become an important issue in most communication and
storage systems for high speed operation and mass data
process. Various error correction code are provided for
improving data reliability. A Reed-Solomon code is quite
suitable for burst errors, but in case of random errors, it has
some difficulty. For MLC NAND flash memories, Bose-
Chaudhuri-Hocquenghem (BCH) codes are frequently used.
[2][4][5] BCH codes provide flexible code length and variable
range of error correcting capability. However, NAND flash
memory systems process with the large size of data such as a
page or a block unit. Hence, BCH codes may not be
appropriate for a NAND flash controller. [3]
In this paper, we propose a product code with using a Reed-
Solomon code scheme for NAND flash memories. The
proposed code can correct errors by the burst error as well as
by the multiple random error. The proposed code may have
much lower decoding complexity than that of a BCH code with
the considerable decoder code rate. We employ three (255, 247)
Reed-Solomon decoders to improve error rate against multiple
random errors.
We propose a product code of using RS codes, in section II
and discuss the performance of the proposed code in section III.
We represent the experimental results of FPGA
implementation in section IV. We give the conclusion in
section V.
II. PROPOSED PRODUCT CODES
A Reed-Solomon (RS) code is constructed in a Galois field.
(GF(2
m
)) [6] A RS code is a block code and can be specified
as a cyclic (n, k) RS. The variable n is the size of codeword
by the symbol, k is the number of data symbol and 2t is the
number of parity symbols. Each symbol contains m number
of bits. The relationship between the size of symbol m and
the size of the codeword n is given by n = 2
m
-1. This means
that if there are m bits in one symbol, there could exist 2
m
-1
distinct symbols in one codeword, excluding the one with all
zeros. The RS code allows to correct up to t number of symbol
errors where t is given by t = (n-k) / 2. [7]
2010 Second International Conference on Computer Engineering and Applications
978-0-7695-3982-9/10 $26.00 2010 IEEE
DOI 10.1109/ICCEA.2010.63
281
Figure 1: The block diagram of transferring row-column data

Figure 2: The block diagram of the proposed product encoder

Figure 3: The block diagram of the proposed product decoder
A. Encoder
The encoder consists of a duplicated structure using (255,
247) RS codes that have four error correcting capability. First
part composes two (120, 118) shortened RS codes that encode
input data in column wise. #1 shortened RS encoder processes
112 input data symbols from 1st to 112
th
, and #2 shortened RS
encoder processes from 113
th
to 224
th
. The shortened RS
encoder fills up 135 symbols with 0 symbols. Two shortened
RS codes have a format of 255 byte codeword despite of
containing 120 message symbols.
For this process, the input data transferred in row wise
sequence are rearranged into a column wise vector before
encoding into shortened RS codes as shown in Fig. 1. They
restructure each message data for an encoder and decode in
reverse sequence. For a shortened RS code, the transferred
block rearranges the original data into a column-wise vector.
For a (255, 247) RS code, it rearranges the column-wise data
to the original data structure.
Transmitted data are systematically encoded. The codeword
is represented as c(X) = c
0
+ c
1
X + c
2
X
2
+ + c
n-1
X
n-1
(c
i

GF(2
m
)). Then, a generator polynomial g(X) is represented as
below. g(X) = (X )(X
2
)(X
3
)(X
2t
) = g
0
+ g
1
X +
g
2
X
2
+ + g
2t-1
X
2t-1
+ X
2t
(g
i
GF(2
m
)). Encoding procedure
is implemented dividing X
n-k
m(X) by g(X), which is written
X
n-k
m(X) = q(X)g(X) + p(X) where, q(X) and p(X) are quotient
and remainder polynomials, respectively. Then, the remainder
is the parity polynomial. The resulting codeword polynomial
c(X) can be written as c(X) = p(X) + X
n-k
m(X). Encoding is a
process composed of overall codeword by generating parity
polynomials for input data. Therefore, the encoder is
implemented with dividing X
n-k
m(X) by g(X). [6]
After first encoding, encoded data of containing extra 7
symbols are sent to a (255, 247) conventional RS encoder. The
conventional RS encoder processes received data in different
way compared to the shortened RS encoder. Therefore, before
second encoding, the 247 data symbols must be rearranged
with using the transfer block. This transfer processing is
different from first one. The transfer block code after the
shortened RS encoder rearranges column wise to a row wise
sequential bit block code.
When data transfer is ended, the conventional RS encoding
is started. Because of using one RS coding processor, the
conventional RS encoding process is the same as the shortened
one ahead. With dividing the code in row-wise and in column-
wise direction, the codeword is encoded against burst errors
and multiple random errors. The parity symbols encoded by a
conventional RS code have information about burst errors,
especially. Furthermore, another parity symbols done by two
shortened RS codes have information about multiple random
errors, especially. The processing from preparing data to
sending the codeword to decoder is shown in Fig. 2.
B. Decoder
The decoding is processed in reverse order, a conventional
(255, 247) RS decoding is processed in forward direction. It
searches the data and corrects errors in row wise. At this point,
the data structure is the same as the original, thus the decoder
becomes to correct burst errors.
The decoder first calculates the syndrome equations which
show any potential errors. If the syndrome polynomial is not
zero, the receiving codeword is erroneous. Then, the decoder
corrects errors by calculating the error locator polynomial and
the error evaluator polynomial. The process of decoding is to
calculate error locator polynomials from the syndrome. This
paper uses the Berlekamp-Massey (BM) algorithm to solve
error locations. [7] Let c(X) be the codeword polynomial and
r(X) the received word polynomial. The encoded data are
represented as r(X) = c(X) + e(X), where e(X) represents the
error polynomial with the same degree of c(X) and r(X). If the
root
j
of the polynomial is X =
j
, the equation becomes r(
i
)
= c(
i
) + e(
i
) = e(
i
), because c(
j
) is always zero. Then, if
error values come zero, r(
i
) becomes zero, and if not, not zero.
Thus, the syndrome is defined by S
i
= r(
i
) = e(
i
), (i = 1, 2, ,
2t).[8] RS decoding is the technique that solves 2t unknown
equations with 2t unknown quantities (X
1
, X
2
, ..., X
2t
, and Y
1
,
Y
2
, , Y
2t
).
282
in c
How
beca
can
xX
1
)
recip
of in
coef
are d
field
locat
mod
equa
is de
is th
and
Fina
recei
N
are r
grou
proc
data
Afte
symb
shor
symb
shor
filled
wise
this
corre
247)
corre
RS c
E
anot
iden
symb
shor
by th
as sh
#
#
#
#
#
#
#
#
#
#2
#2
#2
#2
coding
column wise
Figure 4:
wever, these 2t
ause of their n
be defined a
)(1 - xX
2
)(1
procal of roots
ndicating error
fficients of (
determined by
d element. Th
tions are the i
dulo x
2t
+ 1
ations, the dec
efined by Y

e formal deriv
error location
ally, codewor
ived polynom
Next, the corr
rearranged by
ups as in the
cesses the sam
in row-wise
er transferring
bols encoded
rtened RS dec
bols encoded
rtened RS dec
d with 0 sy
e by the same
process, mult
ect 8 symbol
) RS decoder
ect 16 burst sy
code decoder.
Each error do
ther processin
ntically distrib
bol errors in
rtened RS dec
he transfer blo
hown in Fig. 3
#1 byte 1 2
#2 byte 9 10
#3 byte 17 18
#4 byte 25 26
#5 byte 33 34
#6 byte 41 42
#7 byte 49 50
#8 byte 57 58

230 byte 1833 1834

231 byte 1841 1842
#232~
239 byte
p
#240~
247 byte
p
#248~
255 byte
The structure of
t equations ca
nonlinearity. F
s follows. [6]
1 - xX
2t
) = 1 +
s of (x) prov
r patterns e(X
(x).[9] The ro
y testing (x)
his process is
inverse of root
xX

coder can find

vation of (x)
ns so that we
rd-correcting-
mial r(X) to the
rected data by
y the transfer
encoder. The
me as first tran
e are rearrang
g data, the da
by #1 shorte
oder. The dat
by #2 shorte
coder. The re
ymbols. Each
e method as th
tiple random e
errors in ma
r. Fig. 5 show
ymbol errors i

oes not affect
ng with the p
bution. So the
n total. Final
oder are rearr
ock and the de
3.
3 4 5
11 12 1
19 20 2
27 28 2
35 36 3
43 44 4
51 52 5
59 60 6

4 1835 1836 18
2 1843 1844 18
parity symbols for #
parity symbols for #2
parity symbols fo
coding in ro
f the proposed RS
annot be solve
irst, an error l
] (x) =

+
1
x +
2
x
2
vides the error
X). With BM a
oots of error l
) polynomials
s called "Chi
ts of (x). [10
X

error values.
, (n = 1, 2,
). The decoder
e obtain error
errors are g
e error polynom
y the convent
block and are
data transfer
nsfer block in
ged into colu
ata from 1
st
to
ened RS enco
ta from 113
th
t
ened RS enco
est of 135 em
symbol is co
he convention
errors can be
aximum with
ws that the p
in maximum w
t others, beca
properties of
e proposed co
lly, the data
ranged again t
ecoder issues
5 6 7
13 14 15
21 22 23
29 30 31
37 38 39
45 46 47
53 54 55
61 62 63
837 1838 1839
845 1846 1847
1 column wise
2 column wise
or row wise
ow wise
S decoding
d in the usual
locator polyno
xX

=
+ +
2t
x
2t
r location num
algorithm, we
locator polyno
s with each G
ien search." E
0] (x) = (x
X

x. Using t
The error valu
, v). Where
r finds error v
polynomial e
given by ad
mial. [7]
tional RS dec
e divided into
r block in dec
n the encoder.
umn-wise vec
o 112
th
and p
der are sent t
to 224
th
and p
der are sent t
mpty symbols
orrected in col
nal RS decode
corrected. We
a shortened (
roposed code
with the (255
ause each one
f independent
ode can correc
a processed b
to the origina
the corrected
8
16
24
32
40
48
56
64
1840
1848

l way
omial
(1 -
t
.

The
mbers
e find
omial
Galois
Error
x)s(x)
these
ue Y
n

(x)
alues
e(X).
dding
coder
o two
coder
. The
ctors.
parity
to #1
parity
to #2
s are
lumn
er. In
e can
(255,
e can
, 247)
e has
t and
ct 16
by a
l one
d data
T
max
row
erro
sym
even
How
conv
thos
sinc
corr
T
prop
info
(a) row wise er
Figure 6
The proposed
ximum. The co
wise. In Fig.
rs by a (255,
mbol errors tha
n though the
wever that e
ventional RS
se errors by c
e two shorte
rect 16 symbo
The symbol e
posed code are
rmation data a
P

rror pattern
Figure 5: E
6: Probability vs.
III. PER
d code can
onventional R
5 (a), there ar
247) RS cod
at can be cor
ey are shaped
error pattern
code. Thus
column wise d
ened RS code
l errors in max
error probabil
e calculated b
are independe
0
C

log

(b) column w
Error patterns
Eb/N0 of the vari
RFORMANCE
correct 16
RS code can co
re four of max
de. In Fig. 5 (
rrectable by t
d in the sam
cannot be
the proposed
decoding. In t
es are emplo
ximum.
lity and code
y following eq
ent and identic

wise error pattern
ious RS codes
symbol error
orrect 4 symbo
ximum correc
(b), there are
the proposed
me error patt
correctable b
d code can co
the proposed
yed the code
e efficiency o
quations, whe
cally distribute
(1)
(2)
(3)
(4)


rs in
ols in
ctable
eight
code
terns.
by a
orrect
code
e can
of the
en the
ed.
283
#1 sRS
#2 sRS
Transfer block for RS
Transfer block for sRS
RS

Figure 7: Layout of FPGA chip for the proposed RS code

TABLE I. DATA FOR FPGA IMPLEMENTATION OF THE PROPOSED RS CODE
ECC Gate count
Latency
(clk)
Operation
Freq.
(MHz)
Bandwidth
(Gbps)
Power
(mW)
Proposed
Product
Code
Total 43,501
554.5 290 1.07 26.44
sRS
6,075
6,089
Conventional
RS
6,080
Transfer for
sRS
7,880
Transfer for
RS
17,337

TABLE II. RESULTS OF FPGA IMPLEMENTATION OF RS CODE
ECC
Correct
(symbol)
Coding
gain
(@ 10
-7
)
gate
Latency
(clk)
Operation
Frequency
(MHz)
Bandwidth
(Gbps)
Power
(mW)
Proposed
ProductCode
16 2.9 43,501 554.5 290 1.07 26.44
(255, 247)
RS code
4 4.7 6,900 267.5 317 1.47 8.03
(255, 191)
RS code
[14]
32 3.5 11,681 -- 125 0.01 62
(239, 231)
Hamming * 8
8 - 20,544 24 550 43.82 52.56
(32767, 32692)
BCH [3]
5 - 0.044um
2
250us 25 0.036 1mA
Operation voltage : 1.2 V

(1) is a upper bound on the symbol error probability P
s
for
orthogonal signals. (2) is the symbol error rate of a Reed-
Solomon code. From this, we can calculate the symbol error
rate of the proposed product code in (3). (4) is the effective
E
s
/N
0
for (255, 247) conventional RS code.[11] In comparison,
we calculate the error probability of the proposed product RS
codes, that of (255,247) conventional RS code, that of (120,
118) shortened RS code, and that of (255, 191) conventional
RS code. Fig. 6 shows that the proposed code has the coding
gain of 1.8 dB over that of a conventional RS code and 0.6 dB
over that of [14].
IV. FPGA IMPLEMENTATION
The proposed product RS code is implemented by an
Alteras Stratix II FPGA chip (EP2S60F672C3) that contains
48,352 adaptive look-up tables and 2Mbit of on-chip memory.
The operation is measured Tektronixs TLA 5203 Logic
Analyzer. The entire circuits are designed by a verilog HDL
language using an Alteras Quartus II 7.0 program. [12][13]
The implementation experiment shows that the proposed
code has 43,501 gates and 554.5 clock latency as shown in
table 1. The coding controller operates 1.07 Gbps at the
maximum frequency of 290 MHz and consumes 26.4 mW in
1.2 V operation voltages. Table 2 summarizes the comparison
with other results reported. [14]
The proposed code shows the improved error correction
capability and coding gain over a conventional RS code. It has
faster operation frequency and more improved bandwidth than
other coding schemes. In comparison to other codes,
Hamming codes, a BCH code, and a ordinary RS code such as
the proposed code has more powerful error correction
capability.
Fig. 7 is the chip layout of the proposed code is drawn in
an Alteras Stratix II FPGA chip (EP2S60F672C3) by quartus
II 7.0.
V. CONCLUSION
This paper proposes a (255, 247) product Reed-Solomon
code for multiple random errors and burst errors. The proposed
code takes two dimensional array data consisted of two
shortened Reed-Solomon codes in a column-wise and a
conventional Reed-Solomon code in a row-wise. The proposed
code becomes powerful against multiple random errors and
burst errors. The proposed code can corrects 16 symbol errors.
The code has the coding gain of 1.8 dB and the bandwidth of
1.07 Gbps when operated at 290 MHz with the power
consumption of 26.4 mW.

ACKNOWLEDGEMENT
This work was supported by the Special Research Grant of
Sogang University, Korea and Hynix Semiconductor, Korea.

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