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eZdspTM F2812 Technical Reference

2003

DSP Development Systems

eZdspTM F2812 Technical Reference

506265-0001 Rev. F September 2003

SPECTRUM DIGITAL, INC. 12502 Exchange Dr., Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com

IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware, products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user, at his own expense, will be required to take any measures necessary to correct this interference. TRADEMARKS eZdsp is a trademark of Spectrum Digital, Inc.

Copyright 2003 Spectrum Digital, Inc.

Contents
1 Introduction to the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides a description of the eZdspTM F2812, key features, and board outline. 1.0 Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Key Features of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-3

2-1 Operation of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the operation of the eZdspTM F2812. Information is provided on the DSKs various interfaces. 2.0 The eZdspTM F2812 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1 The eZdspTM F2812 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 eZdspTM F2812 Memory 2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 eZdspTM F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.3 P3, Parallel Port/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.4 P4,P8,P7, I/O Interface ................................................ 2-9 2.3.5 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3.6 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.7 Connector Part Numbers .............................................. 2-14 TM 2.4 eZdsp F2812 Jumpers ............................................... 2-14 2.4.1 JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.4.2 JP4, JP5, Voltage Jumpers ............................................ 2-16 2.4.2.1 JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.4.2.2 JP5, +3.3/5 Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.4.4 JP9, PLL Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 eZdspTM F2812 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contains the schematics for the socketed and unsocketed versions of the eZdspTM F2812 A-1

eZdspTM F2812 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the socketed and unsocketed versions of the eZdspTM F2812

List of Figures ..................................... Figure 1-1, Block Diagram eZdspTM F2812 TM Figure 2-1, eZdsp F2812 PCB Outline ...................................... ................................... Figure 2-2, eZdspTM F2812 Memory Space TM F2812 Connector Positions ................................ Figure 2-3, eZdsp Figure 2-4, Connector P1 Pin Locations ....................................... Figure 2-5, Connector P2 Pin Locations ........................................ Figure 2-6, Connector P4/P8/P7 Connectors ................................... Figure 2-7, Connector P5/P9 Pin Locations ................................... Figure 2-8, Connector P6 Location .......................................... TM Figure 2-9, eZdsp F2812 Power Connector .................................. ................................ Figure 2-10, eZdspTM F2812 Jumper Positions TM Figure 2-11, eZdsp F2812 Voltage Jumper Positions(Bottom side) .............. 1-3 2-2 2-4 2-5 2-6 2-7 2-9 2-11 2-13 2-13 2-15 2-16

List of Tables Table 2-1, External Chip Select and Usages ................................... TM F2812 Connectors ....................................... Table 2-2, eZdsp Table 2-3, P1, JTAG Interface Connector ...................................... Table 2-4, P2, Expansion Interface Connector .................................. Table 2-5, P4/P8, I/O Connectors .......................................... Table 2-6, P7, I/O Connector .............................................. Table 2-7, P5/P9, Analog Interface Connector ................................. Table 2-8, Connector Part Numbers ........................................ Table 2-9, eZdspTM F2812 Jumpers .......................................... Table 2-10, JP1, XMP/MCn Select ........................................... Table 2-11, JP4, +3.3/5 Volts for P8, P2 ...................................... Table 2-12, JP5, +3.3/ Volts for P4 ........................................... Table 2-13, JP7,JP8, JP11, JP12, Boot Mode Select ........................... Table 2-14, JP9, PLL Disable .............................................. Table 2-15, LEDs ........................................................ Table 2-16, Test Points ................................................... 2-3 2-5 2-6 2-8 2-10 2-11 2-12 2-14 2-14 2-15 2-17 2-17 2-18 2-18 2-19 2-19

About This Manual This document describes board level operations of the eZdspTM F2812 based on the Texas Instruments TMS320F2812 Digital Signal Processor. The eZdspTM F2812 is a stand-alone module permitting engineers and software developers evaluation of certain characteristics of the TMS320F2812 DSP to determine processor applicability to design requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The eZdspTM F2812 will sometimes be referred to as the eZdsp. eZdsp will include the socketed or unsocket version Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;

Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide, literature #SPRU430 Texas Instruments TMS320C28x Assembly Language Tools Users Guide, literature #SPRU513 Texas Instruments TMS320C28x Optimizing C/C++ Compiler Users Guide, literature #SPRU514 Texas Instruments Code Composer Studio Getting Started Guide, literature #SPRU509

Chapter 1 Introduction to the eZdspTM F2812


This chapter provides a description of the eZdspTM for the TMS320F2812 Digital Signal Processor, key features, and block diagram of the circuit board.

Topic
1.0 1.1 1.2 Overview of the eZdspTM F2812 Key Features of the eZdspTM F2812 Functional Overview of the eZdspTM F2812

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1-2 1-2 1-3

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1.0 Overview of the eZdspTM F2812 The eZdspTM F2812 is a stand-alone card--allowing evaluators to examine the TMS320F2812 digital signal processor (DSP) to determine if it meets their application requirements. Furthermore, the module is an excellent platform to develop and run software for the TMS320F2812 processor. The eZdspTM F2812 is shipped with a TMS320F2812 DSP. The eZdspTM F2812 allows full speed verification of F2812 code. Two expansion connectors are provided for any necessary evaluation circuitry not provided on the as shipped configuration. To simplify code development and shorten debugging time, a C2000 Tools Code Composer driver is provided. In addition, an onboard JTAG connector provides interface to emulators, operating with other debuggers to provide assembly language and C high level language debug. 1.1 Key Features of the eZdspTM F2812 The eZdspTM F2812 has the following features: TMS320F2812 Digital Signal Processor 150 MIPS operating speed 18K words on-chip RAM 128K words on-chip Flash memory 64K words off-chip SRAM memory 30 MHz. clock 2 Expansion Connectors (analog, I/O) Onboard IEEE 1149.1 JTAG Controller 5-volt only operation with supplied AC adapter TI F28xx Code Composer Studio tools driver On board IEEE 1149.1 JTAG emulation connector

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1.2 Functional Overview of the eZdspTM F2812 Figure 1-1 shows a block diagram of the basic configuration for the eZdspTM F2812. The major interfaces of the eZdsp are the JTAG interface, and expansion interface.

30 Mhz.

A N A L O G

XTAL1/OSCIN ANALOG TO DIGITAL CONVERTER


E X P A N S I O N

P A R A L L E L P O R T

PARALLEL PORT/JTAG CONTROLLER

JTAG

TMS320F28xx
XZCS6AND7n EXTERNAL JTAG 64K x 16 SRAM
I / O E X P A N S I O N

Figure 1-1, BLOCK DIAGRAM eZdspTM F2812

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eZdspTM F2812 Technical Reference

Chapter 2 Operation of the eZdspTM F2812

This chapter describes the operation of the eZdspTM F2812, key interfaces and includes a circuit board outline.

Topic
2.0 2.1 2.1.1 2.2 2.2.1 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.4 2.4.1 2.4.2 2.4.2.1 2.4.2.2 2.4.3 2.4.4 2.5 2.6 The eZdspTM F2812 Operation The eZdspTM F2812 Board Power Connector eZdspTM F2812 Memory Memory Map eZdspTM F2812 Connectors P1, JTAG Interface P2, Expansion Interface P3, Parallel Port/JTAG Interface P4,P8,P7, I/O Interface P5,P9, Analog Interface P6, Power Connector Connector Part Numbers eZdspTM F2812 Jumpers JP1, XMP/MCn Select JP4, JP5 Voltage Jumpers JP4, +3.3/5 Volts for P8, P4 JP5, +3.3/5 Volts for P2 JP7,JP8,JP11,JP12, Boot Mode Select JP9, PLL Disable LEDs Test Points

Page
2-2 2-2 2-3 2-3 2-4 2-5 2-6 2-7 2-9 2-9 2-11 2-13 2-14 2-14 2-15 2-16 2-17 2-17 2-18 2-18 2-19 2-19

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2.0 The eZdspTM F2812 Operation This chapter describes the eZdspTM F2812, key components, and operation. Information on the eZdsps various interfaces is also included. The eZdspTM F2812 consists of four major blocks of logic: 2.1 The eZdspTM F2812 Board The eZdspTM F2812 is a 5.25 x 3.0 inch, multi-layered printed circuit board, powered by an external 5-Volt only power supply. Figure 2-1 shows the layout of both the socketed and unsocketed version of the F2812 eZdsp. Analog Interface Connector I/O Interface Connector JTAG Interface Parallel Port JTAG Controller Interface

Figure 2-1, eZdspTM F2812 PCB Outline

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2.1.1 Power Connector The eZdspTM F2812 is powered by a 5-Volt only power supply, included with the unit. The unit requires 500mA. The power is supplied via connector P6. If expansion boards are connected to the eZdsp, a higher amperage power supply may be necessary. Section 2.3.6 provides more information on connector P6. 2.2 eZdspTM F2812 Memory The eZdsp includes the following on-chip memory: 128K x 16 Flash 2 blocks of 4K x 16 single access RAM (SARAM) 1 block of 8K x 16 SARAM 2 blocks of 1K x 16 SARAM

In addition 64K x 16 off-chip SRAM is provided. The processor on the eZdsp can be configured for boot-loader mode or non-boot-loader mode. The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For larger software projects it is suggested to do a initial debug with on eZdsp F2812 module which supports a total RAM environment. With careful attention to the I/O mapping in the software the application code can easily be ported to the F2812. The table below shows the external chip select signal and its use. Table 1: External Chip Select and Usage Chip Select Signal XZCS0AND1n XZCS2n XZCS6AND7n Use Expansion header Expansion Header External SRAM

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2.2.1 Memory Map The figure below shows the memory map configuration on the eZdspTM F2812.

Figure 2-2, eZdspTM F2812 Memory Space Note: The on-chip flash memory has a security key which can prevent visibility when enabled.

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2.3 eZdspTM F2812 Connectors The eZdspTM F2812 has five connectors. Pin 1 of each connector is identified by a square solder pad. The function of each connector is shown in the table below: Table 2: eZdspTM F2812 Connectors Connector P1 P2 P3 P4/P8/P7 P5/P9 P6 Function JTAG Interface Expansion Parallel Port/JTAG Controller Interface I/O Interface Analog Interface Power Connector

The diagram below shows the position of each connector

P1 P2 P3

P4/P8/P7

P5/P9

P6

Figure 2-3, eZdspTM F2812 Connector Positions

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2.3.1 P1, JTAG Interface The eZdspTM F2812 is supplied with a 14-pin header interface, P1. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The positions of the 14 pins on the P1 connector are shown in the diagram below as viewed from the top of the eZdsp.

P1 13 11 9 7 5 3 4 1 2 1 2 14 12 10 8

JTAG Fig 2-4, P1 Pin Locations The definition of P1, which has the JTAG signals is shown below. Table 3: P1, JTAG Interface Connector Pin # 1 3 5 7 9 11 13 Signal TMS TDI PD (+5V) TDO TCK-RET TCK EMU0 Pin # 2 4 6 8 10 12 14 Signal TRSTGND no pin GND GND GND EMU1

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WARNING !
The TMS320F2812 supports +3.3V Input/Output levels which are NOT +5V tolerant. Connecting the eZdsp to a system with +5V Input/Output levels will damage the TMS320F2812. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent lactchup conditions. 2.3.2 P2, Expansion Interface The positions of the 60 pins on the P2 connector are shown in the diagram below as viewed from the top of the eZdsp. P2
2 1 4 3 6 5 8 10 12 7 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 9 11 13 15 17 19

Figure 2-5, Connector P2 Pin Locations

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The definition of P2, which has the I/O signal interface is shown below. Table 4: P2, Expansion Interface Connector
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Signal +3.3V/+5V/NC * XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XA0 XA2 XA4 XA6 XA8 XA10 XA12 XA14 GND XZCS0AND1n XREADY XRnW XWE +3.3V XRSn/RSn GND GND XA16 XA18 XHOLDAn No connect Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Signal +3.3/+5V/NC * XD1 XD3 XD5 XD7 XD9 XD11 XD13 XD15 XA1 XA3 XA5 XA7 XA9 XA11 XA13 XA15 GND XZCS2n 10K Pull-up 10K Pull-up XRDn XNMI/INT13 No connect GND GND XA17 XHOLDn No connect No connect

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JP5. 2-8 eZdspTM F2812 Technical Reference

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2.3.3 P3, Parallel Port/JTAG Interface The eZdspTM F2812 uses a custom parallel port-JTAG interface device. This device incorporates a standard parallel port interface that supports ECP, EPP, and SPP8/bidirectional communications. The device has direct access to the integrated JTAG interface. Drivers for C2000 Code Composer tools are shipped with the eZdsp modules 2.3.4 P4/P8/P7, I/O Interface The connectors P4, P8, and P7 present the I/O signals from the DSP. The layout of these connectors are shown below.
1 2 1 1 2 4 3 2 3 6 5 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

P4 P8

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 7 4 9 5 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 6 7 8 9 10

P7

Figure 2-6, P4/P8/P7 Connectors

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The pin definition of P4/P8 connectors are shown in the table below. Table 5: P4/P8, I/O Connectors P4 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P4 Signal +3.3V/+5V/NC * XINT2/ADCSOC MCLKXA MCLKRA MFSXA MFSRA MDXA MDRA No connect GND CAP5/QEP4 CAP6/QEPI2 T3PWM/T3CMP T4PWM/T4CMP TDIRB TCLKINB XF/XPLLDISn SCITXDB SCIRXDB GND P8 Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 P8 Signal +3.3V/+5V/NC * SCITXDA XINT1n/XBIOn CAP2/QEP2 PWM1 PWM3 PWM5 T1PWM/T1CMP TDIRA GND No connect SPISIMOA SPICLKA CANTXA XCLKOUT PWM8 PWM10 PWM12 T1CTRIP/PDPINTAn GND P8 Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P8 Signal +3.3V/+5V/NC * SCIRXDA CAP1/QEP1 CAP3/QEPI1 PWM2 PWM4 PWM6 T2PWM/T2CMP TCLKINA GND XINT1N/XBIOn SPISOMIA SPISTEA CANRXA PWM7 PWM9 PWM11 CAP4/QEP3 T3CTRIP/PDPINTBn GND

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JP4.

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The pin definition of P7 connector is shown in the table below. Table 6: P7, I/O Connector P7 Pin # 1 2 3 4 5 6 7 8 9 10 P7 Signal C1TRIPn C2TRIPn C3TRIPn T2CTRIPn/EVASOCn C4TRIPn C5TRIPn C6TRIPn T4CTRIPn/EVBSOCn No connect GND

2.3.5 P5/P9, Analog Interface The position of the 30 pins on the P5/P9 connectors are shown in the diagram below as viewed from the top of the eZdsp.

P5 1 2 1 P9 2 4 3 3 6 5 4 8 7

ANALOG 5 9 6 7 8 9 10 10 12 14 16

18 20

11 13 15 17 19

Figure 2-7, Connector P5/P9 Pin Locations

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The definition of P5/P9 signals are shown in the table below. Table 7: P5/P9, Analog Interface Connector P5 Pin # 1 2 3 4 5 6 7 8 9 10 Signal ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP P9 Pin # 1 3 5 7 9 11 13 15 17 19 Signal GND GND GND GND GND GND GND GND GND GND P9 Pin # 2 4 6 8 10 12 14 16 18 20 Signal ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 VREFLO * No connect

* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.

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2.3.6 P6, Power Connector Power (5 volts) is brought onto the eZdspTM F2812 via the P6 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2 mm. The position of the P6 connector is shown below.

TP1 POWER Figure 2-8, Connector P6 Location The diagram of P6, which has the input power is shown below. +5V P6 Ground PC Board Front View Figure 2-9, eZdspTM F2812 Power Connector

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2.3.7 Connector Part Numbers The table below shows the part numbers for connectors which can be used on the eZdspTM F2812. Part numbers from other manufacturers may also be used.

Table 8: eZdspTM F2812 Suggested Connector Part Numbers Connector P1 P2 Male Part Numbers SAMTEC TSW-1-10-07-G-T SAMTEC TSW-1-20-07-G-T *SSW or SSQ Series can be used 2.4 eZdspTM F2812 Jumpers The eZdspTM F2812 has 8 jumpers available to the user which determine how features on the eZdspTM F2812 are utilized. The table below lists the jumpers and their function. The following sections describe the use of each jumper. Table 9: eZdspTM F2812 Jumpers Jumper # JP1 JP4 JP5 JP7 JP8 JP9 JP11 JP12 Size 1x3 1x3 1x3 1x2 1x3 1x3 1x3 1x3 Function XMP/MCn +3.3/5 Volts to P8,P4 +3.3/5 Volts to P2 Boot Mode 3 Boot Mode 2 PLL Disable Boot Mode 1 Boot Mode 0 Position As Shipped From Factory 2-3 Not connected Not Connected 2-3 2-3 1-2 1-2 2-3 Female Part Numbers SAMTEC SSW-1-10-01-G-T SAMTEC SSW-1-20-01-G-T

WARNING! Unless noted otherwise, all 1x3 jumpers must be installed in either the 1-2 or 2-3 position

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The diagram below shows the positions of six jumpers on the component side of the eZdspTM F2812.

JP9

JP8

JP7

DS2 DS1

JP1 JP11 JP12

TP1

TP2

Figure 2-10, eZdspTM F2812 Jumper Positions


2.4.1 JP1, XMP/MCn Select Jumper JP1 is used to select the XMP/MCn option. The 1-2 selection allows the DSP to operate in the Microcontroller mode. The 2-3 selection allow the DSP to operate in the Microprocessor mode. The positions are shown in the table below. Table 10: JP1, XMP/MCn Select Position
1-2 2-3 *

Function
Microprocessor mode Microcomputer mode

* as shipped from factory

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2.4.2 JP4, JP5 Voltage Jumpers Jumpers JP4 and JP5 are an unpopulated jumpers on the bottom side of the board that provide either +3.3 volts or +5 volts to pins on the expansion connectors. These jumpers are shipped uninstalled to prevent accidental damage by connecting wires or circuitry to the expansion connector. The user may connect these jumpers by installing a jumper wire or zero ohm resistor. The position of these jumpers are shown in the figure below. JP5

JP4

Figure 2-11, eZdsp

TM

F2812 Voltage Jumper Positions (Bottom Side)

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2.4.2.1 JP4, +3.3/5 Volts for P8, P4 Jumper JP4 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of expansion connector P8, and pin 1 of P4. The settings for this jumper are shown in the table below Table 11: JP4, +3.3/5 Volts for P8, P4 Position
1-2

Function
Connect +5 Volts to P8, pins 1,2, and P4 pin1 Connect +3.3 Volts to P8, pins 1,2, and P4 pin1

Jumper Position 5V JP4 5V JP4 5V JP4 3.3V 3.3V 3.3V

2-3

No connect *

* As shipped from factory

2.4.2.2 JP5, +3.3/5 Volts for P2 Jumper JP5 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of expansion connector P2. The settings for this jumper are shown in the table below. Table 12: JP5, +3.3/5 Volts for P2 Position
1-2

Function
Connect +5 Volts to P2, pins 1,2 Connect +3.3 Volts to P2, pins 1,2

Jumper Position JP5 5V JP5 5V JP5 5V 3.3V 3.3V 3.3V

2-3

No connect *

* As shipped from factory

2-17

Spectrum Digital, Inc


2.4.3 JP7, JP8, JP11, JP12, Boot Mode Select Jumpers JP7, JP8, JP11, JP12 are used to determine what mode the DSP will use for bootloading on power up. To set a signal high, place the jumper in the 1-2 position. For a low signal, use the 2-3 position.The options are shown in the table below. Table 13: JP7, JP8, JP11, JP12, Boot Mode Select JP7, BOOT3 SCITXDA
1 0 0 0 0 0

JP8, BOOT2 MDXA


X 1 0 0 0 0

JP11, BOOT1 SPISTEA


X X 1 1 0 0

JP12, BOOT0 SPICLKA


X X 1 0 1 0

MODE
FLASH SPI SCI H0 * OTP PARALLEL

* factory default

2.4.4 JP9, PLL Disable Jumper JP9 is used to enable/disable the use of the Phase Lock Loop (PLL) logic on the DSP. The selection of the 1-2 position enables the use of the PLL. If the 2-3 position is used the PLL is disabled. This signal is latched at reset and may be used as XF after reset. The positions are shown in the table below. Table 14: JP9, PLL Disable Position
1-2 * 2-3

Function
PLL Enabled PLL disabled

* as shipped from the factory

2-18

eZdspTM F2812 Technical Reference

Spectrum Digital, Inc


2.5 LEDs The eZdspTM F2812 has two light-emitting diodes. DS1 indicates the presence of +5 volts and is normally on when power is applied to the board. DS2 is under software control and is tied to the XF pin on the DSP through a buffer. These are shown in the table below. Table 15: LEDs LED #
DS1 DS2

Color
Green Green

Controlling Signal
+5 Volts XF bit (XF high = on)

2.6 Test Points The eZdspTM F2812 has two test points. The signals they are tied to are shown in the table below. Table 16: Test Points Test Point
TP1 TP2

Signal
Ground Analog Ground

2-19

Spectrum Digital, Inc

2-20

eZdspTM F2812 Technical Reference

Appendix A eZdspTM F2812 Schematics

The schematics for the eZdspTM F2812 can be found on the CD-ROM that accompanies this board. The schematics were drawn on ORCAD. The schematics are correct for both the socketed and unsocketed version of the eZdspTM.

WARNING !
The TMS320F2812 supports +3.3V Input/Output levels which are NOT +5V tolerant. Connecting the eZdsp to a system with +5V Input/Output levels will damage the TMS320F2812. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.

Design Notes: 1. The TMS320F2812 X1/CLKIN pin is +1.8 volt input. The clock input is buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides +3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the schematics.

A-1

A-2
REVISIONS REV DESCRIPTION DATE APPROVED

PROTOTYPES

04-April-2002

B C UPDATE PER SPRS174G 20-Jan-2003

PRODUCTION RELEASE

07-June-2002
D

Spectrum Digital, Inc

The TMS320F2812 EzDSP design is based on preliminary information(SPRS174G) for the TMS320F2812 device. This schematic is subject to change without notification. Spectrum Digital Inc. assumes no liability for applications assistance, customer product design or infringement of patents described herein.
B

DWN CHK ENGR ENGR-MGR DATE DATE DATE DATE QA MFG NEXT ASSY RLSE APPLICATION USED ON DATE DATE

DATE

REVISION STATUS OF SHEETS


A

REV

SH

REV

SPECTRUM DIGITAL INCORPORATED


Title TMS320F2812 EzDSP Size B Date:
3 2

SH

REV

Document Number 506262 Wednesday, June 04, 2003 Sheet


1

Rev C 1 of 6

SH
4

eZdspTM F2812 Technical Reference

3.3V (4,6) XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18 1.8V (6) VDD3VFL

(3,4,5,6) GND

XA[0..18] XD[0..15]

(3,4) (3,4)

(3,4,5,6) AGND 69 31 64 81 114 145 23 37 56 75 100 112 128 143 154 18 43 80 85 103 108 111 118 121 125 130 132 138 141 144 148 152 156 158 U8

VDD I/0 -3.3V

10UF CERAMIC LOW ESR C35

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4)
FLASH - 3.3V

TAIYO YUDEN EMK325F106ZH-T

ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7
VDD CORE - 1.8V

(4) ADCREFM (4) ADCREFP

174 173 172 171 170 169 168 167 2 3 4 5 6 7 8 9 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15

VDD3VFL

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5

VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10

XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 XA18

21 24 27 30 33 36 39 54 65 68 73 74 96 97 139 147

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15

10UF CERAMIC LOW ESR C36 R26 24.9K VDDA1

TP3

11 10 16 12 13 175 ADCBGREFIN 164 ADCREFP ADCREFM ADCRESEXT AVSSREFBG AVDDREFBG ADCLO ADCBGREFIN

RN2A RN2B RN2C RN2D RN2E RN2F XZCS0AND1n XZCS2n XZCS6AND7n XWEn XRDn XRnW XREADY XMP/MCn XHOLDn XHOLDAn XRSn 44 88 133 84 42 51 161 17 159 82 160 77 76 119 X1/XCLKIN X2 XCLKOUT TESTSEL TEST1 TEST2 TRSTn TCK TMS TDI TDO EMU0 EMU1 134 67 66 135 136 126 131 127 137 146

1 2 3 4 5 6

TP

A A A A A A

B 16 33 15 B 33 14 B 33 B 13 33 B 12 33 11 B 33

XZCS0AND1n XZCS2n XZCS6AND7n XWEn XRDn XRnW XREADY XMP_MCn XHOLDn XHOLDAn XRSn X1_CLKIN XCLKOUT XTESTSEL

(4) (4) (3) (3,4) (3,4) (4) (4) (4) (4) (4) (5) (4) (4) (3,4,5,6)

(4)

VREFLO

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) GPIOA0-PWM1 GPIOA1-PWM2 GPIOA2-PWM3 GPIOA3-PWM4 GPIOA4-PWM5 GPIOA5-PWM6 GPIOA6-T1PWM_T1CMP GPIOA7-T2PWM_T2CMP GPIOA8-CAP1_QEP1 GPIOA9-CAP2_QEP2 GPIOA10-CAP3_QEPI1 GPIOA11-TDIRA GPIOA12-TCLKINA GPIOA13-C1TRIPn GPIOA14-C2TRIPn GPIOA15-C3TRIPn

PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 T1PWM_T1CMP T2PWM_T2CMP CAP1_QEP1 CAP2_QEP2 CAP3_QEPI1 TDIRA TCLKINA C1TRIPn C2TRIPn C3TRIPn

92 93 94 95 98 101 102 104 106 107 109 116 117 122 123 124

C28_TRSTn C28_TCK C28_TMS C28_TDI C28_TDO C28_EMU0 C28_EMU1

(5) (5) (5) (5) (5) (5) (5)

GPIOF0-SPISIMOA GPIOF1-SPISOMIA GPIOF2-SPICLKA GPIOF3-SPISTEA

40 41 34 35

SPISIMOA SPISOMIA SPICLKA SPISTEA

(4) (4) (4) (4)

SINGLE POINT CONNECTION 1 AGND TP2

L4 VDD1 110 115 79 83

( 1.8V
(4) (4) (4) (4) (4) XINT1n_XBIOn (4) XINT2n_ADCSOC (4) XNMIn_XINT3 149 151 150 T1CTRIP_PDPINTAn T2CTRIPn_EVASOCn T3CTRIP_PDPINTBn T4TRIPn_EVBSOCn

ADC

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) GPIOB0-PWM7 GPIOB1-PWM8 GPIOB2-PWM9 GPIOB3-PWM10 GPIOB4-PWM11 GPIOB5-PWM12 GPIOB6-T3PWM_T3CMP GPIOB7-T4PWM_T4CMP GPIOB8-CAP4_QEP3 GPIOB9-CAP5_QEP4 GPIOB10-CAP6_QEPI2 GPIOB11-TDIRB GPIOB12-TCLKINB GPIOB13-C4TRIPn GPIOB14-C5TRIPn GPIOB15-C6TRIPn

PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 T3PWM_T3CMP T4PWM_T4CMP CAP4_QEP3 CAP5_QEP4 CAP6_QEPI2 TDIRB TCLKINB C4TRIPn C5TRIPn C6TRIPn

45 46 47 48 49 50 53 55 57 59 60 71 72 61 62 63

GPIOF8-MCLKXA GPIOF9-MCLKRA GPIOF10-MFSXA GPIOF11-MFSRA GPIOF12-MDXA GPIOF13-MDRA GPIOF4-SCITXDA GPIOF5-SCIRXDA GPIOG4-SCITXDB GPIOG5-SCIRXDB
1.8V

28 25 26 29 22 20 155 157 90 91 GPIOF6-CANTXA GPIOF7-CANRXA VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 GPIOF14-XF-XPLLDISn 19 32 38 52 58 70 78 86 99 105 113 120 129 142 153 87 89 140

MCLKXA MCLKRA MFSXA MFSRA MDXA MDRA SCITXDA SCIRXDA SCITXDB SCIRXDB CANTXA CANRXA XF_XPLLDISn

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4)

1.8V

BLM21P221SN

GPIOD0-T1CTRIP_PDPINTAn GPIOD1-T2CTRIPn_EVASOCn GPIOD5-T3CTRIP_PDPINTBn GPIOD6-T4CTRIPn_EVBSOCn GPIOE0-XINT1_XBIOn GPIOE1-XINT2_ADCSOC GPIOE2-XNMI_XINT13

C2 1uF

C58 .1uF

C56 .001uF

14 VDDA1 166 VDDA2 15 VSSA1 165 VSSA2

162 VDD1 163 VSS1

( 3.3V
VDDA1 C37 .001uF

)
TMS320F2812PGF

1 VDDAIO 176 VSSAIO

3.3V

L3

DSP
SPECTRUM DIGITAL INCORPORATED
Title TMS320F2812 EzDSP Size B Date: Document Number 506262 Wednesday, June 04, 2003 Sheet 2 of 6 Rev C

BLM21P221SN

C3 1uF

C57 .1uF

C38 .1uF

LOCATE NEAR DSP


4 3 2

Spectrum Digital, Inc

A-3

11 33

VDD1 VDD2

12 34

IS61LV6416-12T

VSS1 VSS2

A-4
4 3 2 1 D

Spectrum Digital, Inc

XA[0..18] XD[0..15] (2,4)

(2,4)
C

3.3V

C22 0.1uF U4

C10 0.1uF

XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XA11 XA12 XA13 XA14 XA15 XA16 XA17 1 2 3 4 5 18 19 20 21 24 25 26 27 42 43 44 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A11 A12 A13 A14 A15 A16 A17 A9 A10 NC CS WE OE BHE BLE 28 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 6 17 41 40 39 7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38 (2) XZCS6AND7n (2,4) XWEn (2,4) XRDn

XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15

64Kx16 and 256Kx16 Compatible

SPECTRUM DIGITAL INCORPORATED

ASRAM

Title TMS320F2812 EzDSP Size B Date: Document Number 506262 Wednesday, June 04, 2003
3 2

(2,4,5,6) GND Rev B Sheet


1

of

eZdspTM F2812 Technical Reference


4

3.3V +5V B A B JUMPER3_SMT 2 PLLDISn 3.3V R41 2.2K 3 JUMPER3B R42 1 10K JP9 2 JUMPER3_SMT 1 C A 3 1 +5V

JP5 3.3V

JP4

Make a solder connection on JP4 and/or JP5 to the appropriate power supply.

XF_XPLLDISn

(2)

P2

P8

3.3V DS2 LTST-C150GKT GREEN

(2) (2) (2) (2) (2) (2) (2) (2) 3.3V

SCITXDA XINT1n_XBIOn CAP2_QEP2 PWM1 PWM3 PWM5 T1PWM_T1CMP TDIRA

SCIRXDA (2) CAP1_QEP1 (2) CAP3_QEPI1 (2) PWM2 (2) PWM4 (2) PWM6 (2) T2PWM_T2CMP (2) TCLKINA (2)

C62 .1uF 5 U12 R43 SN74AHC1G14 2 XF 3 4 220 XF

(2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) ISn STRBn XRDn XNMIn_XINT3 (2,3) (2) XZCS2n (2) (2) SPISIMOA (2) SPICLKA (2) CANTXA (2) XCLKOUT (2) PWM8 (2) PWM10 (2) PWM12 (2) T1CTRIP_PDPINTAn 3.3V XINT1n_XBIOn (2) SPISOMIA (2) SPISTEA (2) CANRXA (2) PWM7 (2) PWM9 (2) PWM11 (2) CAP4_QEP3 (2) T3CTRIP_PDPINTBn (2)

XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XA0 XA2 XA4 XA6 XA8 XA10 XA12 XA14

XD1 XD3 XD5 XD7 XD9 XD11 XD13 XD15 XA1 XA3 XA5 XA7 XA9 XA11 XA13 XA15

(2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3) (2,3)

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

T M S3 2 0 F2 8 1 2 s up p o r t s 3 .3 V i n p u t /o u t p u t l e v e l s w h i c h a re N OT 5 V t o l e r a n t . Co n n e c t i n g t he eZdsp t o a s yst em w it h 5V i n p u t /o u t p u t l e v e l s w i l l d a m a g e t h e T M S3 2 0 F2 8 1 2 . If t h e e Z d s p i s c o n n e c t e d t o a n o t h e r t a rg e t t h e n t h e e Zd s p m u s t b e pow ered up first and pow ered d o w n l a s t t o p r e v e n t l a t c hu p condi t ion s .

(2) XZCS0AND1n (2) XREADY (2) XRnW (2,3) XWEn 3.3V (5) DSP_RSn P4 P7

DSP_RSn

XTESTSEL XTESTSEL (2,3,5,6)


C

(2,3) (2) (2)

XA16 XA18 XHOLDAn

XA17 XHOLDn

(2,3) (2)

1 3

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

JP1 XMPNMC 2 JUMPER3B R39 R36 10K 2.2K 1 3 JUMPER3B R38 R35 10K 2.2K 1 3 JUMPER3B R40 R37 10K 2.2K 1 3 JUMPER3B R31 R30 10K 2.2K 1 3 JUMPER3B JP7 2 BOOT-3 JP8 2 BOOT-2 JP11 BOOT-1 2 JP12 BOOT-0 2

XMP_MCn

(2)

HEADER 30X2

(2) XINT2n_ADCSOC (2) MCLKXA (2) MCLKRA (2) MFSXA (2) MFSRA (2) MDXA (2) MDRA

C1TRIPn (2) C2TRIPn (2) C3TRIPn (2) T2CTRIPn_EVASOCn (2) C4TRIPn (2) C5TRIPn (2) C6TRIPn (2) T4TRIPn_EVBSOCn (2)

SPICLKA

(2)

P9

1 2 3 4 5 6 7 8 9 10

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

MDXA

(2)

P5

BOOT MODE

ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 VREFLO

(2) (2) (2) (2) (2) (2) (2) (2) (2)

(2) CAP5_QEP4 (2) CAP6_QEPI2 (2) T3PWM_T3CMP (2) T4PWM_T4CMP (2) TDIRB (2) TCLKINB (2) XF_XPLLDISn (2) SCITXDB (2) SCIRXDB

SPISTEA

(2)

Connect VREFLO to AGND or to VREFLO of target system for proper ADC operation.

SCITXDA

(2)

L1 (2,6) 1.8V

3.3V BOOT-3 SCITXDA BLM21P221SN C43 BOOT-2 MDXA BOOT-1 SPISTEA BOOT-0 SPICLKA MODE

1 2 3 4 5 6 7 8 9 10 U14 5 R1 (2) 100 1 3 A X1_CLKIN 4 2 2 JP3 B C 3 100 JUMPER3_SMT R29 SN74LVC1G14

ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP

(2) (2) (2) (2) (2) (2) (2) (2) (2) (2)

1 0.1uF U11 8 5 C42 33 pF SMT/4PIN DIP VCC OFFn CLK GND NO-POP 1 4 0 0 0 0 0

X 1 0 0 0 0

X X 1 1 0 0

X X 1 0 1 0

FLASH SPI SCI H0 OTP PARALLEL


A

Tie off unused F24xx compatible signals.

R6

ISn

3.3V

10K

R5

STRBn

10K (5)

Schematic change from version A/B to C. F2812 clkin is 1.8V input.


MCLK

GND

OPTIONAL
Title TMS320F2812 EzDSP Size B Document Number 506262
6 5 4 3

GND

(2,3,5,6)

AGND

(2,3,5,6)

Rev C Date:
2 Wednesday, June 04, 2003

Spectrum Digital, Inc

A-5
7

Sheet

of

R16 U5 C52 33pf C53 R13 10K 33pf C55 33pf P1 C50 .1uF 74ABT245PW 33pf C29 33pf PPEMU0 HEADER 7X2 PPEMU1 XDS510PP EMULATION HEADER PPSLCT PPPE PPBSY PPACKn PPD7 PPD6 10 PPD5 .1uF 74ABT245PW PPD4 .001uF C27 C28 B1 B2 B3 B4 B5 B6 B7 B8 A A A A A A A A B B B B B B B B VCC GND 20 5V 18 17 16 15 14 13 12 11 RN1A RN1B RN1C RN1D RN1E RN1F RN1G RN1H 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 33 33 33 33 33 33 33 33 P3 DB25_SHIELD U2 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 G DIR 19 1 EMUOFF .001uF C31 33pf 10K
D

100 XEVNT0 99 98 XTRSTn 97 PPTRSTn 96 IPPTCK 95 XTDI 94 93 IPPTDO 92 GND 91 FPGA_VCCA 90 VCCR 89 XTCKI 88 GND 87 JCLK 86 XTMS 85 PPTMS 84 XTDO 83 3.3V 82 PPTDI 81 80 79 78 77 EMUOFF 76

RSV13_TCK_IO XEVNT0 PPEMU0 XTRSTn PPTRSTn PPTCK XTDI PPTDO RSV11_PRA_IO GND VCCA VCCR_NC XTCKI RSV10 JCLK XTMS PPTMS XTDO VCCI PPTDI ODEMU0n ODEMU1n ODEMU0_SRC ODEMU1_SRC EMUOFF_1

PPBUSENn RSV6 PPBUSDIR RSV7 XPPC3n XPPC2 XPPC1n XPPC0n RSV8_PRB_IO VCCA GND VCCR_NC ALT_MCLK HCLK RSV9 PONRSn TPOWLOSSn VFUNC_EN VCCI EXT_VER7 EXT_VER6 EXT_VER5 EXT_VER4 EXT_VER3 EXT_VER2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PPBUSENn

PPBUSDIR

XPPC3n XPPC2 XPPC1n XPPC0n

FPGA_VCCA GND VCCR ALT_MCLK MCLK

PONRSnIN TPOWLOSSn GND 3.3V GND GND 3.3V 3.3V GND GND

A-6
R14 10K 10K A1 A2 A3 A4 A5 A6 A7 A8 A A A A A A A A C54 33pf C33 C51 33pf C32 R17 PPTRSTn 3.3V B B B B B B B B G DIR GND 10 VCC 20 5V B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11 RN3A RN3B RN3C RN3D RN3E RN3F RN3G RN3H 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 33 33 33 33 33 33 33 33 PPTMS PPTDI 5V PPTDO PPTCK 1 3 5 7 9 11 13 2 4 6 8 10 12 14
PPEMU0/1 CONNECT DIRECTLY TO F2812 FOR EMULATOR WAIT-IN-RESET SUPPORT

XPPD7 XPPD6 XPPD5 XPPD4 XPPD3 XPPD2 XPPD1 XPPD0

RN4A RN4B RN4C RN4D RN4E RN4F RN4G RN4H

1 2 3 4 5 6 7 8

A A A A A A A A

B B B B B B B B

16 15 14 13 12 11 10 9

33 33 33 33 33 33 33 33

2 3 4 5 6 7 8 9

PPBUSENn PPBUSDIR

19 1

XPPS4 XPPS5 XPPS7n XPPS3

Spectrum Digital, Inc

5V

XPPC3n PONRSnIN B XTRSTn PLACE NEAR EACH MOUNTING HOLE XTDI 3.3V XTDO R19 C16 R11 R12 10K R22 10K TPOWLOSSn 10K 1M .001uF .001uF R20 100 100 R24 100 R15 R8 XTCK 100 R18 100 33pf PPTCK PPTDO 33pf C17 3.3V R10 R9 33 33 33 33pf C15 C30 33pf R25 C34 1M C67 R47 XTCK XEVNT0 XEVNT1 XTMS XPPC2 XPPC1n XPPC0n

PPD3 PPSELn PPD2 PPINITn PPD1 PPERRn PPD0 PPALEn PPSTRBn PONRSnIN C28_TRSTn C28_TMS C28_TDO C28_TDI C28_TCK C28_EMU0 C28_EMU1

13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 (6) (2) (2) (2) (2) (2)

CROSS COUPLE IN TO O UT

(2) (2)

C14 0.1uF Locate R7,R54, C70 at the DSP XRSn pin for best EMI/ESD noise immunity. 3.3V U6 U13 1 2 R54 DSP_RSn 100 GND C70 22nF XRSn (2)
IF U13 IS INSTALLED THEN REMOVE R49 AND R48.

C25 0.1uF

C26 0.1uF

C49 0.1uF

3.3V

R49 0 FPGA_VCCA IN GND 3 EN NC/FB TPS72201 4 41.2K 1% OUT 5

R7 1.5K OPEN-DRAIN

XRSn is logical AND of PONRSnIN and emulator controlled reset. Power on default is PONRnIN controls XRSn.

R50 C45 0.1uF C23 0.1uF C24 0.1uF C11 0.1uF C68 1uF

GND

3.3V

3.3V XEVNT1

R23 DSP_RSn
To/from expansion header

R51 (4) 40.2K 1%

10K

GND 3.3V GND GND FPGA_VCCA

+5V GND GND GND GND 3.3V FPGA_VCCA

R48 VCCR 0 C47 0.1uF C13 0.1uF

3.3V GND XPPD0 XPPD1 XPPD2 XPPD3 XPPD4 XPPD5 XPPD6 XPPD7

3.3V XPPS3 XPPS4 XPPS5 3.3V GND GND

XPPS7n

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DSP_RSn MCLKOUT MCLKOUTEN MCLKOUT2 MCLKOUT2EN EXTERN_RSTn GND GND VCCA SPECTRUM DIGITAL I NC. XBITOUT0 XBITOUT1 EMBEDDED PP JTAG CONRO T LLER XBITOUT2 XBITOUT3 506053-000 1B XBITIN0 XBITIN1 EXT_VER 00110-001 XBITIN2 XBITIN3 VCCI VCCA VBUS_ENn VPOWER_BLEED VPOWER_ONn EXT_VER0 EXT_VER1 GND

GND RSV1_TDI_IO EMUOFF XEVNT1 PPEMU1 RSV2 RSV3_TMS_IO VCCI GND XPPD0 XPPD1 XPPD2 XPPD3 XPPD4 XPPD5 XPPD6 XPPD7 RSV4 RSV5 VCCI XPPS3 XPPS4 XPPS5 XPPS6 XPPS7n

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

L2 506053-0001B

3.3V

BLM21P221SN C48 0.1uF 5V +5V 3.3V U10 8 R32 5 33 C46 VCC OFFn CLK 30 MHz NO-POP CBLV-3C-30.000
4 3 2

3.3V GND 1 4 GND Title TMS320F2812 EzDSP Size C Date: Document Number 506262 Wednesday, June 04, 2003
1

GND

(2,3,4,6)

SPECTRUM DIGITAL INCORPORATED

(4) MCLK

Rev C Sheet 5 of 6

eZdspTM F2812 Technical Reference

+5V U9 5 6 C66
+

P6 1IN 1IN 1RESET 1EN 1OUT 1OUT 1FB/SENSE R33 16.9K, 1% C64
+

28

18.2K 1.899V 16.9K 1.848V 15.0K 1.773V 13.7K 1.722V 1.8V (2,4)

1.8VONn 4 3 1GND 0.1uF R45 11 12 C65 10 0.1uF 2EN 2OUT 2OUT 2SENSE C63
+

+5V Max

R44 220 0.1uF CT3 22uF 23 24 25 30.1K, 1%

CT2 47uF

DS1 LTST-C150GKT GREEN 2IN 2IN 17 18 19 CT4 22uF 0.1uF R52 0 3.3V 2RESET 22

3.3V

R46 10K 3.3V

9 2GND

VDD3VFL

(2)

U16 R53 D 1.5K 1% G S R34 2.0K 1% TIE TPS767D301 POWER PAD TO GND PLANE (TI-SLMA002) Q3 BSS138 TPS767D301

THERMAL_PAD

CT

1 2 7 8 13 14 NC NC NC NC NC NC NC NC NC NC NC NC

15 16 20 21 26 27

VDD

C1 1uF

C7 .1uF

GND

RESETn

R2 10K
C

MRn

TPS3838K33DBV

RESETn of TPS3838 is open-drain. U16 was added for testing but not populated on production boards.

PONRSnIN

(5)

1.8V

(2,4)

CT6 22uF

CT5 22uF

C19 0.1uF

C18 0.1uF

C5 0.1uF

C8 0.1uF

C21 0.1uF

C41 0.1uF

C40 0.1uF

C61 0.1uF

C59 0.1uF

3.3V
B

CT1 22uF C20 0.1uF C6 0.1uF C9 0.1uF C39 0.1uF C60 0.1uF

TP1 GND (2,3,4,5) GND

POWER ON SEQUENCE NOTES 3.3V SUPPLY, VDDIO VDD3VFL, VDDA1,VDDA2 2.2V Q3

TPS767D301 RATINGS MAX Iout PER CHANNEL IS 1A TPS767D301 PD = (Vin-Vout)*Iout VOLTAGE SUPPLY 1.8V SUPPLY 1.8V 3.3V 140ms-280ms PD(max) = (Tj(max) - Ta)/Rja Title PONRSnIN = (125 - 35)/27.9 = 3255mW Size B Date:
4 3 2

3.3V THEN 1.8V

PONRSnIN, GOES HIGH > 200ms AFTER ALL POWER IS STABLE.

MAX CURRENT 333mA 307mA

TPS767D301 PD 1065mW 521mW 1586mW Total


A

SET Q3 TO TURN ON WHEN 3.3V SUPPLY IS GREATER THEN 2.2 VOLTS. REGULATOR TURN ON DELAY AND RAMP RATE WILL ENSURE THAT 3.3V SUPPLY IS AT 2.5 VOLTS OR HIGHER BEFORE THE 1.8V SUPPLY REACHES 0.3 VOLTS.

SPECTRUM DIGITAL INCORPORATED


TMS320F2812 EzDSP Document Number 506262 Wednesday, June 04, 2003 Sheet
1

U16 WILL TURN OFF THE 1.8V SUPPLY WHEN INPUT POWER FALLS BELOW 2.94V. THIS SPEEDS UP THE 1.8V SUPPLY TURN OFF.

Rev C 6 of 6

Spectrum Digital, Inc

A-7

Spectrum Digital, Inc

A-8

eZdspTM F2812 Technical Reference

Appendix B eZdspTM F2812 MechanicaI Information

This appendix contains the mechanical information about the socketed and unsocketed versions of the eZdspTM F2812

B-1

Spectrum Digital, Inc

B-2

eZdspTM F2812 Technical Reference

This drawing is not to scale

Spectrum Digital, Inc

This drawing is not to scale

B-3

Spectrum Digital, Inc

B-4

eZdspTM F2812 Technical Reference

Printed in U.S.A., September 2003 506265-0001 Rev. F