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Features
Optimized for 1.8V systems - As fast as 6.0 ns pin-to-pin delays - As low as 27 A quiescent current Industrys best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation 1.5V to 3.3V Available in multiple package options - 144-pin TQFP with 118 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 212 user I/O - 324-ball FG (1.2mm) BGA with 240 user I/O Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management - Four seperate output banks - Fast Zero Power (FZP) 100% CMOS product term generation - DataGATE enable (DGE) signal control - Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16) CoolCLOCK - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Advanced design security - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pullup on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility - Hot pluggable
Description
The CoolRunner-II 384-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of twenty four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchonous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
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XC2C384 CoolRunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is output banking. Four output banks are available on the CoolRunner-II 384 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II 384 macrocell CPLD is I/O compatible with various I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
I/O Types LVTTL LVCMOS33 LVCMOS25 LVCMOS18 1.5V I/O HSTL-1 SSTL2-1 SSTL3-1
20
15
ICC (mA)
10
Frequency (MHz)
Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical -7, -10 ICC (mA) Typical -6 ICC (mA)
Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block).
25
50
75
100
125
150
175
200
225
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Storage Temperature (ambient) Maximum Soldering temperature (10s @ 1/16in. = 1.5mm) Junction Temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA.
Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation
VAUX
JTAG programming
Parameter Standby current (-7, -10) Standby current (-6) Dynamic current (-7, -10) Dynamic current (-6) JTAG input capacitance Global clock input capacitance I/O capacitance
Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz
Min. -
Max. 100
Units A mA mA mA mA mA
10 12 10
pF pF pF
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Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise win VREF may not exceed +/- 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise win VREF may not exceed +/- 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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Parameter Low level output voltage Input leakage current I/O High-Z leakage
Test Conditions IOL = 8 mA, VCCIO = 1.7V VIN = 0 or VCCIO to 3.9V VIN = 0 or VCCIO to 3.9V
Min. 10 10
Typ -
Max. 0.4 10 10
Units V A A
Notes: 1. VREF should track the variations in VCCIO, also peak to peak ac noise win VREF may not exceed +/- 2% VREF 2. VTT of transmitting device must track VREF of receiving devices
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Maximum system frequency(2) Maximum external frequency(3) Maximum external frequency(3) Fast input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Fast input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Set-up before DataGATE latch assertion Hold to DataGATE latch assertion DataGATE recovery to new data DataGATE high pulse width CDRST setup time before falling edge GCLK2
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-6 Symbol TCDRHO TCONFIG Parameter Hold time CDRST after falling edge GCLK2 Configuration time Min. 0.0 Max. Min. 0.0
Notes: 1. FTOGGLE (1/2*TCW) is the maximum frequency of a T flip-flop with output enabled 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device with 16-bit resettable binary counter through one p-term per macrocell while FSYSTEM2 is through the OR array (one counter per function block) 3. FEXT1(1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array
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-7 Max. 2.5 2.8 1.8 2.8 2.0 2.4 3.5 0.5 0.4 0.3 0.4 0.2 2.0 0 2.8 1.6 2.0 0.5 2.0 0 2.0 0 2.0 Min. 1.4 0 1.4 0 Max. 3.1 3.4 2.4 3.8 2.7 3.0 4.3 0.6 0.5 0.4 0.5 0.4 2.2 0 3.3 2.0 3.0 0.8 3.0 0 3.0 0 3.0 Min. 1.8 0 1.8 0 -
-10 Max. 3.8 4.2 3.3 4.6 3.7 3.9 5.5 0.9 0.8 0.8 0.7 0.7 3.0 0 4.5 3.0 4.0 1.0 4.0 0 4.0 0 4.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter(1) Input buffer delay Fast data register input delay Global Clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay Control term delay Single P-term delay adder Multiple P-term delay adder Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay Feedback delay Macrocell to global OE delay Hysteresis input adder Output adder Output slew rate adder Standard input adder Hysteresis input adder Output adder Output slew rate adder
TCT TLOGI1 TLOGI2 TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL TF TOEM THYS15 TOUT15 TSLEW15 TIN18 THYS18 TOUT18 TSLEW
Macrocell Delay
Feedback Delays
10
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-7 Max. 0.5 1.5 1.5 2.0 0.7 1.0 1.0 2.0 1.5 0 1.5 0 1.5 0 Min. -
-10 Max. 0.8 2.5 2.5 3.0 1.0 2.0 2.0 3.0 1.8 0 1.8 0 1.8 0 Min. -
Min. -
Max. 1.0 3.0 3.0 4.0 2.0 3.0 3.0 4.0 2.5 0 2.5 0 2.5 0
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Characteristics
VCC = 1.8V, 25oC
6.0
5.8
TPD_PAL (ns)
5.6
4.4
4.2
4.0 1 2 4 8 12 16
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Pin Descriptions
Function Block Macrocell TQ144 PQ208 FT256 FG324 I/O Bank
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
B3 B4 C4 A2 C5 A3 E7 D3 C3 E3 B2 D4 A1 D2 C2 E5 B1
C3 A1 A2 B3 C4 B4 C5 B5 A3 A4 D3 B2 B1 C2 C1 D2 F4 E2 E1 F2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A4 C6 B5 D6 A5 E8 B6 C7 A6 E4 C1 E2 F2 E6 F3 D1 G4 E1 G3
D6 A5 C6 B6 A6 D7 C7 B7 A7 D8 G4 G3 G2 G1 H4 H3 H2 H1 J3 J2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
12
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5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D7 B7 E9 A7 D8 B8 C8 A8 E11 E10 G2 F5 F1 K1 H2 H4 G1 H3 H1 H5
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
35 34 33 32 31 30 38 39 40 41 42 43
51 50 49 48 47 46 45 44 43 54 55 56 57 58 60 61 -
P2 N3 R1 N4 N2 M3 P1 M4 M2 L3 P4 P5 R2 T1 T2 N5 R4 M5
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
28 -26 25 44 45 46 48 49 50
41 40 39 38 37 36 35 34 32 62 63 64 65 66 67 69 70 71
N1 L4 M1 L5 K4 L2 K3 L1 R5 R6 N6 R3 M6 T3 P6
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 51 52 53 54 -
31 30 29 28 27 72 73 74 75 76 77 78
K5 K2 J4 K1 J3 J2 J5 J1 T4 P7 T5 N7 R7 M7 T6
R3 R2 R1 P4 P3 P2 P1 N3 N2 N1 AA9 AB9 W10 Y10 AA10 AB10 AB11 W11 AA11 Y11
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
14
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13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
112 113 114 115 111 110 107 106 105 104 -
160 161 162 163 164 159 158 155 154 153 152 151 150
B16 G11 C14 B15 A16 B13 B14 C13 A15 C12 D14 C15 G12 D15 E14 C16 F14 D16 F13 E15
C21 C20 B22 B21 A22 A21 B20 C19 B19 C18 D19 D20 C22 D21 D22 E20 F19 E21 E22 F20
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
165 166 167 168 169 170 171 149 148 147 146 145 144 143
B12 D13 A14 E13 A13 C11 A12 B11 D11 A11 G13 F15 G14 E16 H12 F16 H16 -
B18 A19 D17 A18 C17 B17 D16 C16 B16 D15 F21 F22 G19 G20 G21 G22 H19 H21 H22 J19
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
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17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
173 174 175 178 179 180 182 142 140 139 138 137 136 135 134 -
D10 B10 E12 F12 B9 C9 C10 A9 D9 G15 H13 G16 H14 H15 J12 K12 J16
C15 B15 D14 B14 C13 A13 D12 C12 B11 A10 J20 J21 J22 K19 K20 K21 K22 L19 L20 L21
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
74 75 76 77 78 79 71 70 69 68 66 64 -
103 106 107 108 109 110 111 112 113 102 101 100 99 97 95 -
P13 P14 P15 R15 T16 N14 R16 N15 M15 M13 R13 N13 R14 T15 R12 T14 N11 P11 M11 T13
AA22 Y20 Y21 W20 W21 Y22 W22 V20 V21 U19 AB22 AA21 AB21 W19 AA20 Y18 AA19 Y17 AA18 AB18
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
16
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21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
80 81 82 83 61 60 59 -
114 115 116 117 118 119 120 121 122 123 91 90 89 88 87 86 85 -
P16 N16 L14 M14 L15 L13 M12 M16 K14 N10 T12 P10 T11 R10 M10 T10 M9 R9 P9
V22 U20 U21 U22 T19 T20 T21 T22 R21 R22 AA17 AB17 Y16 AA16 AB16 W15 Y15 AA15 AB15 W14
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
85 86 87 88 91 92 58 57 56 -
P20 P21 N19 N21 N22 M22 M19 M20 M21 L22 Y14 AA14 AB14 Y13 AA13 AB13 W12 Y12 AA12 AB12
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable.
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17
No connects
118
173
18
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Ordering Information
JC Pin/Ball JA Spacing (C/Watt) (C/Watt) 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 0.5mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 1.0mm 0.5mm 0.5mm 1.0mm 1.0mm 34.1 34.1 34.1 36.1 36.1 36.1 33.5 33.5 33.5 39.3 39.3 39.3 34.1 36.1 33.5 39.3 6.5 6.5 6.5 8.4 8.4 8.4 5.5 5.5 5.5 5.3 5.3 5.3 6.5 8.4 5.5 5.3 Package Dimensions 20mm x 20mm 20mm x 20mm 20mm x 20mm 28mm x 28mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 17mm x 17mm 17mm x 17mm 23mm x 23mm 23mm x 23mm 23mm x 23mm 28mm x 28mm 28mm x 28mm 17mm x 17mm 23mm x 23mm Commercial (C) I/O 118 118 118 173 173 173 212 212 212 240 240 240 118 173 212 240 Industrial (I) C C C C C C C C C C C C I I I I
Part Number XC2C384-6TQ144C XC2C384-7TQ144C XC2C384-10TQ144C XC2C384-6PQ208C XC2C384-7PQ208C XC2C384-10PQ208C XC2C384-6FT256C XC2C384-7FT256C XC2C384-10FT256C XC2C384-6FG324C XC2C384-7FG324C XC2C384-10FG324C XC2C384-10TQ144I XC2C384-10PQ208I XC2C384-10FT256I XC2C384-10FG324I
Package Type Thin Quad Flat Pack Thin Quad Flat Pack Thin Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch Thin BGA Fine Pitch BGA Fine Pitch BGA Fine Pitch BGA Plastic Quad Flat Pack Plastic Quad Flat Pack Fine Pitch Thin BGA Fine Pitch BGA
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VCC I/O(1) I/O(1) I/O I/O(1) I/O(1) I/O VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VCCIO1 I/O GND I/O(2) I/O I/O(2) I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4
GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO3 I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1
20
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VCCIO1 I/O I/O I/O I/O I/O I/O GND TDI I/O TMS I/O TCK I/O I/O I/O I/O GND
VCC I/O(2) I/O(5) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
VCC I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O I/O(1) I/O VAUX I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCCIO2 I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O(2) I/O I/O(2) I/O I/O I/O I/O I/O(4) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
I/O GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4 I/O I/O I/O GND TDO I/O I/O I/O VCCIO4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO4
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
VCC I/O I/O(2) I/O I/O I/O(5) VCCIO1 I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3 GND TDI I/O TMS I/O TCK I/O I/O I/O I/O I/O GND
GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO4 VCCIO3 I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO3
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
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16
15
14
13
12
11
10
2
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O I/O(4) I/O I/O(5)
A B C D E F G H J K L M N P R T
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(3)
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O(1)
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(1)
I/O
I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO4
GND
GND
GND
GND VCCIO2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O
I/O
I/O
I/O
I/O
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O(2)
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
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I/O(3) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O(4)
A B C D E F G H J K L M N P R T U V W Y AA AB
I/O
I/O
VCC
I/O
I/O
N/C
N/C
N/C
N/C
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(1) I/O(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O(1)
NC
I/O
I/O
I/O
GND
GND
VCC
I/O(1)
I/O
I/O
I/O
I/O
I/O
NC
VAUX
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
N/C N/C
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
VCCIO4
VCCIO2 VCCIO2
I/O
I/O
I/O
I/O
VCCIO4
GND
GND
GND
GND
N/C
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
N/C N/C
I/O I/O
I/O I/O
I/O
I/O
VCC
I/O
VCCIO3
GND
GND
GND
GND VCCIO1
N/C
I/O
I/O
NC
GND
I/O
I/O
I/O
I/O
I/O
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O(2)
I/O
I/O
I/O
I/O
I/O
GND
N/C
I/O
I/O
N/C
I/O
I/O
N/C
I/O
I/O
GND
I/O
NC
I/O
I/O
I/O
I/O
TCK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O(2)
I/O I/O
I/O I/O
I/O TMS
I/O TDI
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O I/O
I/O(5) I/O
I/O I/O
VCC I/O(2)
I/O NC
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable
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Revision History
The following table shows the revision history for this document. Date 05/31/02 08/20/02 Version 1.0 1.1 Initial Xilinx release. Minor Changes Revision
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