Space Vector PWM as a Modified Form of Sine-Triangle PWM for Simple Analog or Digital Implementation

Authors: 1. P. Srikant Varma (Non- member) Department of Electrical Engineering, Indian Institute of Science, Bangalore 560 012. Ph: 91- 80 2293 2932 Fax: 91 80 2360 0444 Email: contact_varma@rediffmail.com 2. G. Narayanan (Non- member) (Corresponding author) Department of Electrical Engineering, Indian Institute of Science, Bangalore 560 012. Ph: 91- 80 2293 2930 Fax: 91 80 2360 0444 Email: gnar@ee.iisc.ernet.in

Abstract Conventional space vector PWM (CSVPWM) has the advantages of yielding up to 15% higher fundamental line-side voltage fo r a given DC bus voltage and also less harmonic distortion in line currents over sine-triangle PWM (SPWM). However, no analog implementation of CSVPWM is possible in its traditional form. Digital implementation of CSVPWM is also more complex than that of SPWM. This paper analyses the two techniques. The analysis establishes that CSVPWM can be viewed as a modified form of SPWM, and leads to a simple method to implement CSVPWM. The simplified method does not require evaluation of trigonometric functions, look-up tables, sector identification etc. An existing line of products employing SPWM can easily be upgraded to exploit the benefits of CSVPWM. The work serves to unify the understanding of triangle-comparison based PWM and space vector based PWM techniques. The work is of tutorial value to students and engineers.

Key words: inverters, motor drives, pulsewidth modulation, sine-triangle PWM, space vector PWM

Space Vector PWM as a Modified Form of Sine-Triangle PWM for Simple Analog or Digital Implementation
Abstract Conventional space vector PWM (CSVPWM) has the advantages of yielding up to 15% higher fundamental line-side voltage for a given DC bus voltage and also less harmonic distortion in line currents over sine-triangle PWM (SPWM). However, no analog implementation of CSVPWM is possible in its traditional form. Digital implementation of CSVPWM is also more complex than that of SPWM. This paper analyses the two techniques. The analysis establishes that CSVPWM can be viewed as a modified form of SPWM, and leads to a simple method to implement CSVPWM. The simplified method does not require evaluation of trigonometric functions, look-up tables, sector identification etc. An existing line of products employing SPWM can easily be upgraded to exploit the benefits of CSVPWM. The work serves to unify the understanding of triangle-comparison based PWM and space vector based PWM techniques. The work is of tutorial value to students and engineers. Key words: inverters, motor drives, pulsewidth modulation, sine-triangle PWM, space vector PWM

1. Introduction Three-phase voltage source inverters (VSI) are widely used in applications such as AC motor drives, uninterruptible power supplies (UPS), line-side converters with power factor compensation and active power filters. VSI is a three-phase bridge consisting of six active switches as shown in Fig. 1. Fig. 2 shows the block diagram of a VSI-based power electronic system such as motor drive, three-phase AC/DC converter with power factor compensation or UPS. The modulator produces the gating signals for the devices in the inverter on the basis of the voltage reference provided by the controller. Several pulsewidth modulation (PWM) techniques have been reported for the generation of such gating signals, and thereby, to control the line-side voltage for a given DC bus voltage VDC [1-10]. The choice of the PWM technique strongly influences the quality of line-side current and voltage waveforms [1-13]. It also affects the switching losses in the inverter [1-3,7,10]. Of the existing real- time PWM techniques, sine-triangle PWM (SPWM) and conventional space vector PWM (CSVPWM) are very popular and important [1-2]. Compared to SPWM, CSVPWM yields 15% higher line-side voltage for a given DC bus voltage. Conversely, for a given maximum line-side voltage, CSVPWM requires less DC bus voltage. Consequently, the voltage stress on the semiconductor devices is less. Further, CSVPWM results in reduced harmonic distortion in the line currents over SPWM, particularly at higher modulation indices [1-2]. However, while SPWM can easily be implemented either by digital or analog means, no analog implementation is possible with CSVPWM in its traditional form. The

digital implementation of CSVPWM is also more complex than that of SPWM since the former requires evaluation of trigonometric functions and a host of other tasks (as will be discussed in section 2). Also, space vector PWM is, arguably, not so well understood by power electronics engineers as sine-triangle PWM. This paper strives for a clearer understanding and easier implementation of CSVPWM so as to exploit the benefits of this technique. SPWM has its basis in modulation theory of communication engineering. CSVPWM is based on space vector theory, which can be said to have its origin in the generalized theory of electric machines. As algorithms, the two PWM techniques are very different. Despite these differences, the PWM waveforms generated by the two techniques have striking similarities as will be brought out in the later sections. Comparative studies on SPWM and CSVPWM techniques have been reported in numerous papers [4-8]. This paper presents a simpler and lucid analysis that brings out the similarities and dissimilarities between the two techniques. The paper establishes that CSVPWM can be viewed as a modified form of SPWM. The present work goes on to derive a simple method of calculation for generating PWM waveforms identical to those produced by CSVPWM technique.

2. Conventional space vector PWM Three-phase voltages (or currents) can be transformed into voltage space vectors (or current space vectors) using the space vector transformation, defined in (1). The axes three-phase axes and the two-phase axes (a-axis and b-axis) are illustrated in Fig. 3a.

va = 3vRN / 2 vb = 3(vYN vBN ) / 2 VS = va + jvb ...(1)

2.1. Switching states and voltage vectors Every leg of the VSI is a Single Pole Double Throw (SPDT) switch with the top and bottom devices switching in a complementary fashion. When the top device is ON, the pole voltage, measured with respect to the DC bus neutral, is +0.5VDC. When the bottom device is ON, the pole voltage is -0.5VDC. With three such legs there are 23 or eight possible switching states as shown in Fig. 3b. For each switching state the three-phase pole voltages ( v RO ,v YO ,v BO ) are uniquely defined. Equation (2) gives the corresponding line- line voltages. Assuming a three-phase balanced star-connected load, the corresponding line-neutral voltages applied are as in (3). The space vector can now be expressed in terms of three-phase pole voltages as given in (4). v RY = v RO v YO ; v YB = vYO vBO ; vBR = vBO vRO v RN = ( vRY vBR )/3; vYN = ( vYB vRY )/3; vBN = ( v BR vYB ) / 3 ...(2) ...(3)

v a = 3vRN / 2 = (2v RO vYO v BO ) / 2 vb = 3( vYN vBN ) / 2 = 3( vYO v BO ) / 2 ...(4)

The eight inverter states and the corresponding three-phase voltages are tabulated in Table I. The corresponding voltage vectors are also listed both in rectangular as well as polar coordinates.

When all the top devices are ON or all the bottom devices are ON, the three-phase load is shorted by the inverter. There is no transfer of power between the DC bus and the three-phase load. These two states are termed as the zero states of the inverter. The two zero states lead to a voltage vector of zero magnitude as shown in Fig. 3b. The other six states of the inverter are termed as active states, which lead to six active vectors of equal magnitude VDC. Fig. 3b shows the vectors with their magnitudes normalized with respect to VDC. The active vectors divide the space vector plane into six sectors of angle 600 as shown. 2.2. Reference vector The space vector approach to PWM involves the use of a voltage space vector as reference instead of three-phase modulating waves. At steady state, the voltage reference vector has a constant magnitude (VREF) and revolves with a constant frequency (f 1 ) in the anti-clockwise direction for phase sequence RYB. The line-side fundamental voltage is proportional to VREF. The fundamental frequency of the line-side voltage is same as f 1 . 2.3. Calculation of dwell times and switching instants The reference vector is sampled at equal intervals of time, termed as subcycle (T s). Let VREF be the sampled value of reference vector in a given subcycle. Let Vx = 1 x and
Vy = 1 y be the two active vectors closest to VREF. VREF can be expressed as the sum of

a fraction of Vx and a fraction of Vy as shown in Fig. 3c. If Vx is applied for a duration Tx in the given subcycle, Vy is applied over another interval Ty, and the zero vector for the remaining duration Tz, the average vector applied over the subcycle is given by the RHS of

(5a). If the durations Tx, Ty and Tz are appropriate, the average vector applied over the subcycle equals VREF as shown in (5). In other words, the applied volt-seconds equal the reference volt-seconds. This is referred to as volt-second balance. T Tx T + Vy y + 0 z Ts Ts Ts T T VREF = x x + y y Ts Ts VREF = V x y = x + 60o = x + ...(5a ) ...(5b) ...(5c) ...(5d )

To derive expressions for the dwell times Tx, Ty and Tz, the vectors Vx , Vy and VREF are all resolved along the direction of Vx and the direction orthogonal to it as shown in Fig. 3d. The respective components can be equated as shown in (6).

VREF sin( ) = (Ty / Ts )sin(60o ) VREF cos( )= ( y / Ts )cos(60o ) + (Tx / Ts ) T ...(6)

Alternatively, from the tip of VREF, drop a perpendicular to Vx and another perpendicular to Vy as shown in Fig. 3e. This construction yields equation (7).
VREF sin( ) = (Ty / Ts )sin(60o ) VREF sin(60o ) = (Tx / Ts )sin(60o ) ...(7)

Solving (6) yields the expressions for Tx and Ty as given in (8). These expressions are readily seen from (7).
Tx = TsVREF sin(60 o )/sin(60 o ) = TsVREF sin( y )/sin(60o ) T y = TsVREF sin( )/sin(60o ) = TsVREF sin( x )/sin(60o ) Tz = Ts Tx T y ... (8)

The zero vector can be applied either using the zero state 0 or the zero state 7. The switching instants of the three phases depend on the apportioning of Tz between 0 and 7, and the switching sequence employed. CSVPWM applies both the zero states equally for a duration 0.5Tz as shown in Fig. 3f. The sequence of inverter states is 0-1-2-7 (forward sequence) and 7-2-1-0 (reverse sequence) in alternate subcycles in sector I. The forward and reverse sequences pertaining to different sectors are shown in Table II. Corresponding to every state sequence, the sequence in which the three phases switch is also given. It may be noted that numerous other switching sequences are also possible. These are employed by certain advanced PWM techniques [9,10,13], and will be discussed in section 6. 2.4. Computational burden The CSVPWM algorithm, explained above, requires digital implementation. For every sampled reference vector, the algorithm requires identifying the sector. The active vectors to be applied and the corresponding switching sequences depend on the sector in which the sample of the reference vector falls. Even within a sector the forward and reverse sequences are to be alternated. Moreover, calculation of dwell times of the voltage vectors involves trigonometric functions, and requires look-up table. These lead to complexity in the implementation of CSVPWM in its traditional form.

3. Analysis of sine -triangle PWM Sine-triangle PWM employs three-phase sinusoidal modulating waves, illustrated in Fig. 4 and defined in (9), as voltage reference. The modulating waves are compared

against a common triangular carrier wave to determine the switching instants of the devices. The carrier wave is usually of a much higher frequency (switching frequency) than that of the modulating waves ( 1 ), and is not shown in the figure. The line-side f fundamental voltage is controlled by the ratio (Vm / Vp ) and the fundamental frequency is f1. v R = Vm cos( t ) vY = Vm cos( t 120o ) v B = Vm cos( t + 120o ) = 2 f1 3.1. Inverter state sequence in a half carrier cycle Fig. 5 illustrates the determination of switching instants in a carrier cycle in region I of the fundamental cycle (see Fig. 4), where v R > v Y > v B. At the start of the falling halfcarrier cycle, the carrier is greater than v R, v Y and vB. Hence the bottom devices are ON in all three phases. The initial inverter state is the zero state --- (0). As the carrier decreases with time, the phases switch in the sequence R-Y-B since v R > v Y > v B. This leads to the inverter state sequence ---, +--, ++-, +++ (i.e. 0-1-2-7) as shown in Fig. 5a. Similarly, the inverter state sequence in the rising half-carrier cycle, where the carrier increases from -VP to +VP, is 7-2-1-0 as illustrated in Fig. 5b. The relative values of (v R, v Y, vB) differ in the six regions of the fundamental cycle as shown in Fig. 4. Correspondingly, the sequence of switching of the three phases differs from region to region as tabulated in Table III. For any Vm < VP, the three-phase references (v R, v Y, v B) in any half-carrier cycle must be less than +VP and greater than VP. Hence in any of the six regions, the initial state ...(9)

in a falling half-carrier cycle is the zero state --- (0) as in Fig. 5a. Similarly, the initial state in a rising half-carrier cycle is +++ (7) as in Fig. 5b in any region of the fundamental cycle. Starting with an initial state of --- (0), the switching sequences in all six regions during a falling half-carrier cycle are brought in Fig. 6a. Starting with the initial state +++ (7), the switching sequences during a rising half-carrier cycle in the six regions are shown in Fig. 6b. These sequences are shown tabulated in Table III. Observe the similarity between the sequences corresponding to SPWM in Table III and those corresponding to CSVPWM in Table II. 3.2. Dwell times of zero states The dwell times of the zero states in a half-carrier cycle in SPWM can be determined using the three-phase references. The duration T0 is proportional to (VP v R), and T7 is proportional to (v B + VP) in Fig. 5. The expressions for T0 and T7 in region I are given by (10a) in Table IV. The corresponding expressions for the other five regions of the fundamental cycle are given in (10b) to (10f) in the same table. Unlike CSVPWM, T0 is not equal to T7 in a half-carrier cycle except when t = 30o , 90o , 150o , 210o , 270o , 330o . 3.3. Dwell times of active states The state sequences for the six regions of the fundamental cycle in Table III indicate the active states applied in each region with SPWM. The active vectors (Vx and Vy ) in the six regions are tabulated in Table V for convenience. The dwell times of the active vectors in a half-carrier cycle can also be determined using the three-phase references. The duration T1 is proportional to (v R v Y), and T2 is proportional to (v Y - v B) in

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Fig. 5. The expressions for Tx and Ty in the six regions are given by (11a) (11f), respectively, in Table V. The expressions for the dwell times of the two active states in a half-carrier cycle can be generalized as in (12). Observe the similarity between (12) and (8). Tx = Ts (3V m / 4VP )sin( y t )/sin(60 o ) Ty = Ts (3V m / 4VP )sin( t x )/sin(60 o ) ...(12)

3.4. Average voltage vector in a half carrier cycle The active vectors Vx and Vy are applied for durations Tx and Ty, respectively, as shown in (12) in every half-carrier cycle in SPWM. The zero vector (either 0 or 7) is applied over the remaining interval. Therefore, the average voltage vector applied over a half-carrier cycle is given by (13). VAV = T 3V sin( y t ) Tx 3V sin( t x ) x + y y = m x + m y o Ts Ts 4VP sin(60 ) 4VP sin(60o ) ...(13)

The vectorial addition in the RHS of (13) is similar to the illustration in Fig. 3c. The resultant vector has its magnitude and angle as shown in (14). VAV = 3Vm /(4VP ); = t ...(14)

The average voltage vector generated in every half-carrier cycle over a fundamental cycle in SPWM is illustrated in Fig. 7. The magnitude remains constant if (Vm /VP) i s unchanged, i.e. at steady state. The angle of the average vector changes in steps of Ts as shown. Thus, in numerous respects, SPWM can be viewed as CSVPWM with VREF = 0.75Vm /VP and subcycle duration equal to half-carrier cycle.

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The fundamental voltages are equal for SPWM with a given Vm /VP and CSVPWM with VREF = 0.75Vm /VP. The six regions of the fundamental cycle in SPWM (see Fig. 4) correspond to the six sectors in the space vector plane (see Fig. 3b). The fundamental angle t in the former corresponds to the position of the fundamental voltage vector in the latter. The same state sequence is applied in a given half-carrier cycle / subcycle in both the techniques. The dwell times of active vectors (Tx and Ty) and total zero vector time (T z) are also equal. However, Tz is equally divided between 0 and 7 in CSVPWM, while the division is unequal in SPWM. The difference in the apportioning of Tz between 0 and 7 causes the line voltage waveforms produced by the two techniques to differ. The difference between the two waveforms is only in the harmonic content.

4. Simplified method This section attempts at modification of SPWM such that the waveforms generated by the modified technique are identical to those generated by CSVPWM. 4.1. Equal division of zero vector time The highest of the three-phase references ( v R , v Y , v B ) in a given half- carrier cycle is designated as v MAX , the lowest one as vMIN , and the middle-valued one as vMID . An offset voltage or a common- mode component ( vOFF ) may be added to the three-phase modulating waves as shown in (15a) subject to the constraints in (15b).

( v * , v* , v* ) = ( vMAX , v MID , vMIN ) + ( vOFF , vOFF , vOFF ) MAX MID MIN v * VP ; MAX
* v MIN ( VP )

...(15a ) ...(15b )

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If the modified voltage references ( v * , v * , v * ) are used for determining the MAX MID MIN switching instants instead of ( v MAX , v MID , v MIN ) , the active vector times are unchanged since
* ( v * vMID ) = ( v MAX v MID ) and ( v * v * ) = ( v MID v MIN ) . However, T0 and T7 are MAX MID MIN

changed as shown in (16). The condition for T0 = T7 is derived as shown in (17).

T0 = Ts (VP v* )/(2VP ) MAX

* T7 = Ts (vMIN + VP )/(2VP )
* (VP v * ) = (v MIN ( VP )) MAX * v* + vMIN = 0 MAX

...(16)

vMAX + vMIN + 2vOFF = 0 vOFF = 0.5( v MAX + v MIN ) = 0.5v MID

...(17)

The variation of the offset voltage over the entire fundamental cycle is shown in Fig. 8a. The common- mode component appears almost like a triangular wave of peak 0.25Vm and frequency 3f 1 as shown in Fig. 8a. The common-mode wave contains only triplen harmonics. Addition of this offset voltage to the R-phase modulating wave results in the modified modulating wave for R-phase shown in Fig. 8a. Comparison of such threephase modified modulating waves against a common triangular carrier produces PWM waveforms identical to those produced by CSVPWM using the procedure detailed in section 2. In other words, CSVPWM can be viewed as such a modified form of SPWM, and can be implemented as such in a simpler fashion. 4.2. Implementation The offset voltage required by the simplified form of CSVPWM can be derived from the three-phase references themselves as shown in Fig. 8b.

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In case of digital implementation, the three-phase modulating waves are sampled, usually once in every carrier cycle or half-carrier cycle. The offset voltage is calculated as shown in (18a). The modified voltage references are obtained as shown in (18b). The switching instants in the given half- carrier cycle are determined using the modified references ( v * [n ], v * [n], v* [ n]) . R Y B
vOFF [ n] = 0.5( vMAX [ n ] + v MIN [ n ]) = 0.5vMID[ n ] ( v [n ], v [n ], v [ n ]) = ( vR [n ], vY [ n ], vB [ n ]) + ( vOFF [ n], vOFF [ n], vOFF [n ])
* R * Y * B

...(18a ) ...(18b )

The simplified method makes analog implementation of CSVPWM possible. Given three-phase modulating waves, v MAX can be obtained using three diodes with cathodes connected together as shown in Fig. 8c. Similarly, v MIN can be obtained using three diodes with anodes connected together as shown. The common- mode component is obtained using v MAX and v MIN as shown in (19a). The modified references ( v * (t ), v* ( t ), v* ( t)) are R Y B obtained as shown in (19b), and are used to determine the switching instants of the three phases.
vOFF (t ) = 0.5( v MAX ( t ) + vMIN ( t )) = 0.5vMID (t ) ( v (t ), v (t ), v ( t )) = ( v R (t ), v Y (t ), vB (t )) + ( vOFF ( t ), vOFF ( t ), vOFF (t ))
* R * Y * B

...(19a ) ...(19b )

4.3. Experimental results CSVPWM has been implemented digitally in its simplified form on a laboratory prototype. The prototype is a 550W, 220V, 50Hz, three-phase induction motor drive fed from an IGBT-based inverter. The controller platform is built around TMS320C50 DSP processor. Experimental results, namely modulating wave, no-load current waveform and

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its harmonic spectrum, corresponding to SPWM are shown in Figs. 9a 9c, respectively. Corresponding results for CSVPWM in its simplified form are presented in Figs. 9d 9f.

5. Superior performance of CSVPWM The reasons for higher DC bus utilization and reduced harmonic distortion due to CSVPWM over SPWM are brought out in this section. 5.1. DC bus utilization For a given DC bus voltage, the highest line-side fundamental voltage is obtained with CSVPWM when VREF = 0.866, i.e. when VREF equals the radius of the largest circle that can be inscribed inside the hexagon joining the tips of the six active vectors in the space vector plane as shown in Fig. 10. As far as the line-side fundamental voltage is considered, SPWM is equivalent to CSVPWM with VREF = 0.75Vm /VP as brought out in section 3. When Vm = VP , the magnitude of equivalent reference vector is 0.75 as shown in Fig. 10. Thus, the highest line-side voltage obtained with SPWM is only 0.866 times (i.e. 0.75/0.866 times) of that obtained with CSVPWM. The difference in DC bus utilization can be seen from the three-phase references as well. ( v MAX , v MID , v MIN ) are defined as given in (20). The expression for v * is given in (21). MAX
(v MAX , v MID , v MIN ) = (Vm cos( ), Vm cos( 120o ), Vm cos( +120o )), 0o 60 o , sector = I , III ,V = (Vm cos( 60 o ), Vm cos( + 60 o ), Vm cos( 180 o )), 0o 60 o , sector = II , IV ,VI ... (20)

v * = v MAX + 0.5vMID = ( 3 / 2 )Vm cos( 30o ), MAX

0o 60o

...(21)

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The peak value of v * occurs at = 30o , and is equal to ( 3/2)Vm . The highest MAX line-side fundamental voltage is obtained, when the peak value of v * equals VP, i.e. when MAX

Vm = (2VP )/ 3 . Thus, the highest possible value of Vm is now 1.15 times VP.
Consequently, the highest line-side voltage is 15% higher than that with SPWM. 5.2. Total harmonic distortion In every half-carrier cycle or subcycle, there is an instantaneous error between the applied voltage vector and the average voltage vector or the reference vector. This voltage error is responsible for the harmonics in the line current. The time integral of the error voltage vector is termed as stator flux ripple vector. This quantity is a measure of the ripple in the line currents [9]. The trajectory of the tip of the stator flux ripple vector corresponding to CSVPWM in a given subcycle is shown in solid lines in Fig. 11a. The trajectory corresponding to SPWM in the same subcycle is shown in dashed lines in the same figure. The flux ripple vector is considered in a synchronously revolving d-q reference frame. The d-axis and qaxis components of the ripple vector are shown in Fig. 11b. The quantities Qz, Q1 , Q2 and D in Fig. 11b are defined in (22).

Qz = VREFTz Q1 = (cos( ) VREF )T1 Q2 = (cos(60o ) VREF )T2 D = sin( )T1 = sin(60o )T2 ...(22)

The d-axis ripple corresponding to SPWM and CSVPWM are equal - both in terms of peak value as well as RMS value. However, the peak q-axis ripple is higher for SPWM due to unequal division of Tz as shown. The RMS q-axis ripple is also higher. Hence the

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RMS current ripple over a subcycle is higher for SPWM. Consequently, the RMS current ripple over a fundamental cycle is higher for SPWM. Therefore, SPWM results in a higher total harmonic distortion (THD) over CSVPWM at a given fundamental voltage as shown in Fig. 11c.

6. Discussion CSVPWM employs sequences ( -1-2-7, 7-2-1-0, ) in sector I. Every phase 0 switches once in a subcycle with these sequences. CSVPWM can be seen as a modified form of SPWM. Certain advanced PWM techniq ues employ sequences such as (0-1-2-1, 12-1-0, ), ( 7-2-1-2, 2-1-2-7, ), ( 1-0-1-2, 2-1-0-1, ) and ( 2-7-2-1, 1-2-7-2, ) in sector I [10]. With these sequences one of the phases switches twice, another phase switches once, while the third phase remains clamped in a subcycle. When such sequences where a phase switches more than once in a subcycle are employed, the space vector based technique cannot be viewed as a modified form of SPWM [9,13]. The implementation of these techniques cannot be simplified to such extent as possible with CSVPWM. However, the dwell times of active vectors can still be calculated using the differences between the three-phase voltage references in the given subcycle, namely

( v MAX vMID ) and

( vMID v MIN ) . This results in a substantial reduction in computational effort as evaluation of trigonometric functions is not required for calculation of dwell times.

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7. Conclusion Sine-triangle PWM (SPWM) is analyzed from a space vector perspective. The analysis brings out the similarities and dissimilarities between SPWM and conventional space vector PWM (CSVPWM). The reasons for higher DC bus utilization and lower harmonic distortion with CSVPWM over SPWM are explained. The study further leads to a simplified method for implementing CSVPWM, which can be viewed as a modified form of SPWM. The simplified form does not require evaluation of trigonometric functions, sector identification and tracking of forward / reverse sequences unlike the traditional form. Further the simplified form of CSVPWM is amenable to both analog and digital implementation, while only digital implementation is possible with the traditional form. An existing product or a line of products such as three-phase UPS or three-phase AC drives, employing SPWM, can easily be upgraded into ones modulated using CSVPWM. This requires only a few additional components in case of analog control. In case of microprocessor / microcontroller / DSP based products, a few additional lines of code would suffice. The benefits of CSVPWM can hereby be harnessed easily. Apart from its practical significance, the study presented is useful in unifying the understanding of triangle-comparison based PWM techniques and that of space vector based PWM techniques. The analysis presented here has successfully been used in a postgraduate course on power electronics covering PWM techniques.

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References [1] J.Holtz, Pulsewidth modulation a survey, IEEE Trans. IE, vol. 39(5), pp. 410-420, Dec 1992. [2] J.Holtz, Pulsewidth modulation for electronic power conversion, Proc. IEEE, vol. 82(8), pp. 1194-1214, 1994. [3] J.Kolar, F.C.Zach and H.Ertl, Influence of the modulation method on conduction and switching losses of a PWM converter system, IEEE Trans. IA, vol. 27(6), pp. 1063-1075, 1991. [4] D.G.Holmes, The significance of zero space vector placement for carrier-based PWM schemes, IEEE Trans. IA, vol. 32(5), pp. 1122-1129, 1996. [5] V.Blasko, Analysis of a hybrid PWM based on modified space- vector and trianglecomparison methods, IEEE Trans. IA, vol. 33(3), pp. 756-764, 1997. [6] D-W. Chung, J-S. Kim and S-K. Sul, Unified voltage modulation technique for realtime three-phase power conversion, IEEE Trans. IA, Vol. 34(2), pp. 374-380, 1998. [7] A.M.Hava, R.J.Kerkman and T.A.Lipo, Simple analytical and graphical methods for carrier-based PWM-VSI drives, IEEE Trans. PE, vol. 14(1), pp. 49-61, Jan 1999. [8] K. Zhou and D.Wang, Relationship between space- vector modulation and three-phase carrier-based PWM: A comprehensive analysis, IEEE Trans. IE, vol. 49(1), pp. 186-196, Feb 2002. [9] G.Narayanan, Synchronised pulsewidth modulation strategies based on space vector approach for induction motor drives, Ph.D. Thesis, Indian Institute of Science, August 1999.

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[10] Di Zhao, G.Narayanan and R.Ayyanar, Switching loss characteristics of sequences involving active state division in space vector based PWM, Proc. IEEE-APEC 2004, pp. 479-485, 2004. [11] H.W.van der Broeck Analysis of the harmonics in voltage fed inverter drives caused by PWM schemes with discontinuous switching operation, Proc. EPE 91, Firenze, Italy, 1991, pp. 261-266. [12] S.Fukuda and K.Suzuki, Harmonic evaluation of two- level carrier-based PWM methods, Proc. EPE 97, Trondheim, 1997, pp. 331-336. [13] G.Narayanan and V.T.Ranganathan, Triangle comparison and space vector approaches to pulsewidth modulation in inverter- fed drives, J. Indian Institute of Science, vol. 80, pp. 409-427, Sep.-Oct. 2000.

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Figure captions and subcaptions Fig. 1. Voltage source inverter Fig. 2. Block diagram of a voltage source inverter based power electronic system Fig. 3. Conventional space vector PWM (a) Space vector transformation (b) Switching states and voltage vectors produced by a VSI. Magnitudes of vectors are normalized with respect to VDC. I, II, III, IV, V and VI are sectors. (c) Volt-second balance (d) Derivation of expressions for dwell times method I (e) Derivation of expressions for dwell times method II (f) Switching pattern of the three phases in sector I for forward and reverse sequences Fig. 4. Three-phase sinusoidal modulating waves Fig. 5. Switching instants and inverter states in a half- carrier cycle in SPWM (a) Half-carrier cycle from positive peak to negative peak (b) Half-carrier cycle from negative peak to positive peak (Pole voltages are normalized with respect to VDC) Fig. 6. Switching sequences for different relative values of (v R, v Y, v B) (a) Half-carrier cycle from positive peak to negative peak (b) Half-carrier cycle from negative peak to positive peak Fig. 7. Average voltage vectors applied in half-carrier cycles over a fundamental cycle in SPWM Fig. 8. Simplified form of CSVPWM

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(a) CSVPWM as a modified form of SPWM (b) Algorithm for generation of modified modulating waves [7] (c) Analog circuit for generating v MAX and v MIN [6] Fig. 9. Experimental results obtained on a 0.55kW, 220V, 50Hz induction motor at a fundamental frequency of 40Hz and fundamental line voltage of 176V. (a) Modulating wave, (b) no- load current waveform and (c) its harmonic spectrum for SPWM. (d) Modulating wave, (e) no- load current waveform and (f) its harmonic spectrum for CSVPWM in its simplified form. Fig. 10. Space vector diagram with hatched area indicating the additional linear region provided by CSVPWM Fig. 11. Comparison of current ripple due to CSVPWM and SPWM (a) Current ripple vector over a subcycle (b) Current ripple along q-axis and d-axis over a subcycle (c) THD versus VREF

List of tables Table I. Switching states and voltage vectors Table II. Forward and reverse sequences in six sectors Table III. Switching sequence of phases and corresponding state sequence in SPWM Table IV. Dwell times of zero states in SPWM Table V. Active vectors and their dwell times in SPWM

22

TABLE I. SWITCHING STATES AND VOLTAGE VECTORS

States - - - (0) + - - (1) + + - (2) - + - (3) - + + (4) - - + (5) + - + (6) + + + (7) (vRO , vYO, vBO ) (vRY , vYB, v BR) (vRN , vYN, vBN ) (-VDC/2, -VDC /2, -VDC/2) (0, 0, 0) (0, 0, 0) (VDC/2, -VDC /2, -VDC/2) (VDC, 0, -VDC) (2VDC/3, -VDC /3, -VDC/3) (VDC/2, VDC /2, -VDC/2) (0,VDC, -VDC) (VDC/3, VDC /3, -2VDC/3) (-VDC/2, VDC /2, -VDC/2) (-VDC/2, VDC /2, VDC/2) (-VDC/2, -VDC /2, VDC/2) (VDC/2, -VDC /2, VDC/2) (VDC/2, VDC /2, VDC/2) (-VDC, VDC, 0) (-VDC/3, 2VDC /3, -VDC/3) (-VDC, 0, VDC) (-2VDC/3, VDC /3, VDC/3) (0, -VDC, VDC) (-VDC/3, -VDC /3, 2VDC/3) (VDC, -VDC, 0) (0, 0, 0) (VDC/3, -2VDC /3, VDC/3) (0, 0, 0)

(va, vb )
(0, 0) (VDC, 0) (VDC/2,

3 VDC/2)

Vs 0 VDC 00 VDC 600 VDC 1200 VDC 1800 VDC 2400 VDC 3000 0

(-VDC/2, 3 VDC/2) (-VDC, 0) (-VDC/2, - 3 VDC/2) (VDC/2, - 3 VDC/2) (0, 0)

TABLE II. FORWARD AND REVERSE SEQUENCES IN SIX SECTORS Sector No. I II III IV V VI Forward sequence 0-1-2-7 7-2-3-0 0-3-4-7 7-4-5-0 0-5-6-7 7-6-1-0 Reverse sequence 7-2-1-0 0-3-2-7 7-4-3-0 0-5-4-7 7-6-5-0 0-1-6-7 Switching sequence of phases for forward sequence R-Y-B B-R-Y Y-B-R R-Y-B B-R-Y Y-B-R Switching sequence of phases for reverse sequence B-Y-R Y-R-B R-B-Y B-Y-R Y-R-B R-B-Y

23

TABLE III SWITCHING SEQUENCE OF PHASES AND CORRESPONDING STATE SEQUENCE IN SPWM
Switching Switching State State Relative sequence of phases sequence of phases sequence in a sequence in a values of in a falling halfin a rising halffalling halfrising half(vR , vY, vB ) carrier cycle carrier cycle carrier cycle carrier cycle vR > vY > vB vY > vR > vB vY > vB > vR vB > vY > vR vB > vR > vY vR > vB > vY R-Y-B Y-R-B Y-B-R B-Y-R B-R-Y R-B-Y B-Y-R B-R-Y R-B-Y R-Y-B Y-R-B Y-B-R 0-1-2-7 0-3-2-7 0-3-4-7 0-5-4-7 0-5-6-7 0-1-6-7 7-2-1-0 7-2-3-0 7-4-3-0 7-4-5-0 7-6-5-0 7-6-1-0

Region
I II III IV V VI

Range of t
0o < t < 60o 60o < t < 120o 120o < t < 180o 180o < t < 240o 240o < t < 300o 300o < t < 360o

TABLE IV DWELL TIMES OF ZERO STATES IN SPWM Region

I

Range of t
0o < t < 60o 60o < t < 120o 120o < t < 180o 180o < t < 240o 240o < t < 300o 300o < t < 360o

Relative values of (vR , vY, vB )

vR > vY > vB

Expressions for T0 and T7

T0 =TS (VP vR )/(2 P ) =TS (VP Vm cos(t))/(2V ) V P T7 =TS (vB +VP )/(2 P ) =TS (VP +Vm cos(t +120o ))/(2V ) V P ...(10a)

II

vY > vR > vB

T0 =TS (VP vY )/(2VP ) =TS (VP Vm cos(t 120o ))/(2 P ) V

o T7 =TS ( v +VP )/(2 P ) =TS (VP +Vm cos(t +120))/(2 P ) V V B

...(10b)

III

vY > vB > vR

T0 =TS (VP vY )/(2 P ) =TS (VP Vm cos(t 120o ))/(2 P ) V V T7 =TS (vR +VP )/(2 P ) =TS (VP +Vm cos(t))/(2VP ) V T0 =TS (VP vB )/(2 P ) =TS (VP Vm cos(t +120o ))/(2V ) V P T7 =TS (vR +VP )/(2 P ) =TS (VP +Vm cos(t))/(2VP ) V
o T0 =TS (VP vB )/(2V ) =TS (VP Vm cos(t +120))/(2V ) P P o T7 =TS ( v +VP )/(2 P ) =TS (VP +Vm cos(t 120))/(2V ) V Y P

...(10c)

IV

vB > vY > vR

...(10d)

vB > vR > vY

...(10) e

VI

vR > vB > vY

T0 =TS (VP vR )/(2 P ) =TS (VP Vm cos(t))/(2V ) V P T7 =TS (vY +VP )/(2 P ) =TS (VP +Vm cos(t 120o ))/(2V ) V P ...(10 f )

24

TABLE V ACTIVE VECTORS AND THEIR DWELL TIMES IN SPWM Relative Range of t values of (vR , vY, vB )
0o < t < 60o v R > v Y > v B 60o < t < 120o

Active vector Vx = 1 x
V1 = 10o
V2 = 160 o

Active vector Vy = 1 y
V2 = 1 60o
V3 = 1120 o V4 = 1180 o V5 = 1 240 o

Expressions for Tx and Ty

o T1 =TS ( vR vY )/(2 P )= TS (3 m/4VP )sin(60o t)/sin(60) V V o T2 =TS ( v vB)/(2 P ) = TS (3 m/4VP )sin(t)/sin(60) V V Y o T2 =TS ( v vB)/(2 P ) = TS (3 m/4VP )sin(120o t)/sin(60) V V R o o T3 = TS (vY vR )/(2V ) =TS (3Vm /4 P)sin(t 60)/sin(60) V P o T3 = TS (vY vB )/(2V ) =TS (3Vm /4 P)sin(180o t)/sin(60) V P o o T4 =TS ( v vR)/(2 P ) = TS (3 m/4VP )sin(t 120)/sin(60) ...(11) V V c B o T4 =TS ( v vR)/(2 P ) = TS (3 m/4VP )sin(240o t )/sin(60) V V Y o o T5 = TS (v BvY )/(2 P ) = T (3V /4 P)sin(t 180)/sin(60) ...(11d) V S m V o T5 = TS (v BvR )/(2 P) = T (3 m /4VP )sin(300o t)/sin(60) V S V o o T6 =TS ( vRvY )/(2 P) = T (3 m /4VP )sin(t 240)/sin(60) ...(11) V e S V o T6 =TS ( vBvY )/(2 P) = T (3 m /4VP )sin(360o t)/sin(60) V S V o o T1 =TS ( v vB )/(2 P ) =TS (3 m/4VP )sin(t 300)/sin(60) ...(11f ) V V R

...(11a)

vY > vR > vB

...(11) b

120o < t < v > v > v Y B R 180o 180o < t < v > v > v B Y R 240o 240o < t < 300o 300o < t < 360o vB > vR > vY

V3 = 1120 o V4 = 1180 o

V5 = 1 240 o V6 = 1 300o

V6 = 1 300o V1 = 1 0o

vR > vB > vY

25

Fig. 1. P. Srikant Varma G. Narayanan

VDC 2 O

SR

SY

SB

R
SR SY

Y
SB

VDC 2

Fig. 2. P. Srikant Varma G. Narayanan

Voltage References/ Modulating waves User Defined References Controller PWM PWM pulses Feedback signals

V DC

3 phase load/ circuit

Fig. 3a. P. Srikant Varma G. Narayanan

se pha Y

b- axis

Vs

R phase
B pha se

a-axis

Fig. 3b. P. Srikant Varma G. Narayanan

V3 (- + -)

V2 (+ + -)

II
b- axis

III
V4 (- + +) V0 (- - -) V7 (+ + +)

Vref a-axis 1.0 V1(+ - -)

IV V
V 5 (- - +)

VI

V6 (+ - +)

Fig. 3c. P. Srikant Varma G. Narayanan

1 y

Ty Ts

VREF

Tx Ts

1 x

Fig. 3d. P. Srikant Varma G. Narayanan

1 y

Ty Ts

VREF

Tx Ts

1 x

Fig. 3e. P. Srikant Varma G. Narayanan

1 y

Ty Ts

VREF

Tx Ts

1x

Fig. 3f. P. Srikant Varma G. Narayanan

7 7

vRO vYO vBO

Tz 2

Tx Ts

Ty

Tz Tz 2 2

Ty Ts

Tx

Tz 2

Fig. 4. P. Srikant Varma G. Narayanan

Fig. 5. P. Srikant Varma G. Narayanan

VP

vR vY

vR vY vB

-VP

vB

0.5 - 0.5 0.5 - 0.5 0.5 - 0.5

vRO vYO vBO

vRO vYO vBO

Ts
(a)

Ts
(b)

Fig. 6a. P. Srikant Varma G. Narayanan

B R 1

7 Y

+-+
2

+++
7

vR>vB>vY (Sector VI ) vR>vY >vB (Sector I ) vY>vR >vB (Sector II ) vY>vB>vR (Sector III )

-3

++
2

+++
7

---

++
4

+++
7

-+-

++
4

+++
7

Y B 5

-++
6

+++
7

vB>vY>vR (Sector IV ) vB>vR >vY (Sector V )

--+

-+

+++

Fig. 6b. P. Srikant Varma G. Narayanan

1 Y 2 B

-3

--0

vB<vY <vR (Sector I ) vB<vR <vY (Sector II ) vR<vB<vY (Sector III ) vR <vY <vB (Sector IV )

++

-+3

Y Y

--0

+++

-+5

--0

++
Y

--+
5

--0

R Y 6

--+
1

--0

vY <vR <vB (Sector V) vY <vB<vR (Sector VI )

-+

--

---

Fig. 7. P. Srikant Varma G. Narayanan

V3 (- + -)

3Vm 4VP

V2 (+ + -)

Ts

V4 (- + +)

V1(+ - -)

V5 (- - +)

V6 (+ - +)

Fig. 8a. P. Srikant Varma G. Narayanan

Fig. 8b. P. Srikant Varma G. Narayanan

vR vY vB

+ + + + + + vMAX
-

* vR * vY vB *

vMID

0.5

vOFF

v MIN

Fig. 8c. P. Srikant Varma G. Narayanan

vMAX

vR vY vB

vMIN

Fig. 10. P. Srikant Varma G. Narayanan

V 3 (- + -)

V 2 (+ + -)

0.866

0.75
V 4 (- + +) V0 (- - -) V7 (+ + +)

V1(+ - -)

1.0

V 5 (- - +)

V 6 (+ - +)

Fig. 11a & 11b. P. Srikant Varma G. Narayanan

(a)
7 0

is q - ax
2

2 CSVPWM 1

0,7

VREF 1

SPWM

is d - ax
(b)

SPWM CSVPWM

q-axis ripple

Q1+0.5QZ
0

-0.5QZ

0.5QZ d-axis ripple

0 1

0.5TZ

T1

T2

0.5TZ

Fig. 11c. P. Srikant Varma G. Narayanan