Академический Документы
Профессиональный Документы
Культура Документы
Z86E04/E08
CMOS Z8 OTP MICROCONTROLLERS
PRODUCT DEVICES
Part Number Z86E0412PEC Z86E0412PSC1860 Z86E0412PSC1866 Z86E0412PSC1903 Z86E0412PSC1924 Z86E0412SEC Z86E0412SSC1860 Z86E0412SSC1866 Z86E0412SSC1903 Z86E0412SSC1924 Z86E0812PEC Z86E0812PSC1860 Z86E0812PSC1866 Z86E0812PSC1903 Z86E0812PSC1924 Z86E0812SEC Z86E0812SSC1860 Z86E0812SSC1866 Z86E0812SSC1903 Z86E0812SSC1924 Oscillator Type Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC Crystal Crystal Crystal RC RC Operating VCC 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 3.0V - 5.5V 4.5V - 5.5V 4.5V - 5.5V 3.0V - 5.5V Operating Temperature -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C -40C/105 C 0C/70 C 0C/70C 0C/70C 0C/70C -40C/105C 0C/70C 0C/70C 0C/70C 0C/70C ROM (KB) 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 Package 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin DIP 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC 18-Pin SOIC
Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the twenty E04/E08 product variants most closely match the users application requirements.
DS97Z8X0401
PRELIMINARY
Zilog
FEATURES
s s
14 Input / Output Lines Six Vectored, Prioritized Interrupts (3 falling edge, 1 rising edge, 2 timers) Two Analog Comparators Program Options: Low Noise ROM Protect Auto Latch Watch-Dog Timer (WDT) EPROM/Test Mode Disable
Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler WDT/ Power-On Reset (POR) On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock Clock-Free WDT Reset Low-Power Consumption (50 mw typical) Fast Instruction Pointer (1s @ 12 MHz) RAM Bytes (125)
s s
s s
s s s s
GENERAL DESCRIPTION
Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilogs single-chip Z8 MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. Note: All Signals with a preceding front slash, /, are active Low, for example: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit
VCC
Device
VDD VSS
GND
PRELIMINARY
DS97Z8X0401
Zilog
XTAL
Port 3
ALU
Interrupt Control
FLAG
OTP
Program Counter
Port 2
Port 0
I/O
DS97Z8X0401
PRELIMINARY
Zilog
D7 - 0
AD 11- 0 Z8 MCU MSN Port 3 Address MUX D7 - 0 AD 11- 0 EPROM Data MUX D7 - 0 Z8 Port 0 ROM PROT Low Noise Z8 Port 2 AD 11- 0
PGM + T est Mode Logic VPP P33 EPM P32 /CE XT1 /PGM P30 /OE P31
PRELIMINARY
DS97Z8X0401
Zilog
PIN DESCRIPTION
18
10
18
10
Table 1. 18-Pin DIP Pin Identication EPROM Programming Mode Pin # Symbol Function 14 5 6 7 8 9 10 11 12 13 14 1518 D4D7 VCC N/C /CE /OE EPM VPP Clear Clock /PGM GND D0D3 Data 4, 5, 6, 7 Power Supply No Connection Chip Enable Output Enable EPROM Prog Mode Prog Voltage Clear Clock Address Prog Mode Ground Data 0,1, 2, 3
Table 2. 18-Pin DIP/SOIC Pin Identication Standard Mode Pin # Symbol 14 5 6 7 8 9 10 1113 14 1518 P24P27 Vcc XTAL2 XTAL1 P31 P32 P33 P00P02 GND P20P23
Direction In/Output
Function Port 2, Pins 4,5,6,7 Power Supply Crystal Osc. Clock Crystal Osc. Clock Port 3, Pin 1, AN1 Port 3, Pin 2, AN2 Port 3, Pin 3, REF Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3
DS97Z8X0401
PRELIMINARY
Zilog
Notes: 1. This applies to all pins except where otherwise noted. Maximum current into pin must be 600 A. 2. There is no input protection diode from pin to V (not applicable to EPROM Mode). 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state.
DD
PRELIMINARY
DS97Z8X0401
Zilog
1
From Output Under Test 150 pF
CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 10 pF 20 pF 25 pF
DS97Z8X0401
PRELIMINARY
Zilog
DC ELECTRICAL CHARACTERISTICS
Typical Note 4 @ 25C Units Conditions V V 1.7 2.8 0.8 1.7 1.8 2.8 0.8 1.5 3.0 4.8 3.0 4.8 0.8 0.4 0.4 0.4 1.0 0.8 25.0 25.0 3.0 1.0 1.0 0.2 0.1 0.2 0.1 1.0 0.8 10.0 10.0 2.8 V V V V V V V V V V V V V V V V V V mV mV V A A IOH = 2.0 mA IOH = 2.0 mA Low Noise @ IOH = 0.5 mA Low Noise @ IOH = 0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +12 mA, IOL = +12 mA, 5 5 5 5 5 5 IIn<250 A IIn<250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Notes 1 1
TA = 0C to +70C Sym VINMAX VCH Parameter Max Input Voltage Clock Input High Voltage VCC [4] 3.0V 5.5V 3.0V 5.5V VCL Clock Input Low Voltage 3.0V 5.5V VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V VOL1 Output Low Voltage 3.0V 5.5V 3.0V 5.5V VOL2 Output Low Voltage 3.0V 5.5V VOFFSET Comparator Input Offset Voltage VLV IIL VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range 3.0V 5.5V 2.2 3.0V 5.5V 1.0 1.0 0.8 VCC 0.8 VCC VSS0.3 VSS0.3 0.7 VCC 0.7 VCC VSS0.3 VSS0.3 VCC0.4 VCC0.4 VCC0.4 VCC0.4 Min Max 12 12 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
@ 6 MHz Max. Int. CLK Freq. VIN = 0V, VCC VIN = 0V, VCC
IOL VICR
3.0V 5.5V
1.0 1.0 0
A A V
PRELIMINARY
DS97Z8X0401
Zilog Typical Note 4 @ 25C 1.5 6.8 3.0 8.2 3.6 12.0 0.7 2.5 1.0 3.0 1.5 4.0 1.5 6.8 2.5 7.5 3.0 8.2
TA = 0C to +70C Sym ICC Parameter Supply Current VCC [4] 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V ICC1 Standby Current 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V ICC Supply Current (Low Noise Mode) 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V Min Max 3.5 11.0 8.0 15.0 10.0 20.0 2.5 4.0 4.0 5.0 4.5 7.0 3.5 11.0 5.8 13.0 8.0 15.0
Units Conditions mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 8 MHz All Output and I/O Pins Floating @ 12 MHz All Output and I/O Pins Floating @ 12 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V,VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 8 MHz HALT Mode VIN = 0V, VCC @ 12 MHz HALT Mode VIN = 0V, VCC @ 12 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 1 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 2 MHz All Output and I/O Pins Floating @ 4 MHz All Output and I/O Pins Floating @ 4 MHz
Notes 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 7 7 7 7 7 7
DS97Z8X0401
PRELIMINARY
Zilog
Notes: 1. Port 2 and Port 0 only 2. VSS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 4. The VCC voltage specification of 3.0 V guarantees 3.3 V 0.3 V with typical values measured at VCC = 3.3V. The VCC voltage specification of 5.5 V guarantees 5.0 V 0.5 V with typical values measured at VCC = 5.0 V. 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level.
10
PRELIMINARY
DS97Z8X0401
Zilog TA = -40C to +105C Sym VINMAX VCH Parameter Max Input Voltage Clock Input High Voltage VCC [4] 4.5V 5.5V 4.5V 5.5V VCL Clock Input Low Voltage 4.5V 5.5V VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V VOL1 Output Low Voltage 4.5V 5.5V 4.5V 5.5V VOL2 Output Low Voltage 4.5V 5.5V VOFFSET Comparator Input Offset Voltage VLV VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range 4.5V 5.5V 4.5V 5.5V VICR 0 4.5V 5.5V 1.8 Min Max 12.0 12.0 0.8 VCC VCC+0.3 0.8 VCC VCC+0.3 VSS0.3 VSS0.3 0.2 VCC 0.2 VCC 2.8 2.8 1.7 1.7 2.8 2.8 1.5 1.5 4.8 4.8 Typical Note 4 @ 25C Units V V V V V V V V V V V V V V 0.4 0.4 0.4 0.4 1.0 1.0 25.0 25.0 3.8 0.1 0.1 0.1 0.1 0.3 0.3 10.0 10.0 2.8 V V V V V V mV mV V
Conditions IIN < 250 A IIN < 250 A Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes 1 1
0.7 VCC VCC+0.3 0.7 VCC VCC+0.3 VSS0.3 VSS0.3 VCC0.4 VCC0.4 VCC0.4 VCC0.4 0.2 VCC 0.2 VCC
IOH = 2.0 mA IOH = 2.0 mA Low Noise @ IOH = 0.5 mA Low Noise @ IOH = 0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +12 mA, IOL = +12 mA,
5 5
5 5
5 5
@ 6 MHz Max. Int. CLK Freq. VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC
IIL
A A A A V
IOL
DS97Z8X0401
PRELIMINARY
11
Zilog
12
PRELIMINARY
DS97Z8X0401
Zilog TA = -40C to +105C Sym ICC1 Parameter Standby Current (Low Noise Mode) VCC [4] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V ICC2 Standby Current 4.5V 5.5V IALL IALH Auto Latch Low Current Auto Latch High Current 4.5V 5.5V 4.5V 5.5V Min Max 4.0 4.0 4.5 4.5 5.0 5.0 20 20 40 40 20.0 20.0 Typical Note 4 @ 25C 2.5 2.5 2.8 2.8 3.0 3.0 1.0 1.0 16 16 8.0 8.0 Units mA mA mA mA mA mA A A A A A A
Conditions HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 1 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 2 MHz HALT Mode VIN = 0V, VCC @ 4 MHz HALT Mode VIN = 0V, VCC @ 4 MHz STOP Mode VIN = 0V, VCC WDT is not Running STOP Mode VIN = 0V, VCC WDT is not Running 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC
Notes: 1. Port 2 and Port 0 only 2. VSS = 0V = GND 3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases. 4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at VCC or VSS level. 8. If analog comparator is selected, then the comparator inputs must be at VCC level.
DS97Z8X0401
PRELIMINARY
13
Zilog
AC ELECTRICAL CHARACTERISTICS
Clock
2 7 7 2 3
T IN
4 6 5
IRQ
N
8 9
14
PRELIMINARY
DS97Z8X0401
Zilog
62 62 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 25 12 50 20
41 41 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 25 12 50 20
ns ns ns ns
180 80
180 80
ms ms ms ms
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31) 3. The VDD voltage specification of 3.0V guarantees 3.3V 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
DS97Z8X0401
PRELIMINARY
15
Zilog
ns ns ns ns
100 100
100 100
ms ms ms ms
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request made through Port 3 (P33-P31).
16
PRELIMINARY
DS97Z8X0401
Zilog
1
Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1,2 1,2 1 1,2 1 1
No 1 2 3 4. 5 6 7 8 9 10
Symbol TPC TrC TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL Low Time TwIH High Time Twdt
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Int. Request Input Watch-Dog Timer Delay Time for Timeout
VCC 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
500 500 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 25 12
125 125 100 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 100 70 2.5TpC 2.5TpC 25 12
ns ns ns ns
ms ms
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. The VDD voltage specification of 3.0V guarantees 3.3V 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V.
DS97Z8X0401
PRELIMINARY
17
Zilog
No 1 2 3 4. 5 6 7 8 9 10
Symbol TPC TrC TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time for Timeout
VCC 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V
Units ns ns ns ns ns ns ns ns
500 500 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 10 10
125 125 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 10 10
ns ns ns ns
ms ms
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31).
18
PRELIMINARY
DS97Z8X0401
Zilog
Output drivers have resistances of 500 Ohms (typical). Oscillator divide-by-two circuitry eliminated.
All pre-driver slew rates reduced to 10 ns typical. Internal SCLK/TCLK operation limited to a maximum of 4 MHz - 250 ns cycle time.
The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted.
Application Precaution
The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above Vcc occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the Vpp, /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP Mode include the following:
s s
Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode.
DS97Z8X0401
PRELIMINARY
19
Zilog
Port 0 (I/O)
Open
PAD
500 k
20
PRELIMINARY
DS97Z8X0401
Zilog Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bidirectional, Schmitt-triggered CMOS-compatible I/O port. These eight I/O lines can be configured under software
Z86E04/E08 CMOS Z8 OTP Microcontrollers control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8).
Port 2 (I/O)
Port 2
DS97Z8X0401
PRELIMINARY
21
Zilog
Port 3
R247 = P3M
0 = Digital 1 = Analog D1
TIN
DIG. PAD P31 (AN1)
+
AN.
IRQ3
PAD P32 (AN2) PAD
IRQ0
22
PRELIMINARY
DS97Z8X0401
Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP
Z86E04/E08 CMOS Z8 OTP Microcontrollers Mode. The common voltage range is 0-4 V when the VCC is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input.
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated into the Z86E04/E08 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for TPOR ms, plus 18 clock cycles, then starts program execution at address 000C (Hex) (Figure 10). The Z86E04/E08 control registers' reset value is shown in Table 3.
INT OSC POR (Cold Start) Delay Line TPOR msec P27 (Stop Mode)
XTAL OSC
Chip Reset
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions:
s s s s
Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator.
DS97Z8X0401
PRELIMINARY
23
Zilog
Reg. SPL RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR
D7 0 0 U 0 U U U U 1 U U U U 0
D6 0 0 U U U U U U 1 U U U U 0
D1 0 0 U U 0 U 0 0 1 U U 0 U 0
D0 0 0 U U 0 U 1 0 1 0 U 0 U 0
Comments
Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
24
PRELIMINARY
DS97Z8X0401
Zilog Program Memory. The Z86E04/E08 addresses up to 1K/2KB of Internal Program Memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0-1024/2048 are on-chip one-time programmable ROM.
Z86E04/E08 CMOS Z8 OTP Microcontrollers Register File. The Register File consists of three I/O port registers, 124 general-purpose registers, and 14 control and status registers R0-R3, R4-R127 and R241-R255, respectively (Figure 12). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8.
1023/2047 Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 On-Chip ROM
3FH/7FFH
Location 255 (FFH) 254 (FE) Stack Pointer (Bits 7-0) General-Purpose Register Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer/Counter 0 T1 Prescaler Timer/Counter 1 Timer Mode Not Implemented 128 127 (7FH) General-Purpose Registers 4 3 2 1 0 (00H) Port 3 Port 2 Reserved Port 0
Indentifiers SPL GPR RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR
0CH IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 0BH 0AH 09H
253 (FD) 252 (FC) 251 (FB) 250 (FA) 249 (F9)
248 (F8) 247 (F7) 246 (F6) 245 (F5) 244 (F4) 243 (F3) 242 (F2) 241 (F1H)
P3 P2 P1 P0
DS97Z8X0401
PRELIMINARY
25
Zilog
r7 r6
r5 r4
r3 r2
r1 r0
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF
Register Group F
F0
R15 to R0
7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F
The lower nibble of the register file address provided by the instruction points to the specified register.
Register Group 1
10 0F
00 *Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253(RP).
26
PRELIMINARY
DS97Z8X0401
Zilog
Internal Data Bus Write OSC PRE0 Initial Value Register Write T0 Initial Value Register Read T0 Current Value Register
IRQ4
External Clock
Clock Logic 4
IRQ5
TIN P31
* Note: By passed, if Low EMI Mode is selected. Figure 14. Counter/Timers Block Diagram
DS97Z8X0401
PRELIMINARY
27
Zilog
IRQ0 - IRQ5
IRQ
IMR
6 IPR
Interrupt Request
PRIORITY LOGIC
Vector Select
28
PRELIMINARY
DS97Z8X0401
Zilog Clock. The Z86E04/E08 on-chip oscillator has a highgain, parallel-resonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 12 MHz max., with a series resistance (RS) of less than or equal to 100 Ohms.
Z86E04/E08 CMOS Z8 OTP Microcontrollers The crystal should be connected across XTAL1 and XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (Figure 16). Note that the crystal capacitor loads should be connected to VSS, Pin 14 to reduce Ground noise injection.
XTAL1
XTAL1 C1 * R
XTAL1
XTAL2
XTAL2
XTAL2
External Clock
DS97Z8X0401
PRELIMINARY
29
Zilog
56 pFd A(Hz) 20K 34K 84K 182K 330K 884K 1.6M 2.8M 6M 8.8M B(Hz) 20K 32K 78K 164K 300K 740K 1.3M 2M 4M 6M
100 pFd A(Hz) 12K 20K 48K 100K 185K 500K 980K 1.7K 3.8K 6.3K B(Hz) 11K 19K 45K 95K 170K 450K 820K 1.3M 2.7M 4.2M
0.00 1Fd A(Hz) 1.4K 2.5K 6K 12K 23K 65K 130K 245K 600K 1.0M B(Hz) 1.4K 2.4K 6K 12K 22K 61K 123K 225K 536K 950K
A(Hz) 33K 56K 144K 315K 552K 1.4M 2.6M 4.4M 8M 12M
Table 6. Typical Frequency Vs. RC Values VCC = 5.0V @ 25C Load Capacitor Resistor (R) 1.0M 560K 220K 100K 56K 20K 10K 5K 2K 1K
Notes:
33 pFd A(Hz) 18K 30K 70K 150K 268K 690M 1.2M 2M 4.6M 7M B(Hz) 18K 30K 70K 148K 250K 600K 1M 1.7M 3M 4.6M A(Hz) 12K 20K 47K 97K 176K 463K 860K 1.5M 3.3M 5M
56 pFd B(Hz) 12K 20K 47K 96K 170K 416K 730K 1.2M 2.4M 3.6M
100 pFd A(Hz) 7.4K 12K 30K 60K 100K 286K 540K 950K 2.2M 3.6K B(Hz) 7.7K 12K 30K 60K 100K 266K 480K 820K 1.6M 2.6M
0.00 1Fd A(Hz) 1K 1.6K 4K 8K 15K 40K 80K 151K 360K 660K B(Hz) 1K 1.6K 4K 8K 15K 40K 76K 138K 316K 565K
30
PRELIMINARY
DS97Z8X0401
Zilog HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP Mode, use the following instruction: LD NOP STOP P2M, #1XXX XXXXB
Z86E04/E08 CMOS Z8 OTP Microcontrollers Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time Opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every TWDT; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of TPOR, plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect. Permanent WDT. Selecting the hardware enabled Permanent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled. Auto Reset Voltage (VLV). The Z86E04/E08 has an autoreset built-in. The auto-reset circuit resets the Z86E04/E08 when it detects the VCC below VLV. Figure 18 shows the Auto Reset Voltage versus temperature. If the VCC drops below the VCC operating voltage range, the Z86E04/E08 will function down to the VLV unless the internal clock frequency is higher than the specified maximum VLV frequency.
X = Dependent on user's application. Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as: FF 6F FF 7F NOP STOP or NOP HALT ; clear the pipeline ; enter STOP Mode ; clear the pipeline ; enter HALT Mode
DS97Z8X0401
PRELIMINARY
31
Zilog
2.8
2.7
2.6
2.5
2.4
Temp
32
PRELIMINARY
DS97Z8X0401
Zilog
Z86E04/E08 CMOS Z8 OTP Microcontrollers ROM Protect. ROM Protect fully protects the Z86E04/E08 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported (Z86E04/E08 and Z86C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automatically be enabled. Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to VCC through a diode to VCC to prevent accidentally entering the OTP Mode. The VPP requires both a diode and a 100 pF capacitor. Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches. WDT Enable. The WDT Enable option bit, when programmed, will have the hardware enabled Permanent WDT enabled after exiting reset and can not be stopped in Halt or Stop Mode. EPROM/Test Mode Disable. The EPROM/Test Mode Disable option bit, when programmed, will disable the EPROM Mode and the Factory Test Mode. Reading, verifying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled. User Modes. Table 7 shows the programming voltage of each mode of Z86E04/E08. Table 7. OTP Programming Table
Less than 1 mA consumed during HALT Mode. All drivers slew rates reduced to 10 ns (typical). Internal SCLK/TCLK = XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time. Output drivers have resistances of 500 ohms (typical).
s s
Oscillator divide-by-two circuitry eliminated. The Z86E04/E08 offers programmable ROM Protect and programmable Low Noise features. When programmed for Low Noise, the ROM Protect feature is optional. In addition to VDD and GND (VSS), the Z86E04/E08 changes all its pin functions in the EPROM Mode. XTAL2 has no function, XTAL1 functions as /CE, P31 functions as /OE, P32 functions as EPM, P33 functions as VPP, and P02 functions as /PGM.
Programming Modes EPROM READ1 EPROM READ2 PROGRAM PROGRAM VERIFY EPROM PROTECT LOW NOISE SELECT AUTO LATCH DISABLE WDT ENABLE EPROM/TEST MODE
VPP NU NU VH VH VH VH VH VH VH
/OE VIL VIL VIH VIL VIH VIH VIL VIH VIL
/PGM VIH VIH VIL VIH VIL VIL VIL VIL VIL
VCC* 4.5V 5.5V 6.4V 6.4V 6.4V 6.4V 6.4V 6.4V 6.4V
Notes: 1. VH =13.0V 0.25 VDC . 2. VIH = As per specific Z8 DC specification. 3. VIL= As per specific Z8 DC specification. 4. X = Not used, but must be set to VH or VIH level. 5. NU = Not used, but must be set to either VIH or VIL level. 6. IPP during programming = 40 mA maximum. 7. ICC during programming, verify, or read = 40 mA maximum. 8. * VCC has a tolerance of - 0.25V. 9. VCC = 5.0V is acceptable.
DS97Z8X0401
PRELIMINARY
33
Zilog
Table 8. Timing of Programming Waveforms Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name Address Setup Time Data Setup Time VPP Setup VCC Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time /OE Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width EPM Setup Time /PGM Setup Time Address to /OE Setup Time Option Program Pulse Width /OE Width Address Valid to /OE Low Min 2 2 2 2 2 0.95 2 2 188 100 2.85 2 2 2 78 250 125 Max Units s s s s s ms s s ns ns ms s s s ms ns ns
34
PRELIMINARY
DS97Z8X0401
Zilog
T2
P01 = Clock
T4 T3 T1
P00 = Clear
Vpp/EPM
T6 T5
Valid
9
Invalid
Valid
Legend: T1 Reset Clock Width T2 Input Clock High T3 Input Clock Period T4 Input Clock Low T5 Clock to Address Counter Out Delay T6 Epm/Vpp Set up Time 30 ns Min 100 ns Min 200 ns Min 100 ns Min 15 ns Max 40 s Min
DS97Z8X0401
PRELIMINARY
35
Zilog
VIH Address VIL VIH Data VIL VH VPP VIL VH EPM VIL
12 17
Address Stable
Address Stable
17
Invalid
9
Valid
Invalid
Valid
5.5V
VCC
4.5V VIH
/CE
VIL VIH
5 16 16 16
/OE
VIL VIH
/PGM
VIL
3
36
PRELIMINARY
DS97Z8X0401
Zilog
Address Stable
1
Data Out Valid
Data Stable
2 9
10
VH VPP VIH
3
DS97Z8X0401
PRELIMINARY
37
Zilog
6V VCC 4.5V
4
VH /CE VIH
5
/OE
VIH
VIH
12 13
EPROM Protect
Low Noise
Figure 21. Z86E04/E08 Programming Options Waveform (EPROM Protect and Low Noise Program)
38
PRELIMINARY
DS97Z8X0401
Zilog
6V VCC 4.5V
4
VH /CE VIH
5
VIH
/OE
VIL
12 13 12 13
13
15
15
15
Auto Latch
WDT
Figure 22. Z86E04/E08 Programming Options Waveform (Auto Latch Disable, Permanent WDT Enable and EPROM/Test Mode Disable)
DS97Z8X0401
PRELIMINARY
39
Zilog
Start
N=0
Program 1 ms Pulse
Increment N
Yes N = 25 ? No Fail Verify One Byte Pass Prog. One Pulse 3xN ms Duration Fail
Increment Address
Fail
Device Failed
Fail
40
PRELIMINARY
DS97Z8X0401
Zilog
Z8 CONTROL REGISTERS
R244 T0 D7 D6 D5 D4 D3 D2 D1 D0
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0
1
T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When READ)
0 No Function 1 Load T0 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T1 0 Disable T1 Count 1 Enable T1 Count TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Reserved (Must be 0)
R245 PRE0 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T0 Single Pass 1 T0 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
T 1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T 1 Current Value (When READ)
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain 1 Port 2 Push-pull Port 3 Inputs 0 Digital Mode 1 Analog Mode
Reserved (Must be 0)
DS97Z8X0401
PRELIMINARY
41
Zilog
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
P02-P00 Mode 00 = Output 01 = Input Reserved (Must be 1.) Reserved (Must be 0.)
Figure 34. Interrupt Mask Register (FBH: Read/Write) Figure 31. Port 0 and 1 Mode Register (F8H: Write Only)
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1 User Flag F2
Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 01 1 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 IRQ1, IRQ4 Priority (Group C) 0 = IRQ1 > IRQ4 1 = IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 = IRQ2 > IRQ0 1 = IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 = IRQ5 > IRQ3 1 = IRQ3 > IRQ5 Reserved (Must be 0.)
Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
42
PRELIMINARY
Zilog
PACKAGE INFORMATION
DS97Z8X0401
PRELIMINARY
43
Zilog
Z86E08
Standard and Extended Temperature 18-Pin SOIC Z86E0812SSC Z86E0812SEC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
Codes
Preferred Package P = Plastic DIP Longer Lead Time S = SOIC
Preferred Temperature S = 0C to +70C E = 40C to +105C Speeds 12 =12 MHz Environmental C = Plastic Standard
Example:
Z 86E04 12 P S C is a Z86E04, 12 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix
1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilogs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX (408) 370-8056 Internet: www.zilog.com
44
PRELIMINARY
DS97Z8X0401