IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.

ED-27, NO. 9, SEPTEMBER 1980

1809

Dual-Gate Bucket-Brigade Devices

RADU M. BARSAN, MEMBER,
IEEE

Abstract-The low charge-transfer efficiency of the basic bucketbrigade circuit and the speed limitation of the tetrode approach have so far prevented bucket-brigadedevices (BBDs), in spite of their greater fabrication simplicity, from competing with charge-coupled devices, excepting for audio applications. A novel charge-transfer device is presented and experimentally evaluated. The dual-gate BBD is a two-step-transfer device (a CCD transfer followed by a BBD transfer),showing operational performances comparable t surface-channel CCDs and, at the same time, enjoying o the fabrication simplicity proper to bucket-brigadecircuits.The concept is implemented using conventional p-channel aluminum-gate technology combined with an additionalshadowed-gap float-off process. The characteristic features and the performance capabilities of the device are discussed.
B I A S LINE

I.INTRODUCTION URING the last decade, charge-transfer devices (CTDs) [l] have developed from the laboratory concept into a mature class of semiconductor devices with significant impact in the areas of sampled-data signal processing,imaging, and memory. The CTD family includes charge-coupled devices (CCDs) [ 2 ] andbucket-brigade devices(BBDs) [3]. Generally, CCDs have better operational performances than BBDs. Atmoderatefrequencies,charge-transferinefficiencyinsurface-channel CCDs on order and the is the of on order of lo- in buried-channel devices, whereas BBDs are limited t o values greater than Dark current noise and are also smaller in CCDs and the packing density is greater than that of BBDs. In exchange, CCDs are more difficult to fabricate. In order to achieve their full capabilities, CCDs require leadingedge technologies,invalidatingtheearlypredictionsthat their processing would be simpler thanconventional MOS circuit technology. In contrast, BBDs can be fabricated using the simplest of the MOS processes, such as a p-channel aluminum gate. This paper describes a novel bucket-brigadestructure, termed dual-gate BBD, which exhibits performance capabilities comparable to surface-channel CCDs. The device is fabricated using ahigh-thresholdp-channel Al-gate technology with an additional float-off process yielding self-aligned gates with submicrometer separations. The device characteristics are discussed in Section I1 and some processing details are presented in Section 111. Experimental results on device performance are reported and interpreted in Section IV.

I
01

1
1

02

(4 Fig. 1. Schematiccross sections througha p-channel (a)simpleBBD, (b) tetrode configuration, and (c) novel dual-gate bucket brigade.

form one of the storage elements in the delay line. The most significant effects contributing to charge-transfer inefficiency atlowandintermediatefrequenciesarethefinitedynamic drain conductance, threshold-voltage modulation, storagecapacitancemodulation[4] -[8] , andsubthreshold leakage [7], [9]. Athigherclockrates, the transfer inefficiencyincreases due to the finite time allotted for charge to flow from one capacitor to the next [4] -[8] . This inherent limitation is determined by the gain characteristicsof thetransistors, as well as by the magnitude of the storage capacitances, and the corresponding intrinsic inefficiency term [7] is given by

11. CHARACTERISTICSF THE DUAL-GATE O BBD In the basicBBD shiftregister,shownin Fig. l(a), charge transfer takes place through the channel of a simple MOSFET whosegate-draincapacitancehas been largely increased to
Manuscript received July 15,1979; revised April 15, 1980. The author iswith the R and D Center for Semiconductors, Bucharest 72996, Rumania.

where 0 is the saturated MOSFET square-law factor, Vc the clock voltage level, V, thethreshold voltage, & the initial , source potential, C,, the storage capacitance, and f,the clock frequency. dominating The mechanisms at low interand mediate frequencies primarily are determined by channel (barrier) length modulation, a typical example being the dynamic drain conductance contribution to incomplete transfer, given by

, where g

is the MOSFET saturation output conductance and

gm the transconductance.

A general method toreduce the modulation effects inCTDs is to isolate the source from the charge sink by means of an

0018-9383/80/009-1809$00.75 0 1980 IEEE

ir1tc:rmediate barrierregion. The charge transfer bec:omc:s in n m d e up clrlly ofthe effective gate capacitance associated with this way atwo-stepprocessinwhichthe chargefrom ore t.he bias-gs-te electrode c b g , , Consequently, all modulation sl:or,age capacitor is first transferred to some jnterrnec1ial:e effects: d o ~ n h ~ a t i n ~ ;low- and intermediate-frequency transthe c,apacitor Cz and then to the next storage capacitor, during ;a f : irle!ffi.c~.e:nc:y are e: reduced .by a factor of c b g / c , , compared single transfercycle.Suchaprocedurereducesthemodulat o th.e simple BBID, and by a factor of c b g / ( c p t C t C , ,, o) tionterms by approximatelytheratio of theintermediate compa.red to the tetrode configuration. The first ratio may lay capacitance tothe storage capacitance [7]. Application of in the rangeof 1/50-~1/100. Considering a tetrode cell and a this principle to the simpleBBD hasresultedin thi: tetrode dulal-,gaie st:ll of t:qlud channel widths, the second factor can strulcture [ 101 , [ 111 , shown in Fig. l(b). Here, the capacitance be expaessed alpprorrimately as CZ (to the left of the active channel) consists of the dep1l:tion bg capacitancebetween theintermediate p island andthesubr == (4) Cdep strat.e C p , the gate capacitance of the first MOSFET Cgl ,a.nd (I, ;I-2 lo, t 2:x.) -t L g l + 2 lov the overlapcapacitance associated with the intermediate island cox and the two adjacent gates, summed up into an overlap capaciwherle l ; b g is the affective length of the bias gate of the dualtance term Cov. Consequently, modulation the (feedback) gate c1d1,Lgl the channel length of the first MOSFET in the cont.ributions to incomplete transfer are reduced from those of cell., 1, theminimuminterelectrodespacing, Zov the the ;simple BBD with the same storage capacitance, by a factor tetroldt: minimum overlap between gate and diffusion: xj the junction of ( ( 7 p + Cg1 -t Cov)/Cst * The main drawback of the tetrode configuration is its low depth, Cde:p the depletion capacitance per unit area, and Cox the oxide capacitance per unit area. Taking L b g = 4 pm, Lgl = speedof operation, as compared with the basic circuit. The lo, effective intrinsic transfer rate term of a two-step transfer cell 10 pm, 1, =- 8 pm., = 6 pm, xj = 2 pm, Cdep = COx/3, the factor r given by (4) is about 0.13. These examples show that is given approximately [7] by the d.u.al-gate BBDI has a low-frequency transfer inefficiencyof 7-8 times smaller than a tetrode BBD and up to two orders of magnitude smaller than the basic circuit. Since theintermediatecapacitanceofthedual-gate cell is reduced by a factor r from that of the tetrodecell, the storage where thesubscripts1and 2 refer to the firstandsecond transfer step, respectively. eli isgiven by (11) in which V is capacitamcle can be made r times smaller for the two structures , replaced by VB, the voltage applied to the bias line. e,j is to ex.hibit similar low-frequency performances. This results in given by a similar expression, in which C is replaced by Cz a signifjicant high-frequency (intrinsic transfer-efficiency) im, and Kn by the initial island potential (whiclh is a function of provennent. Moreover, the high-frequencylimit of the dualKn,V,, and &). Inorder to improve the low-flrequency gate device is further increased through the reduction of e Z i , performance, C has to be , made large compared to CI= which,,inthis calse, corresponcls to a CCD transferprocess. Inaddition,the activechannel. canbemade much smaller Cp t Cgl t C whichdrasticallyaffects ,,, eli. Inaddition, while still avoiding short-channel effects [12] . In conclusion noneofthetwo channels of thetetrode cell canbemade shorter than the channel ofa simple BBD ceU.. Thus the better of the preceding discussion, the dual-gate BBD offers signifilow-frequency behavior of the tetrode configuration is accom- cantly better transfer efficiency over a wide frequency range. panied by a poor high-frequency performance. This limits the Furthermore,the possibility to reduce the cell dimensions, with elimination interelectrode of spacings, usefulness of the tetrode concept to audio a.pplications (typi- combined the result in improved packing density. cally below 50 kHz). Another advantage of the dual-gatestructure over existing The novel dual-gate BBD structure is shown schematically in BBDs concerns the dynamic range. First, the parasitic capaciFig. l(c). Thisconfiguration achieves the screening of the source with respect to the drain of each MOSFET by a self- tance between the pulsed gate and the source is reduced due to aligned bias-gate electrode obtained a with single level of the shielding effect of the self-aligned bias gate, so that larger . Second, the aluminum and a submicrometer gapprocess. Thus each cell signal chargepackets can betransferred[13] contains a dual-gate MOSFET [ 121 , which has the bias gate absence ofan intermediate island reducesdarkcurrentand noise. In addition, the input and output stages can be designed located near the source and the active gate near the drain. In contrast to the tetrode structure discussed above, in which the to reduce the effects of parasitic capacitances. The dual-gate charge transferis by twosuccessive bucket-brigade processes, BBD technology is also compatible with improved peripheral amplifiers using dual-gate MOSFETs [ 141 , whichcan be the charge transferinthe dual-gateapproachconsistsofa bucket-brigade process followed by charge-coupled a attractivefor signal-processing circuitsincorporatinganalog process, provided the dc voltage applied to the bias gate is low delay functions. enough with respect to the clock voltage t o ensure a complete The dlual-gate bucket-brigadeconcepthasbeenreduced to charge-transfer mode of operation of the CCD half cell. practice using p-channel single-levelaluminum-gate technology. Theintermediatecapacitance of the dual-gate BBD cell is The self-aligned metalpatterns were obtainedwith asubThe same concept could also be implemented using overlapping-gate technologies but which, beside increasing the capacitive loading of the clock lines, are more complex and, consequently, less suitable for costeffective CTDs.
21f the tetrode BBD is fabricated with self-aligned islands,,,Z = 0. This higher degree of process complexity is not required by the dualgate approach, so that comparison is made for the simplest of MOS processes.

BARSAN:

BUCKET-BRIGADE DEVICES

1811

INPUT

. .

OUTPUT

Fig. 3. Dual-gate BBD circuit.

source follower (output transistor OT). Note that, in contrast to the transfer transistors, the input dual-gate MOSFET has the gate near the drain connected to the dcbias line (whose voltage is VB),the gate near the source being pulsedby one of the clock phases (G1). The reason for this particular design is as follows. When theinputtransistor is on,the voltage at node A equals the input level qn.. Upon switching ST off (raising $1 anddropping &), the voltage at node A instantaneously changes by an amount

Fig. 2. (a) Microphotograph of experimental dud-gate BBD chip. Lower half of chip contains an 80-stage shift register. Upper portion containstest transistors and capacitors. (b) Enlarged view ofthe transfer structure. The horizontal narrow stripes form the bias lines (gates). They are separated from adjacent clock lines by submicrometer (0.5-firn) gaps.

where VG is the amplitude of theclock pulses. If Cgu greater is than Cgs, input signal can no longer vary from zero, but the onlyfromthe level given by ( 5 ) . Consequently,the ideal maximuminput swing VB - V, is reducedbythisamount. Due to the shielding effect of the bias gate, the parasitic capacitance Cgs much lower than the capacitance between a diffuis sion and the gate overlapping it. According to the preceding discussion, if the gate near the drain of ST were connected to G1, thedynamic range would bereduced.Thealternative shown in Fig. 3 is self-compensating with respect to parasitic capacitancemismatch, since both gates adjacent to C are , formed by the same bias line. Thedynamic rangeisalso limited by the parasiticcapacitances at the outputstage C and cd, (junction capacitances). , , When RT is switchedoffand thelasttransfertransistor is switched on, the voltage at node B should ideally change from the reference level VB - V, to V, -t V, - V,. However,due to parasitics, the voltage changes by onlyafraction of V G , given by

micrometer-gap process similar to the shadow-etch approach described by Browne and Perkins [ 151 , [16] ,yielding typically 0.5-pm gaps. A photograph of the complete chip is shown in Fig. 2(a) and an enlarged view of some of the 80 cells of the BBD circuit is shownin Fig.2(b). Thepathofthe signal samples along the delay line follows a serpentine, alternating between the clock buses from cell to cell and turning around every 10 stages. Beside theshift register, thechipcontains several dual-gate, as well as normal, MOSFETs and some MOS capacitors used for characterization and evaluation purposes. A schematic diagram of the dual-gate BBD shift register is shownin Fig. 3. The circuitconsists of aninput sampling stage(sampling transistor ST and capacitor C) 80 identical ,, transferstages,aprechargerorresettransistor (RT), and a

which is the maximum allowable input swing. The use of a dual-gate precharge transistor reduces Cgs hence, increases and the dynamic range. In conclusion, assuming the effect of parasitic capacitances at the input stage to be negligible, the maximum input signal for a dual-gate BBD delay line is given by V, - V, or ( 6 ) , whichever is smaller.

111. PROCESSING CONSIDERATIONS The dual-gate BBD structures have beenfabricated using standardp-channel Al-gate technologywith HCl gateoxide, followed by a liftoff metal patten definition. Fig. 4 shows a microphotograph and a schematic cross section of a dual-gate cell. After opening the contact windows, a first aluminum film is

BIAS GATE

Fig. 5. Scanning electron micrograph (10 000 X ) of the region separating the bias and clock metal buses (after final heat treatment). Metal 1 is 0.8 pm thick and metal 2 is 0.7 pm thick. The gap size is about 6000 A and the "shadow" (the resist overhang) appears to have been about 1.5 pm. Lower right corner shows an area where aluminum has been removed to produce a cross section through the metallization.
/'

Fig. 4. SEM photograph and cross section of a dual-gate BBD cell. Lg is the effective length of the active channel and Lbg is the effective length of the channel under the bias gate.

evaporated and patterned to define the peripheral metallizations and the clock buses. By an additional photolithographic step, the complement of the bias-gate pattern is printed. Using thismask, thefirstmetal is slightlyoveretched inorder t o produceshadowed edges [16] , Without removing the resist, a second aluminum filmis evaporatedwhich forms the bias gates self-aligned with respect to the activegates.Liftoff of the metal from over the resist is subsequently made in acetone ornitricacid,dependingonitsthickness. Since thesecond layer metal pattern is surrounded by shadowed spacings and the bias line being accessed by an underpass, the only places where the metal has to break over the resist step are narrow terminations at the periphery of the BBD structure. The processingis completedbythedeposition of an overlay oxide, or simply by a heat treatment (10 min in hydrogen and 10 min in nytrogen, both at 550C). A typical interelectrode area is shown in Fig. 5. Note the steepness of the wet-etched metal 1 wall, as compared to the large slopeof themetal 2 pattern,produced by shadowed evaporationinaplanetarysystem.Theupper edge of the slope corresponds to the resist (shadow) edge and the distance to the first layer metal wall shows the magnitude of overetching (the overhang of the resist). Fig.6(a) shows a schematic crosssectionthroughthestructureduringthedeposition of the second aluminum layer. On ageometrical basis, the size of the gap g is determined by the thickness of the first metal layer h, the degree of shadowing (overetching) e, and the most obliqueevaporation angle in theplanetarysystem amin. In practice, the resultedgapis smaller due to the migration of

OVERETCHING l y m )

(b)

Fig. 6 . (a) Cross section through the structure during the evaporation of the second metal layer. (b) The gap size as a function of the overetching of the first metal pattern. Points represent measured values and solid lines are plotted according to (7).

aluminum atoms during evaporation (typically about 3000 A [ 161) and during the final heat treatment or oxide deposition (this was experimentally observed to be about 2000 A for aluminum). Consequently, the gap size is given by
g = e - h cotan a m i n -

(7)

where m represents the gap reduction due to aluminum migration. For amin 60" and m = 0.5 pm, good agreement exists = between (7) and the measured gaps, as shown in Fig. 6(b) for two different thicknesses of the first metal layer. As a result of the investigation ofgap formation, it was confirmed that

BARSAN: DUAL-GATE BUCKET-BRIGADE DEVICES

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5000 A is a typical lower limit for the size of reproducible gaps obtained using aluminum [16] . Sincerelativelystable devices have been fabricated with gaps as large as 1.5 pm, the 0.5-pm margin is not a serious limitation from the standpoint of device performances, stability, reproducibility. and The transferinefficiencymeasured on 0.5-pm-gapshiftregisters showedweak a dependence on background charge, which means that verygood control (absenceofspuriousbarriers) of interelectrode such spacings is possible. However, the 0.5-pm limit could become a problem when very small channels (<3 pm) aredesired,becausesuch short gatesfail to control gap regions greater than a few tenths of a micrometer. A variety of metal thicknesses for both aluminum films have been tested. It was found that a difference of maximum 1000 A between the two is sufficient for easy liftoff of unwanted second-layer metal from over the resist. From threshold voltage,etchingcontrolability,andbondingconsiderations,the thicknessof thefirstaluminum layerfor the devices to be characterized was chosen of 0.8 pm.The secondfilm was 0.7 pm thickandthe resulting gaps weretypically 0.5 pm. Theoxidethickness was inthe rangeof 1200A-1300 A (slightlythinnerunderthe bias gatesdue to anadditional cleaning sequence prior to the second aluminum deposition). The average surfaceimpurityconcentration of the substrate ((1 11) orientation) was 2-4 X 1015cm-. The boron diffusion yielded junction depths of about 1.6 pm. The average effective surface mobility of holes was found to be 140 cm2/V s. The threshold voltage was typically - 4 V for MOSFETs formed by the first aluminum, and about - 4.5 (b) V for those whose gates were formed by the second deposition. 7. Outputs of the BO-stage dual-gate BBD. Verticalscaleis 1V/div. Fig.

kHz. The input word is a sequence of the form 10001000 . . * . IV. EXPERIMENTAL RESULTS AND DISCUSSION OF DEVICE PERFORMANCE The principal parameters (after processing) of the 80-stage together with the dual-gate devices. The observed dependence of E on the bias gate voltage V j is illustrated in Fig. 9. dual-gate BBDs which were characterized are Let us first discuss the behaviorofthedual-gate BBD for large bias gate voltages. It is clear in Fig. 8 that for this case active channel length,L, = 8.5 pm; (VB = - 16 V) the dominant mechanisms responsible for transbias-gate length,Lbg = 6 pm; fer inefficiency below about 1 MHz are subthreshold conducchannel width, W = 32 pm; tion (diffusion over the barrier)and the dynamicdrainconstorage capacitance, Cst = 1.4 pF. ductance effect, since E is weakly dependent on clock frequency and shows the same dependence as the simple BBD (the two The devices were operated with zero substrate bias and clock is surelyaffectedbymodulation voltageamplitudesof 20 V, atfrequencies varying between curvesareparallel)which range. With 1 kHz and 1 MHz. The maximum input swing for 20-V square effects only (Lg = 5 pm), within this frequency clocks and a dc gate bias of -20 V was about 11 V. Typical regard to the relativemagnitude ofthetwotransfer-inefficiency values, the first-order analysis in Section I1 predicts an device responses are shown in Fig. 7. The registers were characterized with respect to transfer effi- improvement of cb,/cst for the dual-gate device, compared to ciency by the step-response method, whereby the incomplete the simplecircuit. By taking intoaccountthe difference in channel lengths, the above factor has to be multiplied by the transfer parameter E is determined from ratio of the simple BBD channel length to that of the dualL T = ( N - l)E (8) gate device. The result is 0.023, which is close to the observed LT the total improvement. Also note (Fig. 9) thatfor V, inthe range where N is the number of delay elements and V normalized loss, defined as the sum of all trailing pulses divided VG - VT < V , < V,, E increases with increasing (absolute value) for V, fixed. This is due to the reduction of the fringby the steady-state output level. Plots of experimentally determined transfer inefficiency,as a function of clock frequency ingfieldbetween the bias andtheactivegatewhen VB is (&), are shown in Fig. 8 for two different voltages applied to increased towards V, (when V, is higher than VG the channel the bias line. Also shown is the measured transfer inefficiency underneath the bias gate is no longer pinched off and acts as ofa128-stagesimple BBD delayline,which was processed a simple series resistance). In terms of saturation conductance,

(a) Step function response at 260 kHz. (b) Impulse response at 100

1814

IEEE TRRXSACTIONS ON ELECTRON DEVICES,VOL.ED-27,

NO. 9, SEPTEMBER 1980

t
l ' o 106

VG

i-

20 v
-1

'
O
10 20

I
30
LO

lo5
CLOCK

106

FREQUENCY ( H z )

Fig. 8. Dual-gate bucket-brigade transfer inefficiency as a functio:n of clock frequency. The broken line corresponds to a simple BBD clhift register having 5-pm channels (40 pm wide) and a storage capacitance of 0.4pF.

GATE OLTAGE V V ( I Fig. 10. Dual-gate MOSFET output conductance in saturation versus gate voltage for different bias gate voltages. Lg = 8.5 pm, L b = 15 pm, and W = 64 pm. The dashed line corresponds to a normd transistor having the gatedefined by the secondaiuminumdeposition. The channel widthis the same and the channel length is 11 pm.

10-1

vo.-20v

$ lo-*,
2

fc=500 KHz

w .
i ! u
U

103:
-

E
v)

w LC.

5 166 :
I E .

1
-10

-12

~ -16

-lL

' -10

'

-20

BIAS

GATE VOLTAGE

IV

Fig. 9. Measured transfer inefficiency versus bias gate voltage for th.ree different clock frequencies. g& increaseswith

V,, as will be illustratedlater on in this section.The regime in which V, is not low enoughwith respect to VG to pinch off the channel underneath the bias gate corresponds to an incomplete (bias) charge-transfer mode of operation of the "CCD" half cells of the dual-gate B13D. When V, is reduced below approximately VG - V,, another mechanism comes into play at higher clock rates. TMIS is the intrinsic transfer rate limitation associated with the fir:;t transfer in the dual-gate BBD cell, resulting in the term eli in (3). Indeed, the low bias voltage plot in Fig. 8 (V, = - 12 V) shows a more rapid increase with clock frequency above about 100 kHz. Also, the 500-kHz plot in Fig. 9' shows a decrease of e withincreasing VB forlow V values,whichconfirms ' the conclusion that the contribution of e l l is significantat low bias gate voltages and high clock rates. From the point of view of dynamic range, V, should be as high as possible. However, as evidenced in Fig. 9, the choice of V , only within an optimum range yields a minimum transfer inefficiency. The upper limit of this optimum range is on the order of VG- V,. The choice of V, is critical only at higher clockfrequencies, but sincenormally V, is derived on-chip

(from the VDDsupply) it has to be set regardless of the operating rate. Concerning the clock frequency figures mentioned in the preceding discussion, it should be kept in mind that the dual-gate BBD under consideration has rather long channels, large storagecapacitances,andalowcarriermobility.Thus other :structures improved with electrical geometrical and parameters mayexhibitlow-frequencycharacteristics up to much higher clock rates. In order to get more insight into the behavior of the dualgatecell,measurementswereconducted on individualdualgate MOST'S on the same chip. Emphasis was directed towards the output conductance in saturation, which is directly determined channel-length by modulation. Typical experimental results. for gd, as a function of V G , with VB as a parameter, " are shown in Fig. 10. The dual-gate FET has the same L, as the BBD half cell. The broken line stands for a normal (singlegate) transistor with a slightly longer channel. Theplots in Fig. 10 show that, incontrast to anormal MOSFET whose g& increases uniformly with increasing gate voltage, saturation the conductmce of a dual-gate device exhibits a maximum and then decreases with increasing VG. It also depends onthe dc voltage applied to the bias gate. Inthe dual-gatetransistor,thesurfacepotentialunderthe activegateacts as drain bias forthe device underthefirst gate(thefirsttransistor) and is afunction of both VG and the actually applied drain voltage VD. For VD fixed, a change in VG results in a modification of the effective drain potential forthe firsttransistor.Thusfor VG smaller than VB - V$ (where V$ is athresholdvalue),thefirstchannel is below pinchoff and g& of the dual-gate MOSFET is practically the saturationconductanceofthesecondtransistor,increasing consequently with VG. As VG approaches V, - V$, gds levels off, departing from normal transistor behavior. The pointofmaximum g& approximately corresponds t o the saturation of the first transistor, which resultsin the "tetrode" effect. The larger VB (absolute value), the more difficult it is to pinch off the channel, so that the peak moves toward larger gate voltages as VB is increased and obviously also increases. Thisexplains the behavior of the dual-gate BBD cell with respect to bias gate voltage discussed earlier. Beyond the

BARSAN: DUAL-GATE BUCKET-BRIGADE DEVICES

1815

verified. The dual-gate BBD achieves charge-transferperformancescomparable to surface-channel CCDs. Theprincipal advantages of this new structure over existing BBDs can be summarized as follows:

(C)
5 -

185

25

0
0

vG.-16v

lower transfer inefficiency (more than an order of magnitude smaller thanthat of simple BBDs and up to an order of magnitude smaller than that of tetrode BBDs); larger high-frequencylimit and higherpackingdensity than tetrode BBDs; larger dynamic range (higher allowable input swing and lower noise).
/ ,

J
0

-5

-10

-15

-20

-25

-30

B I A S GATE VOLTAGE

(VI

Fig. 11. Dependence of the saturation output conductance gds on bias gate voltage VB, for three different dual-gate transistors. All three have the s q e channel width W = 64 elm. Transistors A and B only differ through bias gate length, whereas B and C have different active channel lengths. The broken line shows the output conductance of a normal MOSFET whose channel length equals the sum of L, and Lb, of the dual-gate transistor B.

pinchoff point, the dual-gate MOSFET current is controlled by the firsttransistorwhoseeffectivedrainvoltage is increased by increasing VG (this being the operating regime of the dual-gate BBD). As a consequence, gds decreases with increasing VG, normally going to zero very for large gate voltages,andthis is shown to be the case formoderate VB values. For both VG and VBlarge (high current levels), a negativeconductanceeffect shows upin Fig. 10. Thiscould be explained by the decrease of mobility with increasing temperature in thelocally heated channel at high power levels [ 171 . In order to assess more clearly the effect of the bias gate, experimental results for gds measured on different dual-gate MOSTS are shown in Fig. 11 as functions of V B . The output conductance increases linearly with VB up to the point where the first transistor of the dual-gate device is no longer saturated. A directobservation is that a longerbiasgateallows better control of the dual-gatetransistorparameters, as expected. However, even a 2.5-pm bias gateis able to significantly reduce gds of an 8.5-pm dual-gate device fromthat of anormal MOSFET,provided VB is lower than VG. When VB equals VG,the output conductance is about the same as that of the normal transistor whose channel length is equal to L, t Lbg. If the bias gate is much shorter than the active channel (case C), gds tends to be less dependent on VB. It follows that the relative length of the bias gate with respect to the active gate alone is of consequence. Although the longer the bias gate, the smaller theoutputconductance,our resultsshow that significant improvement over equivalent normal MOSFETs is possible even with bias gates 3 to 4 times shorter than the active channel.

concepthasbeenimplemented using p-channel Al-gate technologyconjunction a in with shadowed-gap float-off processwhichyieldedself-alignednonoverlappingbiasgates separatedfrom the clockbuses by reproduciblesubmicron gaps (typically 0.5 pm). The high yields proper to p-channel aluminum-gate technology were not affected by the additional process. Transfer inefficiencies at below 100 kHz and below at MHz have been 1 currently observed, despite the low carrier mobility (140 cm2 /V s). The operation of the dual-gate BBD has been discussed and the experimental results have been interpreted. Measurements on individual dual-gate MOSFETs having the active gate near the drain(thebuildingblocksof the novel CTD structure) have revealed a dependence of the saturation output conductance on gate voltage different from that of single-gate transistors. The behavior of gdshas been explained and correlated with the observed operational performances of the dual-gate bucket brigade. ACKNOWLEDGMENT Theauthor wishes tothank A.Delibaltov who provided invaluable during help the developmental processing stage. Theassistanceof S . Prisecaru in the SEM evaluationsand of G. Voicu in the measurements is appreciated. Continuous support and encouragement from C. Bulucea is also gratefully acknowledged. REFERENCES
[ 11 C. H. Skquin and M. F. Tompsett, Charge Transfer Devices, suppl.

[2] [3] [4] [5] [6]

V. CONCLUSIONS [7] Due to arelativelyhighdegree of processingcomplexity, CCDs are less accessible CTDs than BBDs. On theother [8] h a n 4 BBDs can be easily fabricated, but they offer poor performances, mainly from the point view of transfer efficiency. of [ 91 A novel two-step transfer CTD concept (combining the BBD and CCD principles)hasbeendescribedandexperimentally

8 to Advances in Electronics and Electron Physics. New York: Academic Press, 1975. W. S. Boyle and G. E. Smith, Charge coupled semiconductor devices, Bell Syst. Tech. J., vol. 49, pp. 587-593, Apr. 1970. F. L. J. Sangster and K. Teer, Bucket-brigade electronics-New possibilities for delay, timeaxis conversion, and imaging, IEEE J. Solid-state Circuits,vol. SC-4, pp. 131-136, June 1969. K. K. Thornber, Incomplete chargetransfer in IGFET bucketbrigade shift registers, IEEE Trans. Electron Devices,vol. ED-1 8, pp. 941-950, Oct. 1971. C. N. Berglund and H. J. Boll, Performance limitations of the IGFET bucket-brigade shift register, IEEE Trans. Electron Devices, vol. ED-19, pp. 852-860, July 1972. C. N. Berglund and K. K. Thornber,Incomplete transfer in charge-transfer devices, IEEE J. Solid-state Circuits, vol. SC-8, pp. 108-116, Apr. 1973. - A fundamental comparisonof incomplete charge transfer , in charge transfer devices, Bell Syst. Tech. J., vol. 52, pp. 147182, Feb. 1973. W. J. Butler, M. B. Barron, and C.McD. Puckette, IV, Practical considerations for analog operation of bucket-brigade circuits, IEEE J. Solid-state Circuits,vol. SC-8, pp. 157-168, Apr. 1973. D. D. Buss and W. M. Gosney, The effect of subthreshold leakage on bucket-brigade device operation, presented atthe Device Research Conf., Edmonton, Alta., Canada, June 1972.

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[ l o ] F. L. J. Sanster, Integrated bucket-brigade delay line using MOS tetrodes,PhiZips Tech. Rev., vol. 31, p. 266, Aug. 1970. [ l l ] L. Boonstra and F. L. J. Sangster, Progress in bucket-brigade charge-transfer devices, in IEEE Solid-state Conf., Dig. Tech. Papers, pp. 140-141, Feb. 1972. [12] W. P. Noble, Jr., Short-channel effects in dual-gate field effect transistors, in IEEE Int. Electron Device Meet., Tech. Dig., pp. 483-486, Dec. 1978. [13] L. G. Heller and H. S. Lee, Chargetransfer device modeling, Semicond. Silicon, pp. 814-828, 1973. [ 141 N. Weste and J. Mavor, MOST amplifiers for performing periph-

eral integrated-circuit functions, IEE J. Electron. Circuits Syst., vol. 1, pp. 165-172, Sept. 1977. [IS] V. A. Browne and K. D. Perkins, Buried-channel CCDs with submicron electrode spacings, in Proc. Int. Charge-CoupZed Devices Conf., pp. 100-105, Oct. 1974. , A nonoverlapping charge-coupling gate technology for [16] serial memory and signal processing applications, IEEE J. SolidState Circuits, vol. SC-11, pp. 203-207, Feb. 1976. [ 171 D. Sharma, J. Gautier, and G. Merckel, Negative dynamic resistance in MOS devices, ZEEE J. Solid-state Circuits, vol. SC-13, pp. 378-380, June 1978.

Charge-Transfer Noise Theory for Surface-Channel Charge-Coupled Devices

YASUHISA DMURA AND KUNIKI OHWADA

Abstract-The detailed expression of charge-transfer noisefor surfacechannel CCDs is derived from the surfacegeneration-recombination rate equation. Not only the charge fluctuation due to occupied interface states but also that due to unoccupied interface states are taken into account. The derived expression can explicitly predict the spectrum intensity dependences on the signal charge concentration and the clock frequency for various amounts of the fat-zero charge. The comparison between theory and experimental results shows good agreement over a wide range of signal charge concentration and clock frequency. It is shown that charge-transfer noise depends heavily on the ratio of the signal charge concentration to the clock frequencyandthe capture cross section in the absence of fat-zero charge. For the small ratio, the charge fluctuation is ruled by the transfer-process noise which is determined from the amount of unoccupied interface states. For the very large ratio, the storage-processnoise which isdeterminedfrom the interface state distribution over the band gap rules the charge fluctuation. Fat-zero charge hardly reduces the transfer-process noise for the small ratio. For the large ratio, the fat-zerochargeenhances the total transfer noise.

I. INTRODUCTION OISE ORIGINS have been analyzed so farinorder to apply charge-coupled devices to low-noise analog devices [ 11 , [2] . Thornber and Tompsett [3] have proposed that the charge-transfer noise is attributedmainlyto transferinefficiency, and that there is a correlation between charge fluctuations in each pair of adjacent charge packets. They classified charge fluctuations into the transfer-process noise which is due to correlation and the storage-process noise which is independent of correlation. They derived the noise spectrum formula
Manuscript received November 1, 1979; revised April 20, 1980. The authors are with Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashinoshi, Tokyo, 180 Japan.

which consists of the transfer-process noise spectrum and the storage-process noise spectrum. Noise spectrum characteristics were experimentally demonstrated for a high clock frequency (-1 MHz) [4], [SI. On the other hand,Carnes and Kosonocky [6] have estimated the storage-process noise and the transferprocess noise on thebasis of the surface generation-recombination theory [7] , [8]. They have considered that the transferprocess noise is onlydue to interfacestatesoccupied by a fat-zero charge. However, it can be considered, in fact, that not only occupied interface states butalso unoccupied interface states contribute t o the charge fluctuation during a transferin period and a transfer-out period. In this paper, an advanced theory on charge-transfer noise spectrum is presented as an explicit function of signal charge concentration,fat-zero charge concentration,andclock frequency surface-channel for charge-coupled devices. In this theory, charge-transfer noise is also classified into the storageprocess noise and the transfer-process noise. Those are derived fromthesurfacegeneration-recombinationrateequationon the basis of the Shockley-Read-Hall statistics. It is regarded thattransfer-process noise is notonlyduetotheoccupied interfacestatesbut also theunoccupiedinterfacestates.It is also regarded that the storage-process noise consists of the charge fluctuation with the signal charge under the electrode and the charge fluctuation due to the emission process during the transfer-out period. The comparison between the theory andexperiments is carried out over a widerange of signal charge concentration, fat-zero charge concentration, and clock frequency for the verification of the theory. Physical origins of charge-transfernoise,someeffectsattributed to energydependent profile of interface states, and noise dependence on the capture cross section are discussed in detail.

0018-9383/80/009-l.816$00.75 0 1980 IEEE