VALLIAMMAI ENGINEERING COLLEGE

SRM NAGAR, KATTANKULATHUR 603 203.

UNIVERSITY QUESTIONS (May2003 to May2010) Semester: III Semester ECE Prepared By: S.RAMESH, Senior Lecturer/ECE UNIT- I Subject Name: EC2203-Digital Electronics Year : 2010-2011 Odd Semester

MINIMIZATION TECHNIQUES AND LOGIC GATES PART-A

*- Repeated Question 1. If A & B are Boolean variables and if A=1 & A+B=0, Find B?
2. State DeMorgans theorem.*

3. Explain the term prime implicants. 4. Apply DeMorgans theorem to simplify A+B C. 5. Simplify A+AB+A+B. 6. Define Maxterm & Minterm. Give examples. 7. Prove that A+AB=A+B. 8. Mention any 2 applications of DeMorgans theorem. 9. Express F=A+BC as sum of Minterm. 10. If a manufacturer specifies the minimum logical 1 at a gate output a 4.0v and also specifies that any voltage down up to 3.6v will be considered as logical 1. Find the noise margin? 11. State two advantages of CMOS logic.* 12. Define noise margin.
13.

Determine the fan-out given IIH(max) =40A & IOH(max)=400A.

14. What are the advantages of Schottky TTL family? 15. What are the universal gates? 16. Define fan-in. 17. Draw the circuit diagram of a TTL NAND gate. 18. What are tri-state gates?
19. 20. 21. 23.

Realize f = AB+AB using minimum universal gates. Draw a tri-state inverter & its truth table. Write down fan-in & fan-out of a standard TTL IC. Draw the logic diagram for X= AB+BC.
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22. What is propagation delay of gate?

24.

Implement F= (AB+AB) (C+D) with only NOR gate.

25. Write the Boolean function of an XOR gate give its truth table. 26. What are open collector & totem pole outputs? 27. Draw the XOR logic using only NAND gates. 28. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1. 29. Show that a positive logic NAND gate is a negative logic NOR gate.
30.

Draw an active high tri-state buffer & write its truth table. PART-B

1. Find a minimal SOP representation for f(A,B,C,D,E)=m(1,4,6,10,20,22,24,26)+d(0,11,16,27)

using K-map method. Draw the circuit of the minimal expression using only NAND.
2. Prove that (x1+x2) (x1 x3 +x3) (x2 +x1 x3) = x1 x2.

(16) (8) (8) (16)

3. Express the switching function f (BA) = A in terms of Minterm.

4. Simplify the 5 variable switching function f(EDCBA)= m(3,5,6,8,9,12,13,14,19,22,24,25,30). 5. Simplify using K-map to obtain minimum POS expression (A+B+C+D) (A+B+C+D)

(A+B+C+D) (A+B+C+D) (A+B+C+D) (A+B+C+D). 6. Plot the expression on the K-map F(w,x,y) = (0,1,2,3,5,6) + d(2,4).

(16) (16)

7. Prove the perfect induction (i)A+AB=A (ii)A+AB=A+B (iii)A(A+B) =A (iv)A(A+B) =AB.(8)

8. Reduce the following function using K=map, f=ABC+ABC+ABC+ABC & realize using only NAND. (8) 9. List out the basic rules (laws) that are used in Boolean algebra expressions with example.*(8) 10. Write the steps for simplifying a logic expression using a K-map.
11.

(10)

(i) Simplify using K-map X=AB+ABC+ABC+ABC. (ii) Convert SOP to equivalent POS ABC+ABC+ABC+ABC+ABC. (iii) Apply DeMorgans theorem [(A+B+C) D]. (iv)Using Boolean rules & laws simplify Z= (A+B) (A+B). (16) Prove the following using DeMorgans theorem, AB+CD=((AB). (CD)) & (A+B) (C+D) =((A+B)+(C+D)). (8) Convert (A+B) (A+C) (B+C) into standard POS form. (8)

12.

13. 14.

Minimize the 4 variable logic function using K-map, f(A,B,C,D)= m(0,1,2,3,5,7,8,9,11,14). (10) (6)

15. Obtain the Canonical POS for F(A,B,C)=(A+B)(B+C)(A+C).

16. Using the K-map method obtain the minimal SOP & POS expressions for the function F(x,y,z,w) =(1,3,4,5,6,7,9,12,13). (10)
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17.

Apply DeMorgans theorem for the function {(A+B+C) D}. (3) (3)

18. Find the complement of A+BC+AB.

19. 20.

Reduce the following function using K-map technique F(A,B,C,D)= m(5,6,7,12,13)+ d(4,9,14,15). (8) Simplify the following expression using Boolean algebra F(x,y,z,) =m(3,5,7). (8) (8) (8) (8) (8)

21. Explain the working of a basic totem-pole TTL 2 input NAND gate.* 22. Explain the terms: Fan-in, Fan-out, Tri-state gates, & Propagation delay. 24. Draw the circuits of 2 input NAND & 2 input NOR gate using CMOS.* 25. Obtain 3 level NOR-NOR implementation of f (a, b, c, d, e, f) = (ab+cd) ef.
26. 27.

23. Explain the working of 2 input CMOS NAND gate. What are the characteristics of CMOS.(10)

Explain with a circuit the working of 3 state TTL gate.* (8)

Minimize f (A, B, C, D, E) =M (2, 4, 7, 9, 26, 28, 29, 31), implement the resultant function using NOR only. (16) (8) Implement the following function using a quad 2 input NOR gates, f= (AB+C).D. (8) Draw a TTL gate that gives an output (AB) & explain its operation. (8)

28. Explain the working of CMOS logic gates.

29. 30.

31. Draw the symbol, truth table & the equation of the 3 basic gates & 2 universal gates and realize all the 5 gates using either of the universal gates. (16) 32. Enumerate the precautionary measures to be considered while handling CMOS devices.* (5) 33. List out & explain the data sheet parameters. 34. Implement the expression (i) AB+BCD+EFGH gates.
35.

(11) (ii) (A+B) (C+D+E) (F+G+H+I) with logic

Simplify & draw logic diagram for the expression, Y= C.B.A+ C.B.A+ C.B.A. (4) (8) (8)

36. Draw the logic symbol of X-NOR gate & give its truth table. 37. Explain the operation of 3 input TTL NAND gate with required diagram & truth table. 38. Explain the operation of CMOS NAND & NOR gates with the circuits & truth table.
39.

Compare & contrast the features of TTL & CMOS logic families.* (8) (6) technique f(ABCD)=

40. Express the Boolean function F=XY+XZ in product of maxterm.

41.

Reduce

the

following

function

using

K-map

(0,3,4,7,8,10,12,14)+d(2,6).
3

(10)
42. 43.

Simplify the following function using Quine McCluskey method F(ABCD)= (0,2,3,6,7,8,10,12,13) (16) Minimize the term using Quine McCluskey method & verify the result using K-map method M(0,1,4,11,13,15)+ d(5,7,8). (12) (4) Implement the following function using NOR gates. (8) UNIT II COMBINATIONAL CIRCUITS PART-A

44. Express the Boolean function as (i)POS form (ii)SOP form D=(A+B)(B+C)
45.

Output=1 When the inputs are m (0,1,2,3,4)&Output=0 When the inputs are m (5,6,7)

*- Repeated Question 1. What is a De-Mux? 2. What is combinational circuit? Give examples. 3. Draw the flow diagram of Gray to Binary conversion. 4. Represent a half adder in block diagram form & also its logic implementation. 5. What are the major categories of logic circuits? 6. Write the Boolean expression for the output of the system. 7. Write the truth table of a 4:1 Mux. 8. Express Gray code 10111into binary numbers.
9. Convert (367)10 into Excess 3 Code.

10. Suggest a solution to overcome the limitation on the speed of an adder. 11. Differentiate decoder from demultiplexer. 12. Write an expression for borrow & difference in a full subtractor circuit. PART-B
1. State the condition for B= I2 in Boolean expression B= I0 S0 S1 + I1 S0 S1+ I2 S0 S1+ I3 S0 S1.

What is the combinational logic circuit realized by the above Boolean expression? 2. State the condition to check the equality of two n-bit binary numbers A & B. 3. Design a full adder & a full subtractor. 4. Draw the block diagram of a 2s complement adder/subtractor. 5. Design & explain the working of a 1 to 8 De-Mux. 6. Draw a circuit of 2 to 1 Mux & 1 to 2 De-Mux.

(16) (8) (10) (8) (8) (4)

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7. Design & explain the following circuits, (i) Comparator (ii) 4 to 1 Mux. 8. Design a look ahead carry generator. 9. Realize F(w, x, y, z)= (1,4,6,7,8,9,10,11,15) using 8 to 1 Mux. 10. Design a BCD to Gray code converter. Uses dont care. 11. Explain carry look ahead adder circuit.* 12. Design & explain the working of a decoder.
13.

(16) (8) (8) (10) (8) (8)

Design & explain the working of Gray to BCD converter.* (8)

14. What is the simplest logic circuit for a decoder that produces a 1 output when BCD input is 0000? (8) 15. Draw the diagram & explain 1 to 16 De-Mux circuit. 16. Implement full adder using 2 half adder. 17. Draw & explain the BCD adder circuit. 18. Design a 5 bit comparator using single IC7485 & a gate. 19. Implement the function with a multiplexer F(A,B,C, D) =(0,1,3,4,8,9,15). * 20. Explain the operation of a 4 bit magnitude comparator. 21. Explain even parity checker.
22.

(8) (8) (8) (8) (6) (10) (6)

Explain the procedure for converting binary to Gray code number & Gray to binary number with example. (8) Implement full subtractor using demultiplexer. (10) Implement the given Boolean function using 8:1 multiplexer F(A,B,C) =(1,3,5,6).* (6) Derive the equation for a 4-bit look ahead carry adder circuit.* (6) Draw & explain the block diagram of a 4-bit serial adder to add contents of two registers.

23. 24. 25. 26.

(10)
27.

Multiply (1011)2 by (1101)2 using addition and shifting operation also draw block diagrams of the 4 bit by 4 bit parallel multiplier. (8) Design & implement the conversion circuits for Binary code to Gray code. (8)
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28.

UNIT- III

SEQUENTIAL CIRCUIT PART-A

1. What is the condition on JK FF to work as D FF? 2. Convert a D FF into a T FF. 3. Write the characteristic equation of a JK FF. 4. Derive T FF from JK FF. 5. Draw the logic diagram of SR FF. 6. What is meant by maximum allowable clock skew? 7. What is a sequential circuit? Give an example. 8. Name two sequential switching circuits. 9. What is the drawback of SR FF? How is this minimized? 10. What is an asynchronous sequential circuit? 11. How does a JK FF differ from an SR FF in its basic equation? 12. Draw a scale of 8-bit ripple counter. 13. Define synchronous counter. 14. What is a sequence generator? 15. If a SISO shift register has N stages and if the clock frequency is f, what will be the time delay between i/p & o/p?
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16. Draw the timing diagram of 4-bit ring counter. 17. Draw a 2-bit ripple counter &Convert this into a 2-bit ring counter. 18. Classify the registers with respect to serial & parallel input output. 19. Draw the logic symbol and truth table of a D FF 20. What is race around condition? 21. Convert T-FF into an SR-FF. Draw the circuit. 22. Draw the state diagram of MOD-10 counter. 23. Draw the gate level logic diagram of MS-JK-FF. 24. Write down the characteristic equation for JK flip-flop.
25.

Distinguish between synchronous & a synchronous sequential circuits.

26. Mention any 2 differences between the edge triggering & level triggering. 27. What is meant by programmable counter? Mention its applications.

PART-B
1. Explain the working Master/Slave JK FF.*

2. Design & explain the working of an UP-DOWN ripple counter.

3. Explain the working of BCD ripple counter with timing diagrams.*

4. Design and explain the working of a MOD-11 counter. 5. Design and explain the working of a synchronous MOD-3 counter. 6. Design and explain the working of a synchronous MOD-7 counter. 7. Write notes on state minimization. 8. Design a synchronous counter with states 0, 1, 2, 3, 0, 1,...using JK FF. 9. Draw an asynchronous decade counter & explain its operation with neat waveforms. 10. Draw a 3-bit reversible counter & explain its operation with neat waveforms.
11. 12.

Draw a 6-stage ring counter & explain its operation. Mention the use of the counter.

Draw a 5 FF shift counter, its truth table & waveforms. Explain its operation as a decade counter.

13. Draw a 4-bit SISO shift register & draw its waveforms 14. Draw the 4-bit Johnson counter & explain the operation. 15. Draw a 8-bit SIPO shift register & Explain the operation.
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16. Design a 3-bit binary counter using T FF that has a repeated sequence of 6 states. 000-001-010011-100-101-110. Give the state table, state diagram & logic diagram. 17. Draw the clocked RS FF & Explain with truth table. 18. Draw the logic diagram for a 5- bit serial load shift register using D FF & explain. 19. Draw the logic diagram for a 4- bit parallel load recirculating shift register. & explain. 20. Design a 3- bit synchronous counter using JK FF. 21. Design a 3- bit binary counter & write the truth table & o/p waveform 22. Design a 5-bit shift register using 5 Master slaves FF. 23. Draw the logic diagram of a D-FF using NAND gates & explain. 24. With a neat circuit diagram explain a universal shift register.* 25. Design a 3 bit asynchronous ripple counter using TFFs & explain its operation. 26. How will you convert a D flip-flop into JK flip-flop? 27. What is meant by universal shift register? Explain the principle of operation of 4-bit universal shift register. 28. Write down the characteristic table for JK flip-flop with NOR gates. 29. Design a 2 bit synchronous Up/Down counter.
30.

Realise JK flip-flop using SR flip-flop. -----

UNIT- IV
1. What is an EPROM?

MEMORY DEVICES PART-A

2. Which memory is called volatile? Why? 3. Draw the basic dynamic memory cell. 4. What is meant by static & dynamic memories? 5. How is the individual location in an EPROM programmed (or) erased? 6. Explain static memory? 7. What is a RAM? 8. Mention 2 types of erasable PROM. 9. What is memory decoding? 10. Whether ROM is classified as a non volatile storage device? Why? 11. Write the advantage of EPROM over a PROM.
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12. Draw the logic diagram of memory cell. 13. What is a combinational PLD? 14. What is write cycle time? 15. Explain EPROM? 16. List the advantages of PLDs. 17. Explain write operation with an example. 18. Draw block diagram of Dynamic RAM cell. 19. What is a memory cycle?
20.

Compare features of PROM, PAL and PLA.

21. Compare & contrast static RAM & dynamic RAM. 22. What is PAL? How does it differ from PLA? 23. What are the advantages of static RAM compared to dynamic RAM? 24. What is meant by memory expansion? Mention its limit. PART-B
1. Write notes on ROM, EPROM, and PLA.

(10) (8) (8) (4) (8) (8) (10)

2. Draw a RAM cell and explain its working.

3. Describe the RAM organization.

4. A Bipolar RAM chip is arranged as 16 words. How many bits are stored in the chip?
5. Write note on MOSFET RAM cell. 6. Write note on Dynamic RAM cell. 7. How can one make 64X8 ROM using 32X4 ROMs? Draw such a circuit & explain.

8. Draw a dynamic RAM cell & explain its operation. Compare its simplicity with that of NMOS static RAM cell, by way of diagram & operation. (16)
9. Illustrate the concept of 16X8 bit ROM arrangement with diagram.

(10) (10)

10. Explain the basic structure of a 256X4 static RAM with neat diagram.
11.

Describe the typical ROM internal organization with neat diagram. (8) (6)

12. Elaborate the single fused PROM cell with clear sketch.
13. 14.

Categories RAM & ROM and explain in detail. (16)

Explain the following terms: Dynamic memory, volatile storage, Field programmable, Mask programmable. (16) (16)

15. Write short notes on RAM, types of ROMs.

16.

Implement the following 2 Boolean functions with PLA.(i) F1(A,B,C)=(0,1,2,4) (ii) F2(A,B,C)= (0,5,6,7). (16) (16)

17. Draw the block diagram of a PLA device & briefly explain each block.
18.

Design a 16bit ROM array & explain the operation. (8) (6)

19. Write short notes on FPGA.*

20.

Explain (i) Memory decoding (ii) Explain the various ROM organizations and give the uses for each type. (10) A combinational circuit defined by functions F1(A,B,C)=(3,5,6,7) and F2(A,B,C)= (0,2,4,7).Implement the circuit with a PLA having 3 inputs, 4 product terms and 2 outputs. (16) (8) (8)

21.

22. Give the classification of semiconductor memories. 23. Write short notes on EPROM and EEPROM.

24. Explain the read cycle and write cycle timing parameters with the help of timing diagrams. (8)
25.

Implement the following Boolean functions with PLA.(i) F1(A,B,C)=(0,1,2,4) (ii) F2(A,B,C)= (0,5,6,7) (iii) F3(A,B,C)= (0,3,5,7). (16) Design a combinational circuit using ROM. The circuit accepts a three bit number & outputs a binary number equal to the square of the input number. (16) (8)

26.

27. Explain the principle of operation of Bipolar SRAM cell.

28. A combinational circuit is defined as the functions F1=ABC+ABC+ABC & F2=ABC+ABC+ABC. Implement the digital circuit with a PLA having 3 inputs, 3 product terms and 2 outputs. (8) -----

UNIT- V

SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS PART-A

1. What is a fundamental mode sequential circuit? 2. Define cycle. 3. What is an Asynchronous Sequential Circuit?
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4. Define a stable state. 5. What is the cause for essential Hazard? 6. Define static Hazard? 7. When do Hazards occur? 8. Define state assignment?
9. What is race?*

10. What is a flow table? 11. What is excitation table?

12.

Define Hazard?*

13. Explain Dynamic Hazard. 14. Define static Hazard. How it can be avoided? 15. What are Hazards? 16. Compare the ASM chart with a conventional flow chart. 17. Draw block diagram for Moore model. 18. What are the hazard free digital circuits? PART-B 1. Design an asynchronous sequential circuit with 2 i/ps X & Y and with one o/p Z. Whenever Y is 1, i/p X is transferred to Z. When Y is 0, the o/p doesnt change for any change in X. Use the SR latch implementation of the circuit. 2. Write notes on the following giving one example for each. (i).Stable state Cycle (iv) races. (ii).Unstable state (iii)

3. Obtain the Primitive flow table for an asynchronous circuit that has 2 i/ps X and Y & o/p Z. An o/p Z =1 is to occur only during the i/p state XY=01 & then if and only if the i/p state XY=01 is preceded by the i/p sequence XY=01, 00, 10, 00, 10, 00. 4. Explain Races and hazards with suitable examples. 5. Design a circuit with primary i/p A & B to give an o/p Z=1, when A becomes 1 if B is already 1. Once Z=1 it will remain so until A goes to 0.Draw waveform diagram, total state diagram, Primitive flow table for designing this circuit. (16) 6. Discuss methods of designing race free & Hazard free circuits with examples.* 7. Draw the fundamental mode asynchronous circuit & explain in detail. (8)
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8. Illustrate Pulse mode asynchronous circuit. 9. Define following terms i) Critical race ii) Non critical race iii) Flow table iv) Hazard 10. Illustrate mixed operating mode sequential circuit model. 11. Write note on Hazard. 12. What are hazards? Explain in detail with a suitable example?*

(8)

(8) (8) (16)

13. The circuit has 2 i/ps T (toggle) & C (clock) & one o/p Q. The o/p state is complemented if T=1 & C changes from 1 to 0(-ve edge triggering) otherwise, under any other i/p condition, the o/p Q remains unchanged. Derive the primitive flow table and implication table. (16) 14. Design an asynchronous circuit using JK FF that will produce o/p only the first pulse received and will ignore any other pulses. (16) 15. Design an asynchronous circuit that will o/p only the first pulse received whenever a control i/p is asserted from low to high state. Any further pulses will be ignored. (16) 16. Design T-FF giving the flow table, state table, state assignment, excitation table and excitation map. (16) 17. Design a three bit binary counter using T flip-flops. 18. Design a negative-edge triggered T flip-flop. (16) (16)

19. What are called as essential hazards? How does the hazard occur in sequential circuits? How can the same be eliminated using SR latches? Give an example. (16)

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