Low Density Parity Check decoder Hardware Implementation

Ruchi Rani (2008EEE2225) Under guidance of Prof. Prof Jayadeva Dr.Shankar Prakriya

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LDPC code
Linear block code which has very sparse parity check matrix Random codes: based on random graphs Simple iterative decoding

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Type of LDPC Codes

Regular

H contains exactly Wc 1's per column and exactly Wr = Wc 1' per row, 1's

Irregular
If the number of 1's per column or row is not constant

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Tanner Graph
N = length of code = 10 K = number of check nodes = 5 M = N K = number of message bits = 5

c0

c1

c2

c3

c4 Check nodes

Variable nodes v0 0
4

v1 1

v2 2

v3 v4 3 4

v5 5

v6 6

v7 v8 7 8

v9 9

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Communication Model

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Encoding

Code = message . G Where G is generator matrix corresponding to previous parity check matrix

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Gaussian Channel
c = binary vector t = transmitted signal vector(using BPSK ) v = gaussian noise vector r=t+v Posterior probability of detection

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Architectures

1. Serial Architecture 2. Parallel Architecture 3. S 3 Semi P ll l A h Parallel Architecture

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reduces the complexity of the interconnect reduces total area of the design all symbol nodes must be updated and the messages stored in memory before the update of the check nodes starts h k d decoding process very slow reducing the total throughput requires large memories to store all the messages addressing of the memories is another p g problem

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mapping directly the symbol and check nodes in the Tanner graph effcient from a speed point of view is demanding in terms of area, due to the interconnect between the processing elements

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trade-o between the routing problem typical of the parallel architecture and the reduction of the throughput f th th h t characteristic of the serial architecture suffer form memory access conflicts. These conflicts occur when multiple data accesses per cycle are required for the same memory bank. These conflicts are difficult to avoid if the code implemented is of random nature but can be avoided for structured codes

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Decoding
Hard D di H d Decoding
Bit-Flipping

Soft Decoding
Message Passing Algorithms Probability Domain Log Domain Min-Sum Algorithm g

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MIN SUM ALGORITHM

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MATLAB Simulation

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FPGA Flow

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ENCODER

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DECODER

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BIT FUNCTIONAL UNIT

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CHECK FUNCTIONAL UNIT

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Simulation Waveforms(Encoder)

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Simulation Waveforms(Decoder)

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Post-Route Post Route Simulation Waveforms(Decoder)

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Timing and Area Analysis

ENCODER
Selected Device : 2vp30ff896-5 Number of Slices: 230 out of 13696 1% Number of Slice Flip Flops: p p 207 out of 27392 0% Number of 4 input LUTs: 390 out of 27392 1% Number of IOs: 11 Number of bonded IOBs: 7 out of 556 1% Number of GCLKs: 1 out of 16 6%Timing Summary:--------------Speed Grade: -5 Minimum period: 8.629ns (Maximum Frequency: 115.882MHz) Minimum input arrival time before clock: p 8.599ns Maximum output required time after clock: 3.997ns Maximum combinational path delay: No path foundTiming Detail:-------------All values displayed in nanoseconds (ns) p y ( )
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DECODER
Selected Device : 3s500efg320-5 Number of Slices: 3107 out of 4656 66% Number of Slice Flip Flops: 941 out of 9312 10% Number of 4 input LUTs: 5762 out of 9312 61% Number of IOs: 18 Number of bonded IOBs: 14 out of 232 6% Number of BRAMs: 1 out of 20 5% Number of GCLKs: 1 out of 24 4%Timing Summary:--------------Speed Grade: -5 Minimum period: 21.855ns (Maximum F (M i Frequency: 45 755MH ) Minimum 45.755MHz) Mi i input arrival time before clock: 9.973ns Maximum output required time after clock: 12.171ns Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)========================== ============================ ===================Timing constraint: Default period analysis for Clock 'clk' Clock period: 21.855ns (frequency: 45.755MHz) Total number of paths / destination ports: 781984991 / 1427

Synthesis Report(Hardware Used)

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References

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Thanks!

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