DESIGN AND SIMULATION OF BAUD RATE GENERATOR

A Mini Project Report submitted to JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY Hyderabad (A.P) In Partial fulfillment of requirements for the award of the degree of BACHELOR OF TECHNOLOGY In Electronics and Communication Engineering By

Ganta.Amulya Kokkonda.Swathi Madgula.Lavanya Bogavelly.Rahul

(08UN1A0415) (09UN5A0402) (08UN1A0430) (08UN1A0406)

AFFILIATED TO JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

VARADHA REDDY COLLEGE OF ENGINEERING

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Ananthasagar, warangal

CERTIFICATE
This is to certify that the dissertation work entitled DESIGN AND SIMULATION OF BAUD RATE GENERATOR is the work done by Ganta.Amulya, Kokkonda.Swathi, Madgula.Lavanya, and Bogavelly.Rahul submitted in partial fulfillment for the award of BACHELOR OF TECHNOLOGY in Electronics and Communications Engineering at Varadha Reddy College of Engineering affiliated to Jawaharlal Nehru Technological University, Hyderabad .

Dr.G.Ramana Rao
Principal

N.Govardhan
Head of ECE Department

N.Govardhan
Asst. Professor

( INTERNAL EXAMINER )

(EXTERNAL EXAMINER )

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ACKNOWLEDGEMENT

The satisfaction and euphoria that accompany the successful completion of any task would be incomplete without the mentioning of the people whose constant guidance and encouragement made it possible. We take pleasure in presenting before you, our project, which is result of studied blend of both research and knowledge. We express our earnest gratitude to our Principal, Dr.G.Ramana Rao and internal guide and Head of the department, ECE Mr. N.Govardhan, for their constant support, encouragement and guidance. We are grateful for their cooperation and their valuable suggestions. Finally, we express our gratitude to all other members of faculty who are involved either directly or indirectly for the completion of this project.

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DECLARATION
We, the undersigned, declare that the mini project entitled DESIGN AND SIMULATION OF BAUD RATE GENERATOR, submitted in partial fulfillment for the award of Bachelor of Technology Degree in Electronics and Communications Engineering, to Jawaharlal Nehru Technological University, is the work carried out by us.

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ABSTRACT
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Design and simulation of BAUD RATE GENERATOR Aim: The main aim of this project is to generate baud rate for given frequency. Block Diagram:

DESCRIPTION: The baud rate of a data communication system is the number of symbols per second transferred. A symbol may have more than two states, so it may represent more than one binary bit (a binary bit always represents exactly two states). Therefore,the baud rate may not equal the bit rate. REQUIRED COMPONENTS: FPGA XILINX ISE

REQUIRED SKILL SET: Knowledge on Digital design. Knowledge on VHDL Programming.

CONTENTS
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ACKNOWLEDGEMENT DECLARATION ABSTRACT LIST OF FIGURES Chapter 1: INTRODUCTION TO VHDL 1.1: VHDL Introduction 1.2: Scope and Role of VHDL in the Design Process 1.3: VHDL Design Flow 1.4: Flow Diagram of VHDL Design Flow 1.5: Need for VHDL 1.6: VHDL Synthesis 1.7: Concepts of VHDL Chapter 2: DESCRIPTION ABOUT PROJECT (STATE MACHINE) Chapter 3: SOURCE CODE Chapter 4: TEST BENCH Chapter 5: OUTPUT WAVEFORMS Chapter 6: SCOPE Chapter 7: CONCLUSION BIBILOGRAPHY

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17 32 36 41 42 43

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LIST OF FIGURES

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Fig: 1.1 Design Flow Fig: 2.1 Baud rate generator Fig: 2.2 Transmitter state diagram Fig: 2.3 Receiver state diagram Fig: 3.1 Block Diagram of Top Level Module Fig: 3.2 RTL Schematic Fig: 3.3 Technological Schematic Fig: 5.1 Simulation Result Fig: 5.2 Top level baud receiver and transmitter Waveform Fig: 5.3 Baud rate waveform Fig: 5.4 Baud Transmitter waveform Fig: 5.5 Baud Receiver waveform

03 12 13 15 17 21 22 36

37 38 39 40

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