n

Depletion
regions
n-channel
Metal electrode
Insulation
(SiO
2
)
p
S D G
p
+
D S
G
Circuit symbol
for n-channel FET
(b)
D S
n-channel
n
Gate
Drain
Source
G
Basic structure
p
+
p
+
n
Depletion
region
S D
n-channel
G
Cross section
n
Channel
thickness
p
+
p
+
(a)
From Principles of Electronic Materials and Devices, Second Edition, S.O. Kasap ( McGraw-Hill, 2002)
http://Materials.Usask.Ca
Fig. 6.27: (a)The basic structure of the junction field effect transistor
(JFET) with an n-channel. The two p
+
regions are electrically
connected and form the gate. (b) A simplified sketch of the cross
section of a more practical n-channel JFET.
Idea: control the ow of majority
carriers from source to drain by
means of a gate voltage
2a

W
2(V(x) V
G
)
eN
d
Width of depletion
regions

W = a V
D
V
G
=
ea
2
N
d
2
V
P
Pinch-off voltage V
p

h(x) = a 1
V(x) V
G
V
P





0


I
D
=
2 Z
transverse
width

h(x)

resistivity

dV(x)
dx
x
h(x)
a
depletion region
depletion region
0 L
D
=5 V

I
DS
= G
0
V
P
1
3
+
V
G
V
P
+
2
3

V
G
V
P
[
\
|

)
j
3/ 2
|
|
|
|
|
|
|
|

(V
D
V
G
>V
P
)

I
D
x =
2aZV
P

V(x)
V
P
+
2
3

V
G
V
P
[
\
|

)
j
3 / 2

2
3
V(x) V
G
V
P
[
\
|

)
j
3 / 2
|
|
|
|
|
|
|
|

I
D
= G
0
V
P
V
D
V
P
+
2
3

V
G
V
P
[
\
|

)
j
3 / 2

2
3
V
D
V
G
V
P
[
\
|

)
j
3 / 2
|
|
|
|
|
|
|
|
(V
D
V
G
<V
P
)


1
G
0
=
L
2aZ
Open channel
resistance

=G
0
V
P
/3

El
p0
=V
D
V
P
depletion region
depletion region
Load line
=5 V
18

V
D
(t) =V
DD
R
D
I
D
(t)

1
r
GS
=
dI
D
dV
G
G
0
1
V
G
V
P









A
V
=
dV
D
dV
G
=
dV
D
dI
D
dI
D
dV
G
=
R
D
r
GS
Voltage amplication:
In our example G
0
= 0.510
-2

-1
and 1/r
GS
= 0.210
-2

-1.

With R
D
=5000 we have
A
V
=10.
where
An inversion layer
appear at the surface at
the threshold voltage
V
T
.
= CV

Q
A
=

i
d
V

Q
A
2
s
eN
a
V
d
p
n
+
n
+
p-type substrate
Source
S
Drain Gate
G D
Metal electrodes
SiO
2
insulation
Heavily doped
n-region
Blk
G
D
S
Blk Bulk (Substrate)
Depletion layer
Fig. 6.36: The basic structure of the enhancement MOSFET and its
circuit symbol.
From Principles of Electronic Materials and Devices, Second Edition, S.O. Kasap ( McGraw-Hill, 2002)
http://Materials.Usask.Ca
Idea: an electrically controlled
potential barrier
Positive gate voltage

V
GS
<V
T

V
GS
>V
T

V
DS
<V
GS
V
T

V
GS
>V
T

V
DS
=V
GS
V
T

V
GS
>V
T

V
DS
>V
GS
V
T

I
DS
=
V
GS
V
T
R
AP',nchannel
K V
GS
V
T
( )
2

I
DS
=
V
GS
V
T
R
AP',nchannel
K V
GS
V
T
( )
2
Linear regime
Saturation regime
E
c

E
v

E
F

E
i

M O S

M

S

E
i
E
F
= e
F
= kTln
N
a
n
i
An inversion layer barely begins to form at the surface of the semiconductor
when the sign of E
i
-E
F
there has the opposite sign than in the bulk. Strong
inversion begins when one has E
i
-E
F
= -2
F
at the surface, or (0) =2
F
. This
condition determines the threshold voltage of the MOSFET.
x
E
i

M O S
E
c

E
v

E
F

eV
T

x
-e(x)
0
Inversion layer
depletion region
+|Q
s
|
-|Q
s
|
-|Q
d
|
-|Q
n
|

E
ox
=
| Q
s
|

ox
0
Poisson equation

d
2
(x)
dx
2
=
e

s
[ p
0
(e
e(x)/ kT
1) n
0
(e
e(x)/ kT
1)], () = 0

Q
s
=
s
E(0) = 2p
0

s
kT (e
e(0)/ kT
+
e(0)
kT
1) +
n
0
p
0
(e
e(0)/ kT

e(0)
kT
1)






1/ 2

V
T
ideal
= 2
F
+
| Q
s
| t
ox

ox
(0)= 2
F
2
F
+
2
s
eN
a

F
t
ox

ox
Threshold voltage
(0) (volt)
Q
s
(
C
/
c
m
2
)

V
FB
Flat band voltage
(uncharged capacitor)

=
m

s
Difference between metal
and semiconductor work
functions

Q
i
Effective
interfacial
charge

C
i

V
T
=V
FB
+V
T
ideal
E
i

M O S
E
c

E
v

E
F

x
-e(x)
+
+
+
+
+
+
+

m
<
s

The threshold voltage is then

Band bending in the semiconductor
can be produced even in the absence
of a gate voltage by
(1) Different work functions in the
metal and the semiconductor
(2) Interfacial charges
To restore at band conditions we
need to apply a potential V
FB
to the
gate:


Q
n
(x) = C
ox
V
G
V
FB
2
F
V(x)
2e
s
N
a
[2
F
+V(x)]
Q
d
(x)

C
ox












C
ox
[V
G
V
T
V(x)]


I
D
=
n
Z Q
n
(x)
dV(x)
dx
I
D
=

n
ZC
ox
L
K

(V
G
V
T
)V
D

1
2
V
D
2









V
G
= V
FB
Corrections
due to interface
charges,
m

s

etc.

Q
s
(x)
Q
d
(x)+Q
n
(x)

C
ox
+
s
(x)
2
F
+V(x)
potential at the
semiconductor surface

Fixed charge in
depletion region
Mobile charge in
inversion layer
x
V(0)=0 V(L)=V
D

Q
d
(x)
Q
n
(x)


Setting V
D
=V
G
V
T
we get I
DS
=

n
ZC
ox
2L
K / 2

(V
G
V
T
)
2
=Saturation current
Plot I
D
(V
D
,V
G
) for a n-channel Si MOSFET at 300 K with the following data
Oxide thickness: d=200 A
Surface electron mobility:
n
=1000 cm
2
/V.s
Width of channel: Z=100 m
Length of channel: L=5 m
Acceptor concentration: N
a
= 10
15
cm
-3
Interfacial charge density Q
i
= 510
10
e C cm
-2
.
I
D
(mA)
V
D

V
G
=5V
V
G
=4V
V
G
=3V
V
T
~0.5V
Linear
regime
Saturation
regime
G
D
S
V
DD

V
out

V
in

R
V
out

V
in

V
T

V
DD

V
low

dV
out
dV
in
=1
Logical 1
Logical 0

V
DS
= V
DD
RI
D

I
D
= K (V
GS
V
T
)V
DS

1
2
V
DS
2






, 0 < V
DS
< V
GS
V
T
I
D
=
K
2
(V
GS
V
T
)
2
, V
DS
> V
GS
V
T
> 0
Analysis: When V
in
is high (~V
DD
) the
MOS channel is on and V
out
=V
L
~0. When
V
in
is low the MOS channel is off and
V
out
=V
H
=V
DD
.
V
GS
=V
in

V
DS
=V
out

=V
in

Analysis
I. PMOS on, NMOS off V
out
=V
DD

II. PMOS linear, NMOS in saturation

III. PMOS and NMOS in saturation
IV. PMOS in saturation, NMOS linear
V. PMOS off, NMOS on V
out
=0
NMOS

V
GS
N
=V
in

V
DS
N
=V
out
PMOS

V
GS
P
=V
in
V
DD

V
DS
P
=V
out
V
DD
V
DD
-V
TP

V
out

V
in

V
TN

V
DD

Logical 1
Logical 0
V
DD

V
DD
/2
0
I II
III
IV V
I
D

(
m
A
)

V
DD

D
S
V
DD

V
in

V
out

PMOS
NMOS
S
G
G
PMOS NMOS
V
out

V
GS
P
=V
DD
V
in

V
GS
N
=V
in
Exercise: calculate V
out
vs V
in
in region IV
A B NOR
0 0 1
0 1 0
1 0 0
1 1 0
A B NAND
0 0 1
0 1 1
1 0 1
1 1 0
N N
P
P
P P
N
N
A B XOR
0 0 0
0 1 1
1 0 1
1 1 0
A
B
Note: All logical gates can be built from the NAND alone.
Access
transistors
P P
N N
(W=1, B=0)
(W=0,B=0)
(W=1,B=1)
(W=0,B=1)
V
DD

0,1
0,1
NMOS
(pass transistor)
W
B
MOS
capacitor
1
0
Idea: Store negative charge in the oating gate. This charge increases
the threshold voltage of the MOSFET and allows electrical read-out.
Erase
To put electrons on the oating gate use the hot carrier effect.To extract
them, use Fowler-Nordheim tunneling.
Write
e
-
e
-
e
-
e
-

Strong electric eld

Array of MOS
photodiodes (pixels)
V
1

V
2

V
3

t
t
1
t
4
t
3
t
2
t
7
t
6
t
5
t
9
t
8

12 23 31
G
1

G
2

G
3

3-phase clocking
sequence
+++ +++ +++ +++
p-Si