Вы находитесь на странице: 1из 7

Z80 CPU architecture

The Z80 CPU is an 8-bits processor witch was constructed in the beginning of July 1976, with ideas from Intel 8080. that was before the Intel-Company started, and made a better 8080-processor, with backward compatibility and with a lot of new instructions. The interesting thing about the Z80-CPU is that you can all ready see the beginning to: what was about to become pipelined constructions. The Z80 CPU became fast a very popular Processor for small systems - especially later when the processor fall in prize. Now a Z80-processor costs about a dollar, and many are using it of tradition, witch make it even more popular, if you look at the homepage of Zilog, then you will see that today there is a lot of new variants of chips for Z80 systems, used in a wide range of applications.

Processor architecture:
The Z80 CPU has a very interesting architecture. First of all it has "fetch/execute overlapping", witch means that it's possible to get (fetch) next instruction from memory while the first instruction are executed. This system are also used in the Intel 8080, and other processors from that time. Another thing that are typical from that time is that those processors are CISC-processors, and that they have variable instructions length. The Z80 CPU instructions-length can be from one to four bytes long. To increase the Z80 CPU speed most instructions are only one byte long. 252 instructions are one byte, the rest are 2, 3 or 4 bytes long.

Fig 1. Fetch/execute overlap.


Another aspect in processor- architecture are the number of internal registers, and if they are dedicated to special purposes. The Z80 CPU internal organization is made visible on the figure below:

Fig 2. Z80 CPU internal organization.


It shows on the figure: 20 - 8-bits registers, and 4 - 16-bits registers. The four 16-bits registers are: PC (Program Counter), SP (Stack Pointer) and the two Index-registers, IX and IY. The 20 - 8-bit registers are grouped into two banks with 10 registers. 8 witch can be used together as 4 - 16-bit register-pairs, an 8-bit accumulator and a 8-bit flag-register. The Accumulator A, are used for all calculations. The F-register (flags) are used to determine if the result is positive, negative, zero etc... The Register-pairs BC and DE are mostly used for counters and storage of part-results. The Register-pair HL can be used in a wide range of instructions mostly as addressing (pointing to memory). The forgotten registers W and Z are only used for internal operations in the processor, like jump to new addresses. (The CPU can only transfer 8 bits at a time, so to transfer (load) a 16-bit address, it will first store it in WZ) . The registers B, C, D, E, F, H, L, W and Z can be changed very fast with B', C', D', E', F', H', L', W' and Z', with the instruction EXX. For this purpose a MUX is used, witch is the fastest way to change the value in 9 registers with 9 others. The A and F are switched with A' and F' with the instruction EX AF,AF'. This finesse are mostly used with interrupt routines, so that the main program are using the main set of registers and the interrupt routine are using the EXX registers, this speeds up the interrupt routine, which can be important in embedded applications. The Z80 CPU has with Intel, inspired to the global processor development and are still alive today more than 20 years after it's construction and it seems like it will continue to live many years more.

Zilog Z80 microprocessor architecture


Memory Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte Program memory - program can be located anywhere in memory. Some jump and all call instructions use 16-bit addresses - they can be used to jump anywhere within 64 KB. Some conditional jump instructions can be used to jump within +129 - -126 bytes from the next instruction. Data memory - the processor can access data anywhere in the memory. Word data can be located at odd or even byte boundaries. Stack memory can be placed anywhere in memory. The stack grows from the top to bottom. Reserved locations: y y y First 64 bytes - contains interrupt entrance points for 8080-compatible interrupts. This area should only be reserved if the CPU is using interrupt mode 0. 0038h - contains entrance point for maskable interrupts when CPU is in interrupt mode 1. 0066h - contains entrance point for non-maskable interrupt.

Interrupts
Program, data and stack memories occupy the same memory space. The total addressable memory size is 64 KB. 16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte Program memory - program can be located anywhere in memory. Some jump and all call instructions use 16-bit addresses - they can be used to jump anywhere within 64 KB. Some conditional jump instructions can be used to jump within +129 - -126 bytes from the next instruction. Data memory - the processor can access data anywhere in the memory. Word data can be located at odd or even byte boundaries. Stack memory can be placed anywhere in memory. The stack grows from the top to bottom. Reserved locations: y y y First 64 bytes - contains interrupt entrance points for 8080-compatible interrupts. This area should only be reserved if the CPU is using interrupt mode 0. 0038h - contains entrance point for maskable interrupts when CPU is in interrupt mode 1. 0066h - contains entrance point for non-maskable interrupt.

Interrupts
The processor has the following interrupts: INT is a maskable hardware interrupt. This interrupt can be enabled/disabled using EI/DI instructions. When an interrupt occurs, then, depending on interrupt mode set in registers IMFa and IMFb, the processor performs the following action: y In interrupt mode 0: fetches an instruction from the bus, usually RST0 - RST7, and executes it.

y y

In interrupt mode 1: jumps to interrupt processing routine located at address 0038h. In interrupt mode 2: fetches one byte from the bus and jumps to interrupt-processing code located at address: low-order byte of the address: the byte fetched from the bus high-order byte of the address: loaded from I register

Interrupt mode can be set using IM 0, IM 1 and IM 2 instructions. RETI instruction is used to return from maskable interrupt. NMI is a non-maskable interrupt. When non-maskable interrupt occurs the CPU will preserve the content of IFF1 register in IFF2 register, disable maskable interrupts and jump to location 0066h. This interrupt has higher priority then the maskable interrupt. RETN instruction is used to return from non-maskable interrupt. Software interrupts can be invoked by executing RST0 - RST7 instructions. These interrupts are processed in the same way as hardware mode 0 maskable interrupts.

I/O ports
256 Input ports 256 Output ports

Registers
Z80 microprocessor has the following registers: Accumulator (A) register is an 8-bit register used for arithmetic, logic, I/O and load/store operations. Flag is an 8-bit register containing 6 1-bit flags: y y y Carry (C), bit 0 - set if there was a carry during addition, or borrow during subtraction/comparison. Subtract (N), bit 1 - this flag is set if the last operation was subtract. The flag is used by DAA instruction to do proper correction of BCD numbers. Parity/Overflow (P/V), bit 2 - set if the parity (the number of set bits) in the result of logical operation is even. This flag also set when addition or subtraction results in a too large positive number or a too small negative number that cannot fit into destination operand, i.e. if the result is greater than +127 or smaller than -128. For example, adding 1 to 127 will set the overflow flag. Half carry (H), bit 4 - set if there was a carry out from bit 3 to bit 4 of the result. Zero (Z), bit 6 - set if the result is zero. Sign (S), bit 7 - set if the result is negative.

y y y

General registers: y 8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a pair the C register contains low-order byte and B contains high-order byte of the word. The BC register can be used for register indirect addressing. It is also used as a byte counter by block transfer and compare instructions. B register is used as a byte counter for DJNZ and I/O block instructions. C register is used as a port number in I/O block instructions. 8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a pair the E register contains low-order byte and D contains high-order byte of the word. The DE register can be used for register indirect addressing.

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a pair the L register contains low-order byte and H contains high-order byte of the word. The HL register can be used for register indirect addressing.

The Z80 CPU includes alternative set of of Accumulator, Flag and General registers. It is not possible to change those registers directly, but it's possible to swap main and alternative registers thus getting access to alternative registers. Index registers (IX and IY) are used for indexed addressing. Other registers: Stack pointer is a 16 bit register. This register points to last used memory location in program stack. The stack pointer is decremented when data is pushed into the stack, and incremented when data is popped from it. Program Counter (PC) is a 16-bit register. This register contains an address of the next instruction. Interrupt vector (I) is an 8-bit register. This register contains upper 8-bit of an address where interrupt processing routines or entrance points for interrupt mode 2 are located. Memory refresh (R) is an 8-bit register. Lower 7 bits of this register are automatically incremented after each instruction fetch and used for dynamic memory refresh. The 8th bit is not used for dynamic refresh. If necessary, the memory refresh register can be set using LD R, A instruction. Interrupt flip-flop 1 (IFF1) 1-bit register. This register contains 1 if maskable interrupts are enabled, and 0 if maskable interrupts are disabled. When non-maskable interrupt occurs the content of this register is preserved in IFF2 register, and this register is reset to 0. Interrupt flip-flop 2 (IFF2) 1-bit register. This register is used to store the content of IFF1 register when nonmaskable interrupt occurs. Interrupt mode flip-flops (IMFa and IMFb) are two 1-bit registers. These registers reflect current interrupt mode: IMFa=0, IMFb=0 - Interrupt mode 0. This is an 8080-compatible interrupt mode. IMFa=0, IMFb=1 - Not used. IMFa=1, IMFb=0 - Interrupt mode 1. In this mode CPU jumps to location 0038h for interrupt processing. IMFa=1, IMFb=1 - Interrupt mode 2. In this mode CPU jumps to location, which high-order address is taken from I register, and low order address is supplied by peripheral device.

Instruction Set
Z80 instruction set consists of the following instructions: y y y y y y y y Data move and exchange instructions. Block move and search instructions. Arithmetic - add, subtract, increment, decrement, decimal adjust, negate and compare. Logic - AND, OR, exclusive OR, complement, shift and rotate. Bit manipulation - set, reset and test bits. Control transfer - conditional and unconditional: jumps, subroutine calls and returns from subroutine. Input/Output instructions. Other - stack operations, disabling/enabling interrupts, setting interrupt mode, etc.

Addressing modes
Implied - the data value/data address is implicitly associated with the instruction. Register - references the data in a register or in a register pair. Register indirect - instruction specifies a register containing an address, where data is located. Immediate - 8-bit data is provided in the instruction. Immediate extended - 16-bit data is provided in the instruction.

Modified page zero - the destination address in zero page is calculated as N * 8, where N is a three-bit number supplied by the instruction. Relative - one byte offset is added to the address of the next instruction. The offset is a signed number in the range 127 - +128. Extended - the instruction operand specifies the memory address where data is located and where the program control should be transferred. Indexed - 8-bit offset is added to the contents of an index register (IX or IY), the resulting value is a pointer to location where data resides. Z80 INSTRUCTION SET: Mnemonic: Description: ADC ADD WITH CARRY ADD ADD LOGICAL AND AND BIT TEST BIT CALL SUB ROUTINE CALL COMPLEMENT CARRY FLAG CCF CP COMPARE COMPARE AND DECREMENT CPD CPDR COMPARE DECREMENT AND REPEAT COMPARE AND INCREMENT CPI COMPARE INCREMENT AND REPEAT CPIR CPL COMPLEMENT ACCUMULATOR DECIMAL ADJUST ACCUMULATOR DAA DECREMENT DEC DISABLE INTERRUPTS DI DJNZ DEC JUMP NON-ZERO ENABLE INTERRUPTS EI EX EXCHANGE REGISTER PAIR EXCHANGE ALTERNATE REGISTERS EXX HALT, WAIT FOR INTERRUPT OR RESET HALT INTERRUPT MODE 0 1 2 IM IN INPUT FROM PORT INCREMENT INC INPUT, DEC HL, DEC B IND INDR INPUT, DEC HL, DEC B, REPEAT IF B>0 INPUT, INC HL, DEC B INI INIR INPUT, INC HL, DEC B, REPEAT IF B>0 JUMP JP JUMP RELATIVE JR LOAD DATA TO/FROM REGISTERS/MEMORY LD LOAD DECREMENT LDD LDDR LOAD DECREMENT AND REPEAT LOAD AND INCREMENT LDI LDIR LOAD INCREMENT AND REPEAT NEGATE ACCUMULATOR 2'S COMPLEMENT NEG NO OPERATION NOP OR -OUTPUT, DEC HL, DEC B, REPEAT IF B>0 OTDR OUTPUT, INC HL, DEC B, REPEAT IF B>0 OTIR OUTPUT TO PORT OUT OUTD OUTPUT, DEC HL, DEC B OUTPUT, INC HL, DEC B OUTI POP POP FROM STACK PUSH INTO STACK PUSH RESET BIT RES RET RETURN FROM SUB ROUTINE RETI RETURN FROM INTERRUPT

RETN RETURN FROM NON MASKABEL INTERRUPT ROTATE LEFT register RL ROTATE LEFT ACUMULATOR RLA RLC ROTATE LEFT THROUGH CARRY register ROTATE LEFT THROUGH CARRY ACCUMULATUR RLCA RLD ROTATE LEFT DIGIT ROTATE RIGHT register RR ROTATE RIGHT ACCUMULATOR RRA RRC ROTATE RIGHT CIRCULAR register ROTATE RIGHT CIRCULAR ACCUMULATOR RRCA ROTATE RIGHT DIGIT RRD RESTART RST SBC SUBTRACT WITH CARRY SET CARRY FLAG SCF SET SET BIT SHIFT LEFT ARITHMETIC register SLA SHIFT RIGHT ARITHMETIC register SRA SHIFT RIGHT LOGICAL register SRL SUB SUBTRACTION EXCLUSIVE OR XOR SAMPLE PROGRAM:

This is a sample program to display "Hello World!" on the screen of a TI-83 plus graphing calculator.
Note: the b_calls exist only on the graphing calculators, not on just any device. .NOLIST #INCLUDE "ti83plus.inc" .LIST .ORG $9D93 .DB t2ByteTok, tAsmCmp b_call(_ClrLCDFull) b_call(_HomeUp) ld hl,msg b_call(_PutS) ; Display the text b_call(_NewLine) RET msg: .DB "Hello world!", 0 .END