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Laboratory Manual EC 760 ASIC-CAD Lab

(ASIC FLOW for a Digital Design) (Using Synopsys and Cadence)

Department of Electronics and Communication Engineering National Institute of Technology Trichy-15

EC 760 ASIC-CAD Lab

Course Description Modern digital design practices are based on Hardware Description Languages (Verilog, VHDL) and CAD tools, particularly logic synthesis. This course emphasizes on complete ASIC flow of a digital design. The objective of this course is to prepare the student to be an ASIC designer in industry. To this end we will focus on how to simulate and synthesize a digital design using Synopsys, Floor planning, Power planning, Parasitic Extraction, Placement and Routing using Cadence Encounter and Post layout simulation and synthesize using Synopsys, using Verilog as the main example. The following topics will be covered in the order given.

1. Design of any digital system with Verilog HDL. 2. Functional simulation using VCS(Synopsys) . 3. Logic synthesize using Design Compiler(Synopsys). 4. RTL simulation using VCS (Synopsys). 5. Floor planning using Encounter (Cadence). 6. Power planning using Encounter (Cadence). 7. Parasitic Extraction using Encounter (Cadence). 8. Placement and Routing using Encounter (Cadence). 9. Post layout simulation using VCS (Synopsys). 10. Post layout synthesize using Design Compiler (Synopsys).

Technical Requirements You must have access to a Verilog simulator (VCS) and design synthesis tools (e.g. Synopsys Design Compiler, Cadence Encounter tools) in order to take this course. In addition, you will be required to have Linux OS in your system.

EC 760 ASIC-CAD Lab FRONT END DESIGN

BACK END DESIGN


FLOOR PLANNING

DESIGN ENTRY (verilog and test bench file)

S Y N O P S Y S

POWER PLANNING RTL simulation using VCS simulator

C A D E N C E E N C O U N T E R

PLACEMENT AND ROUTING Synthesis using DESIGN COMPILER

PARASITIC EXTRACTION Gate level simulation using VCS

Netlist.v, .sdf, .spf Netlist.v, .sdf,.sdc

Read .sdf,netlist.v and .spf from CADENCE in SYNOPSYS DESIGN COMPILER for Post-Layout Synthesis

New netlist.v,.sdf

Post-Layout Simulation using SYNOPSYS VCS simulator

Fig: ASIC FLOW FOR A DIGITAL DESIGN


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Step I
Open gedit to write verilog code. Save it in working directory with extension .v. VERILOG CODE //ripple carry adder `timescale 1ns/1ps // it is compulsory. module rp_cy(s, cout, a, b, cin); output [15:0] s; output cout; input [15:0] a; input [15:0] b; input cin; wire c1,c2,c3; fa_4bit f1(s[3:0],c1,a[3:0],b[3:0],cin); fa_4bit f2(s[7:4],c2,a[7:4],b[7:4],c1); fa_4bit f3(s[11:8],c3,a[11:8],b[11:8],c2); fa_4bit f4(s[15:12],cout,a[15:12],b[15:12],c3); endmodule module fa_4bit(s, cout, a, b, cin); output [3:0] s; output cout; input [3:0] a; input [3:0] b; input cin; wire c1,c2,c3; fulladder f1(s[0], c1, a[0],b[0],cin); fulladder f2(s[1], c2, a[1],b[1],c1); fulladder f3(s[2], c3, a[2],b[2],c2); fulladder f4(s[3], cout, a[3],b[3],c3); endmodule module fulladder(s, cout, a, b, cin); output s; output cout; input a,b,cin; assign {cout,s}= a+b+cin; endmodule

Step II
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Similarly write test bench and save it in the working directory with extension .v. TEST BENCH `timescale 1ns/1ps // it is compulsory. module rpcy_tbench; reg [15:0]a; reg [15:0]b; reg cin; wire cout; wire [15:0]s; rp_cy t1(s, cout, a, b, cin); initial begin a=0; b=0;cin=0; #50 a=2;b=2;cin=1; #50 a=234;b=56789; #50 a=3455;b=12345; #50 a=58967;b=65535; #50 a=167;b=12;cin=0; #50 a=791;b=8975; #50 a=545;b=6754;cin=1; end endmodule

SYNOPSYS SIMULATOR:

VirSim runs the simulator and displays simulation data in real-time in VirSim debug windows. You can start the simulation and synchronize debug operations from the Interactive Window. VirSim can run the following simulators interactively: VerilogXL or VCS, and Scirocco.

EC 760 ASIC-CAD Lab

VCS Verilog Compiler Simulator VCS is a Verilog Compiler and Simulator tool from Synopsys.

VCS enables you to analyze, compile and simulate Verilog, VHDL and mixed-HDL design descriptions. VCS is graphical interface which you can use to debug your code. VCS has a command language interface (CLI) for entering commands during simulation. VCS also has a graphical user interface called Virsim for displaying the design hierarchy, stepping through the code, creating breakpoints, viewing waveforms and other debugging operations. Basic Commands to run VCS >vcs Mupdate RI dut.v testbench.v & where Mupdate is a switch enables incremental compilation -RI is compile and Run interactive debug with virsim GUI //command to compile and run to display the waveforms >vcs Mupdate R dut.v testbench.v & //command to compile & run only to view the signals $monitor. >vcs -Mupdate R dut.v testbench.v >log //command to compile & run to store the signal information in log file. >vcs RPP & //Command to open the virsim hierarchy window >virsim & // command to open the virsim hierarchy window.

EC 760 ASIC-CAD Lab

Step III Functional simulation


In terminal type the following commands... csh cd /cad/home/..... working_directory_path source /cad/synopsys/synopsys.cshrc vcs -Mupdate -RI rp_cy.v rp_tbench.v This command invokes the Virsim Interactive Simulator window

EC 760 ASIC-CAD Lab

Step IV
Click on new waveform window icon. Select the new hierarchy window icon. Select signals in hierarchy window and click on add option to add these signals to the waveform window.

Hierarchy window

EC 760 ASIC-CAD Lab

Waveform window

In the virsim interactive window, set the step time. Click on ok to do functional simulation till specified time. Check the output in waveform window.

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Exit from the Virsim Environment after the functional simulation.

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Step V
To synthesize the design invoke Design Compiler using the following command. design_vision& On giving this command the Design Vision GUI opens.

To set the target and link libraries the following files should be copied to the working directory. s35_CORELIB.db, s35_CORELIB.sdb, s35_CORELIB.v & s35_UDP.v Go to File Setup and set the link and target libraries to ..../wrk_dir/s35_CORELIB.db. Set the symbol library to ..../wrk_dir/s35_CORELIB.sdb.

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To read the design files go to File Read and select the verilog design files to be synthesized. For a sequential design ensure that the clock timing is specified using the command create_clock clkname -p clkperiod

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EC 760 ASIC-CAD Lab Now to synthesise the design give the compile command in the command window.

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The reports for timing, power and area can be seen by giving the following commands. report_timing -delay min report_timing -delay max report_area report_power

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EC 760 ASIC-CAD Lab To view the schematic go to Schematic New Design Schematic View.

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To optimize the design area, the command is set_max_area value . Again compile and see that the area is reduced to the specified value. To generate netlist file, give the command write -format verilog -hierarchy -output netlistfilename.v To generate sdf file for back annotation, the command is write_sdf -significant_digits 4 sdffilename.sdf Here the number 4 indicates the no. of significant digits in the delay value. Close the design vision

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EC 760 ASIC-CAD Lab STEP VI For performing the timing simulation, the steps listed below should be performed. Type `timescale 1ns/1ps in the netlist file which is available in the working directory. Edit the testbench file by giving $sdf_annotate (sdffilename.sdf, testbenchname.instancename, , logfilename.log, minimum, , ) within the initial statement. In the terminal window give the command

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vcs -Mupdate -RI netlistfilename.v testbenchname.v -v s35_CORELIB.v s35_UDP.v The timing delays will now be updated in the waveform.

Synthesized netlist is taken to Cadence Encounter for floor planning,power planning, and placement and routing. The routed netlist along with the .sdf and .spf are back annotated to the synopsys-design compiler for static timing analysis of the circuit.

CADENCE ENCOUNTER
After generating the netlist and sdf files using synopsys, generate sdc file using the following command in the command line of synopsys design vision:

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EC 760 ASIC-CAD Lab write_sdc sdcfilename.sdc Close design vision. Ensure that that you have the following files in your working directory: 1) Netlist file 2) sdf file 3) sdc file

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Also copy the technology library files namely tlf and LEF files into your working directory. Now open a new terminal and give the following commands; #csh Enter into your working directory specifying the appropriate path $cd /home/ecad/MTech/Vlsi2008 Source cadence tool: $source /cad/cadence/cadence.cshrc Encounter provides an integrated solution for an RTL-to-GDSII design flow. It deals with design planning, placement and routing, block implementation. Invoke the tool encounter: $encounter This will open the encounter window.

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IMPORTING A DESIGN: In the Encounter window goto Design Import Design A window by name Design import pops up, in this window the following modifications are to be made under the Basic tab: Browse and add your verilog netlist file which is output of the synopsys synthesis tool Under common timing libraries, browse. In the timing file window, browse for tlf, double click on it, now double click on c35b3_3.3v, select and add all the files under c35b3_3.3v Under LEF Files, browse.In the LEF file window, browse for LEF, double click on it, now double click on c35b3.lef, select and add all the files under c35b3.lef Under timing constraint files, browse.In the timing constraint file window, select your sdc file and add it.

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Now the design import window will look like:

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Now select the Advanced tab and make the following modifications: Select Delay calculation and change the value under Input transition/slew to 120ps

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Now select IPO/CTS and make the changes as shown in the following window:

Next select Power option, under that the entries should be made as shown in the following window: Under power nets enter vdd! and enter gnd! under ground nets.

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Now click on OK. Now the encounter window will display the boundary of your layout:

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EC 760 ASIC-CAD Lab FLOOR PLANNING:

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In the Encounter window select FloorplanSpecify Floorplan to get a Specify Floorplan window. In that under the Basic tab changes should be made as shown in the window:

Now click OK

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In the Encounter window select FloorplanAutomatic FloorplanPlan Design to get a Plan Design window. All settings in this are default, just click Apply and OK.

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POWER PLANNING: In encounter window select PowerPower planningedit power planning to open edit power planning option window, in that under Objects option: RING and under Ring offset make the changes as : Select MET1 or MET3 for H-Layer and MET2 for V-Layer Enter the value as 0 under all the four options namely top, bottom, left and right. click on Add/Modify.

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Now under Objects option: STRIPE and under first/last stripe make the changes as:: Select MET2 under HV-Layer; enter 100 in X from left and X from right columns. Click on Add/Modify. Now select both the objects, give a power planning option set name and save it.

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In encounter window select PowerPower planningAdd rings Under the Basic tab alter the settings as : Under the width option enter 8 for all the four columns, under spacing option enter 1 for all the four columns; Check the use option set checkbox and click on update basic.

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In encounter window select PowerPower planningAdd stripes Under the Basic tab alter the settings as: Enter 8 under the width column and 1 under spacing; Check the use option set checkbox and click on update basic. Click on Ok.

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You will notice that the power cells will be included in the design as shown:

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EC 760 ASIC-CAD Lab PLACEMENT: In encounter window select PlaceStandard cells and blocks, in the window that pops up, make settings as shown:

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place

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EC 760 ASIC-CAD Lab ROUTING:

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In encounter window select Route Trial Route, in the window that pops up, settings should be made as shown in the following illustration. Remember to set max. route layer to 3

After trial route step, the tool does trial routing of your design and not the actual routing. This gives us an idea about the possible locations of congestion in our design after actual routing, the design will now look like:

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RC EXTRACTION: In encounter window select TimingExtract RC Alter the settings as indicated in the window:

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Now the following files have been saved in the working directory .spf and .spef files.

In encounter window select TimingGenerateWireload Model, changes to be made in the window that pops up are as shown below:

In encounter window select TimingCalculate delay, settings to be made as shown in the window:

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In encounter window select TimingOptimize, settings to be made as shown in the window, this checks for timing violations before clock tree synthesis:

To save the netlist with parasitic RC values, goto DesignSaveNetlist Give a filename as rc_net_filename.v CLOCK TREE SYNTHESIS: If we need to check for timing violations after synthesis of clock tree then the following command should be given in the terminal: optDesign -postCTS For specific checking of timing violations after routing, the following commands can be used: optDesign -postRoute optDesign -postRoute -hold // this is for checking hold time violations.

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In case of sequential design, the following procedure is additional. In encounter window select TimingCalculate delay, uncheck the ideal clock option and save the sdf file, also save the netlist.

To get the GDS format, goto Design->Save->GDS Give a filename as gdsfilename.gds This completes the generation of layout for the design.

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USING THE DESIGN COMPILER FOR THE POST-LAYOUT SYNTHESIS: In the pre-Layout synthesis the clock is considered as ideal and actual routing delay is not calculated. But after completing the layout in cadence, it generates the Standard Delay Format (.sdf) file, RC Extraction file (.spf) and netlist (.v). This is back annotated to the Design Compiler using the following commands. design_vision-xg-t>read_verilog netlist.v (got from Encounter) design_vision-xg-t>read_sdf design.sdf (got from Encounter) design_vision-xg-t> read_sdc design.sdc (Synopsys Design Constraints file form Synopsys) Commands exclusive for Post_layout Synthesis: design_vision-xg-t> read_parasitics design.spf (got from Encounter) design_vision-xg-t>set_propagated_clock [get_clocks clk] The set_propagated_clock allows DC to calculate the actual clock latency of a clock tree (post layout). Compile the design and report the timing. Also generate new netlist file and sdf file.(postlayout_netlist.v, postlayout_sdf.sdf). To generate netlist file, give the command write -format verilog -hierarchy -output postlayout_netlist.v To generate sdf file for back annotation, the command is write_sdf -significant_digits 4 postlayout_sdf.sdf Here the number 4 indicates the no. of significant digits in the delay value. Generally Pre-Layout synthesis is done at worst operating conditions for checking the setup time violations and post layout synthesis at best operating conditions for hold time violations. The command report_timing does not give the hold time violations. The following command is used to report the hold time violations.

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EC 760 ASIC-CAD Lab design_vision-xg-t>report_constraints -all_violators We can fix the hold time violations by using set_fix_hold command

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Post-Layout Simulation:
The test bench is annotated with the sdf generated after the physical synthesis (postlayout_sdf.sdf). To do the Post-Layout simulation we need to give the netlist, test bench annotated with the .sdf file(save it as testbench.v) and library files(s35_CORELIB.v , s35_UDP.v ). Following is the command used in the terminal for the Post-Layout simulation. vcs -Mupdate -RI postlayout_netlist.v testbench.v -v s35_CORELIB.v s35_UDP.v

This completes the full ASIC flow for digital design.

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