R.

ARUN
Flat No: 130/5, MahilamPoo Apartments Chinammal Street (Extn), K.K.Pudur Coimbatore - 641 038. Telephone No: +91 98943 12265 E-Mail Id: r.arundec@gmail.com

OBJECTIVE: To be a distinguished performer, contributing my best to the organization in an ethical way, and thereby playing an important role in the organizations growth.

ACADEMIC CHRONICLE: M.Tech VLSI Design SASTRA University, Tanjore CGPA: 6.4 B.E Electronics & Communication Engineering V.L.B.Janakiammal College of Engineering & Technology, Coimbatore Anna University, Chennai Aggregate: 67% STD-XII Bharathi Matriculation Higher Secondary School, Coimbatore Aggregate: 71.75% STD-X Bharathi Matriculation Higher Secondary School, Coimbatore Aggregate: 76.90%

2010-2012

2005-2009

2004-2005

2002-2003

AREA OF INTERESTS: VLSI Design Low Power VLSI Design Computer Networks COMPUTER SKILLS: LANGUAGES SOFTWARE TOOLS : HTML, C & Basics of Java, Verilog, VHDL : Adobe Photoshop

HARDWARE TOOLS : Electric-8.08, MICROWIND, Multisim, ModelSim, Xilinx ISE, Leonardo Spectrum, Cadence SOC Encounter. OPERATING SYSTEM : Microsoft Windows 9x, XP,7 CERTIFIED COURSES : Underwent CCNA training at HCL-CDC.

PRESENTATIONS: POSTER PRESENTATION: Presented a poster on GIS & Remote Sensing at TamilNadu Agricultural University, Coimbatore. PAPER PRESENTATION: Dynamic Partial Reconfiguration of FIR Filter in PEID National Conference at INFO Institute of Engineering, Coimbatore. Opto-Electronics & its applications at Sri Krishna College of Engineering & Technology, Coimbatore. A Mighty Maze with the Fuzzy Ant in Robotics at SASTRA University, Thanjavur.

IN-PLANT TRAINING: All India Radio Station (AIR) Coimbatore. Bharat Sanchar Nigam Limited (BSNL) Coimbatore. MINI PROJECT: Project on Alarm-Bell using 555 timer circuit.

PROJECT:

Title: Static power optimization of FPGAs using architectural level power optimization techniques.
The theme of the project goes on with the work for future way of making our computers greener with the environment. The project aims to design an Arithmetic and Logic Unit (ALU) that consumes lesser power than the traditional one. Since FPGAs are the most widely used reprogrammable devices and consume significantly more power than many other devices, there is a need to optimize the design of these FPGAs. The power hungry ALU is the most important and difficult block to optimize. The design paves way to a new path in the field of low power electronics and it significantly reduces the power consumed by the basic ALU to the 8-bit ALU designed. The project created a platform to learn and work with tools like MICROWIND, Verilog HDL, MODELSIM and Multisim.

EXTRA CURRICULAR ACTIVITIES: Participated in many competitions like Quiz, Product Launch, Debate etc; Member of Music club in college. Participated in State level Football tournament. HOBBIES OF INTEREST: Playing, Quizzing, Reading and Singing. ROLES ACCOMPLISHED: Vice-captain for Cricket and Basket-Ball team. Organizer of Quiz Competition at the National Level Technical Symposium held at college. Master-of-Ceremony in department functions at college. ACHIEVEMENTS: Awarded 1st prize at intra college quiz competition. Secured 1st prize in Basket-Ball tournament. Won 2nd prize in Product-2020 at Concorrenza in V.L.B.Janakiammal College of Engineering & Technology. WORK EXPERIENCE: Worked as lecturer at INFO Institute of Engineering, Coimbatore - (Duration: 8Months).

PERSONAL DETAILS: Name Age Date of Birth Gender Fathers Name Mothers Name Languages Known To Speak To Read/Write : R.Arun : 23 years : 18 December 1987 : Male : M.Ramkumar : R.Thenmozhi : English, Tamil and Kannada : English, Tamil and Hindi

DECLARATION: Thus I declare that the above details furnished by me are true to the best of my knowledge.

(R.ARUN)