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Answer: A Finite State Machine (FSM) is a sequential logic circuit model that
is composed of a finite number of “states” along with the possible transitions
between each of those states. The behavior of a FSM can be described as a
sequence of events that occur at each discrete instance in time. In general, a
FSM can be described by:
• Moore State Machines: the output of each state depends only on the
present state.
• Mealy State Machines: the output of each state depends on both the
present state and the present value of the inputs. In this case, the output
can be thought of as associated with each transition (or “arc”) of the state
machine.
[Comment: The answer is pretty straightforward—it comes from a general
understanding of finite state machines derived from the “finitemachine”
reading you provided.]
Answer: Since the problem did not specify a machine type, let’s follow the
example given and do a Mealy Machine:
[Comment: this is almost the same as the example given in the “finite-
machine” reading—except that when the sequence is detected the output is 0
—not 1 as in the example (you can think of the output as “inverted”). Note
the tricky arcs from states B->B, C->C, and D->B.]
0/1
1/0
1/1
0/1 1/1
The State Table can be drawn as follows corresponding to this state diagram:
Present Input Next Output
State State
A 0 A 1
A 1 B 1
B 0 C 1
B 1 B 1
C 0 D 1
C 1 B 1
D 0 A 1
D 1 B 0
Since this is a somewhat simple state machine, we can see from a glance that
the number of states (4) is pretty much minimized. Therefore the state
minimization step is not needed and we can go ahead and encode/assign the
states. We have many choices of encoding the states (such as “one-hot,” etc.--
where each state is one bit), but for simplicity let’s use the classical “binary
encoding” and just use 2 bits to encode the 4 states:
A = 00, B = 01, C = 10, D = 11
Finally, let’s go ahead and implement our state machine. Since the question
did not specify a choice of flip-flops, we have the freedom to choose—let’s go
ahead and use D flip-flops:
D1:
D0:
So D0 = I + Q1 (~Q0)
O:
So O = ~(I Q1 Q0)
Gate Implementation:
Q1
XOR
Q0
AND DFF
NOT Q1
Clk Reset
I NAND O
Q0
Q1 OR DFF
AND
~Q0 Clk Reset
3. Use Odd Parity Checker example on the lesson to design Even Parity Checker. You
don't need to redesign everything again. You can use the example in this lesson, and
modify some variables to convert the Odd Parity Checker into Even Parity Checker.
Answer: Most of the work is already done by the odd parity checker example
—we just need to output a “1” when we are in the even (present) state instead
of the example’s odd (present) state:
1
Reset E/1 O/
0
1
0 0
Present
Input Next State Output
State
EVEN 0 EVEN 1
EVEN 1 ODD 1
ODD 0 ODD 0
ODD 1 EVEN 0
Present
Input Next State Output
State
0 0 0 1
0 1 1 1
1 0 1 0
1 1 0 0
From the Encoded state transition table shown above, we can write the following
functions:
NS = PS ⊕ PI
OUT = ~PS
D Flip-Flop Implementation
OUT