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EETimes
THE NEWS
SOURCE FOR THE
CREATORS OF
TECHNOLOGY
ISSUE 1603 MONDAY, JUNE 6, 2011 WWW.EETIMES.COM
Tablet wars (aka Computex 2011) 12
June 6, 2011 Electronic Engineering Times 3
CONTENTS JUNE 6, 2011
OPINION
4 Commentary
Is a media tablet a PC?
50 Last Word
Space exploration is a
marathon, not a sprint
NEWS OF THE TIMES
7 Renesas Mobile CEO
banking on LTE for market
share growth
10 Intel Ultrabooks
attack tablet market
12 The tablet wars
(aka Computex 2011)
GLOBAL WATCH
16 ST keeps faith in wireless
big chips in the middle
COVER STORY
18 Touch mania
swipes across markets
INTELLIGENCE
26 Algae yields hydrogen fuel
28 HP discovers memristor
mechanism
DESIGN + PRODUCTS
Global Features
31 3-D IC design: New
possibilities for wireless
33 Creating stereoscopic 3-D
for mobile devices
37 Under the Hood: Wide
Bluetooth, Wi-Fi adoption
seen in handsets
41 Planet Analog: Are you
violating your op amps
input common-mode range?
EE LIFE
47 Pop Culture: Engineering for
kindergarteners
48 Investigations: Knee-deep
in exploding mice
26
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4 Electronic Engineering Times June 6, 2011
COMMENTARY
Some analysts categorize media
tablets separately and are projecting
that the tabs will undercut PC sales in
2011. Market research firm IHS iSup-
pli, for example, recently reported that
first-quarter PC sales slipped a bit from
last years first-quarter numbers, in
part because of rising interest in
media tablets.
Clearly, the media tablet
is a phenomenon that is
making a big impact on
the PC market. Whether
its lifting or hurting that
market, however, depends
on your perspective.
So is a media tablet a PC
or not? This being 2011, it
might be useful to turn to
Wikipedia, the default
reservoir of knowledge on
all topics, which defines
the personal computer as
any general-purpose com-
puter whose size, capabili-
ties and original sales
price make it useful for
individuals, and which is
intended to be operated
directly by an end user
with no intervening computer opera-
tor. It continues:
PCs include any type of computer that is
used in a personal manner. This is in
contrast to the batch processing or time-
sharing models, which allowed large,
expensive mainframe systems to be
used by many people, usually at the
same time, or large data processing sys-
tems, which required a full-time staff to
operate efficiently.
By that definition, a tablet would
appear to qualify. But so would a lot of
other things that arent mainframes
(does anyone use main-
frames anymore?). An
iPod might make the cut.
The Wikipedia defini-
tion goes on to say:
A personal computer may
be a desktop computer or
[a] mobile type, for exam-
ple a laptop, tablet PC or
handheld PC (also called
a palmtop) that is smaller
than a laptop.
Palmtop? Was this writ-
ten in 1996? Someone
really ought to take
advantage of the collabo-
rative nature of
Wikipedia and update its
PC definition in language
recognizable by todays reader.
The Wikipedia entry includes a sub-
section for tablet PCs:
A tablet PC is a notebook or slate-shaped
mobile computer. Its touchscreen or
graphics tablet/screen hybrid technology
allows the user to operate the computer
with a stylus or digital pen, or a finger-
tip, instead of a keyboard or mouse. The
form factor offers a more mobile way to
interact with a computer. Tablet PCs
are often used where normal notebooks
are impractical or unwieldy, or do not
provide the needed functionality.
Aha! Right? Well, not exactly.
For one thing, the photo used to illus-
trate the tablet PC is an HP Compaq
tablet PC with a rotating/removable
keyboard. The photo was taken in 2006.
And many people tend to differentiate
between a tablet PC (read, runs Win-
dows) and a media tablet, such as the
iPad or Android-based tabs.
With the rapid evolution of technolo-
gy and rising prominence of mobility,
the lines between product categories
are blurring beyond recognition. Good
luck, these days, drawing distinctions
among notebook PCs, netbooks, tablets
and even, in some cases, e-readers.
Does it really matter? Yes and no.
Yes, because while the PC markets
usual suspectsAcer, Dell, HP and the
likeare all scrambling to put out com-
pelling tablets, so are a lot of other com-
panies. They include handset vendors
like Research in Motion and Motorola,
electronics giants like Samsung, and
evendepending on your definition of
a tabletbooksellers like Amazon and
Barnes and Noble. (Apple is obviously
far and away the leader in tablets, but
while Apples roots are in personal com-
puting, today its a consumer electronics
vendor that happens to sell personal
computers [dont let Apple hear you call
its computers PCs].)
In another sense, though, it doesnt
really matter whether a tablet is a PC.
To IC Insights point, tablets, like tradi-
tional PCs, consume a lot of chips.
Whether you consider them PCs or you
dont, their popularity is a good thing
for the chip market.
How good a thing? Again, it depends
on your perspective, since the tablet,
unlike the traditional, Wintel PC, has
opened the game to a whole host of
ARM-based processors. And all of them,
at this very moment, are fighting hard
for market share.
p
By Dylan McGrath (dylan.mcgrath@
ubm.com), editor of EETimes.com.
A new report published by market research
firm IC Insights Inc. postulates that PC sales
will grow by 13 percent in 2011, thanks in part
to strong projected growth of Apple Inc.s iPad
and other media tablets. The report calls to
the forefront the question of whether tablets
belong in the PC category or are something
else entirely.
Is a media tablet a PC?
Does it matter?
Good luck,
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TODAYS MOBILE DEVICES are about
having everything in the palm of your
hand, at the touch of a buttonfrom
Internet browsing and e-mail to watch-
ing high-definition TV or using a GPS.
Increasing demand for multimedia fea-
tures translates into complex design
requirements, such as higher perform-
ance with reduced power in an ever-
smaller footprint.
Design teams have two choices:
either shrink the node or innovate
some alternative to address the more
than Moore trend. With development
costs heading toward $100 million for
the 32-nanometer process node, for
example, monolithic mixed-signal SoCs
are increasingly challenging and time-
consuming to develop.
Design teams are looking for alterna-
tives to speed time-to-market and reduce
costs, and some are finding that using
3-D ICs with through-silicon vias (TSVs)
represents the most practical wayor
perhaps the only wayto handle design
complexity and maximize performance
and speed. 3-D ICs promise to meet mar-
ket demand for miniaturization, higher
speed and greater bandwidth, as well as
lower latency and power consumption.
That makes the move from 2-D to
3-D a natural choice.
The question today is not whether
3-D ICs will be designed and built, but
whether design teams (outside of a
handful of large semiconductor compa-
nies) will have the EDA tools and infra-
structure support required to make
3-D-ICs cost-effective.
Not a new concept
Despite the recent buzz in the industry
about 3-D technology, the concept is not
new. Indeed, 3-D packaging has been
around for years, in the form of stacks of
dice with wirebonds, package-in-package
(PiP) design and package-on-package
DESIGN PRODUCTS
+
3-D IC design: New possibilities
for the wireless market
By Samta Bansal, Brad Griffin and Marc Greenberg
GLOBAL FEATURE
June 6, 2011 Electronic Engineering Times 31
Source: Cadence Design Systems
There have been, and will be, multiple steps along the path to true
3-D IC packaging with stacked dice and through-silicon vias.
(PoP) design, to name a few. PoP is a wide-
spread configuration that combines a
stack of memory modules atop an appli-
cation processor or digital baseband.
Open up your Apple iPhone 3 or your
iPad, and PoP technology is already there.
Other 3-D packaging solutionssuch
as embedded dice in laminate, or rebuilt
waferlike fanout wafer-level packag-
ingimprove signal integrity, shorten
interconnects and reduce line/space for
rerouting, thus shrinking the package
footprint. Though all of the above con-
figurations are 3-D at the packaging lev-
el, none of them use TSVs.
Think of a TSV as an additional layer
that helps extend the 3-D packaging to
the IC level. With their short intercon-
nects and better electrical performance,
TSVs could have a huge impact on total
system performance and power. TSVs
can be inserted at the bond pad level (via
last-in wafer-level packaging) or at the
global interconnect level (either via mid-
dle back-end-of-line or via first front-end-
of-line) by foundries.
For a global interconnect TSV, die
stacks are connected not only at the bond
pad level, but also at the IP block or
memory bank level. This type of TSV
enables true heterogeneous integration
of die stacks using the third dimension in
addition to the x-y direction, allowing
optimized interconnections and better
electrical performance. Dice intercon-
nected using this type of TSV are closer to
SoC/IC than system-in package (SiP) and,
hence, are better referenced as 3-D ICs.
TSV technology is actually a conver-
gence of silicon and packaging with the
design, making it possible to conceive
and design new architectures. To bene-
fit fully from 3-D IC TSVs and make this
technology cost-effective, a different
3-D architecture needs to be evaluated
at a very early stage.
TSVs have an unclear technology
road map, however, and methodology
convergence is lacking because of a gap
between the TSV technology process
and TSV system design. Thus, 3-D IC
TSVs represent a new paradigm, for
which designers must modify their
thinking and look beyond the 2-D con-
straints of classical Moores Law design.
Target markets
Major applications that would use 3-D
ICs with TSVs are those that require
speed, bandwidth and power optimiza-
tion. CPUs, GPUs and routers would
adopt this technology for speed and
bandwidth gains. Performance gains
will lead to more competitive end prod-
ucts for which companies can ask high-
er prices, and those premiums might
offset the additional cost that early 3-D
configurations will demand.
Graphics designs that demand very
wide buses and multicore designs that
require high bandwidth to the memory
will also be early adopters of 3-D technol-
ogy, even at the higher initial unit cost.
Set-top boxes, DVRs and HDTVs are
other promising applications for 3-D IC
technology. They constitute a cost-sensi-
tive segment, but in exchange they offer
high volume.
The real drive behind 3-D volume
production will come from the mobile
market, especially smartphones. With
more than 5 billion mobile phones
worldwide, this market represents
attractive volumes, but cost will be the
dominant criterion for TSV acceptance
in the smartphone segment.
Industry requirements
With the advent of truly mobile com-
puting, the mobile industry is searching
for memory technology that can bring
desktop-like computing performance to
mobile devices, including support for
3-D gaming and home-theater standard
1080p, 60-frame/second video. Several
estimates forecast that by 2013, SoC
design starts for mobile devices will
need in excess of 10 Gbytes/s of memory
bandwidthroughly what desktop
machines shipping with DDR3 technol-
ogy require today.
While the mobile industry requires
memory technology that can support
aggressive power and performance goals
in the smallest possible footprint, it
must also shoot for cost-effectiveness.
Using 3-D ICs with TSVs is one of several
possibilities. DRAM stacked with logic
using TSVsa configuration known as
wide I/Opromises 2x to 4x the per-
formance of LPDDR2 technology at half
the power per bit.
Wide I/O could be the technology
that meets the power and performance
goals of the most advanced mobile
devices, if it can be made cost-effective.
The mobile industry needs to look into
a number of elements to resolve the
technical and business challenges that
this technology brings to the table.
One of the biggest questions for any
new memory technology is whether
there is an industry structure to support
it. Jedec efforts are under way to stan-
dardize wide-I/O DRAMs in the areas of
performance, protocol, number of
banks and channels, and number and
arrangement of TSVs. Such standardiza-
tion will create a viable market in
which DRAM manufacturers can sell
their standard dice to multiple cus-
tomers. For their part, customers will
have multiple compatible devices from
which to choose.
Another concern regarding TSVs
application with memory, in particular,
is that DRAM performs poorly at junc-
tion temperatures above 85 C. Keeping
the memory contents refreshed at high-
er temperatures requires more current,
which itself leads to more heating of
the die. There are limits to what can be
standardized, and many of the issues
around assembly, test, and heat dissipa-
tion from the 3-D IC stack will need to
be addressed by each customer.
One way of managing the unknowns
and risks with 3-D IC technology is the
use of silicon interposers. Passive sili-
con interposers allow semiconductor
companies to gain the performance
associated with 3-D IC, while mitigating
risk by avoiding putting TSVs through
active silicon. The silicon interposer
acts as a substrate on which an active
die can be connected with silicon-sized
geometries that are much smaller than
the interconnect on a package or pc
board. TSVs are then used through the
silicon interposer to connect to the
package substrate below.
One of the most public announce-
ments on the use of silicon interposers
came from a large FPGA company.
Rather than use one large die, the com-
pany chose to segment the technology
into four separate, smaller dice to
achieve greater yield. With up to 10,000
interconnect channels on each die and
less than 1-ns delay, the configuration
could enable performance in the silicon
interposer case to be much greater than
would be possible if the dice were con-
nected side by side on a package sub-
strate, or stacked and connected with
bonding wire down to the package sub-
strate. This silicon interposer approach
32 Electronic Engineering Times June 6, 2011
DESIGN PRODUCTS
+
promises next-generation design densi-
ty using current-generation technology.
As appealing as the silicon interposer
may be, its really just an intermediate
step toward true 3-D ICs. Ultimately,
miniaturization and performance goals
will drive design teams to use a stacked,
rather than side-by-side, approach.
With TSVs, interconnect delay through
the stacked active silicon should be
much less than with the side-by-side
interposer approach. So while the pas-
sive silicon interposer is useful for
introducing the concept of TSVs to the
industry, it will most likely lose ground
to a stacked TSV approach as the cost
and attendant risk decrease and as
demand for smaller packages and high-
er performance increases.
Assembly continues to be a major
concern in the industry. Many of the
processing steps involved in the cre-
ation of TSVs can create mechanical,
thermal or electrical stresses on the die
being processed for TSV, and those
stresses may change the properties of
the device. Manufacturing test is anoth-
er issue. For example, finding a method
to probe TSVs with a diameter of 10 m
each and on a 50-m grid could prove
problematic. Allowing the probe head
to contact more than 2,000 TSVs at a
time without damage is another exam-
ple. As the industry works to resolve
these issues, we will surely see logic
devices with TSV-connected DRAM in
the next few years.
Despite the lingering challenges and
unanswered questions, quite a few brave
souls have embarked on this path and are
working to realize the promise of 3-D-ICs
for improved performance and power
management in smaller footprints.
Although theres been significant
traction in this breakthrough technolo-
gy over the past two years, and
although there are no major showstop-
pers from a design or process point of
view, hurdles remain to be cleared
along the path to wide adoption. Those
challenges include cost, the shift in the
design method paradigm, system co-
design, and the incorporation of new
tools and new architectures. A well-
defined ecosystem including foundries,
IP providers, EDA vendors, and out-
sourced semiconductor assembly and
test vendors must emerge with design
kits and reference flows. Cost-effective,
adoptable technological evolution and
ecosystem collaboration are essential
for bringing 3-D ICs with TSVs into the
mainstream.
p
Samta Bansal is senior product
manager for applied silicon
realization at Cadence Design
Systems Inc. She has a
masters degree in physics and a bachelors
degree in electrical and electronics
engineering from Indias Birla Institute of
Technology and Science, Pilani, as well as
an MBA from Santa Clara University.
Brad Griffin is director of
product management for SiP,
IC packaging and PCB high-
speed solutions, for Cadence
Design Systems Allegro and SiP solutions.
He is a graduate of Arizona State University.
Marc Greenberg is director
of product marketing for the
DRAM Design IP products
at Cadence. He has a
masters degree from the University of
Edinburgh in Scotland.
June 6, 2011 Electronic Engineering Times 33
DESIGN PRODUCTS
+
Creating stereoscopic 3-D for mobile devices
By Veera Manikandan Raju
GLOBAL FEATURE
STEREOSCOPIC 3-Dis quickly emerg-
ing as a prime technology across vari-
ous markets, adding a further
dimension of reality to existing 2-D
videos, games, movies and images. With
3-D TVs having hit store shelves, con-
sumers now are getting acquainted
with large-screen, realistic S3-D effects
in home entertainment. Today, S3-D
experiences are migrating from the
large screen to mobile devices, provid-
ing realisticand glasses-freeperson-
alized viewing experiences on the go.
Overall, S3-D video and imaging use
cases can be categorized in two ways:
S3-D content creation and S3-D viewing.
Each poses a unique set of challenges in
mobile design and development. This
article offers solutions to some of the
challenges and shares perspectives on
how to enable successful S3-D experi-
ences on mobile platforms.
Its important first to understand
how S3-D experiences are created.
S3-D essentially adds an extra dimen-
sion to a viewing scene using left- and
right-image pairs via two cameras. In
games, for example, S3-D rendering
refers to the positioning of virtual cam-
eras, while for S3-D video and images,
content is created using two sensors
that are physically spaced apart.
The human brain is able to differenti-
ate depth perception when both views
(left and right, seen through the eyes)
are rendered together. Farther objects in
a given scene are seen at a distance,
while closer objects are seen as closer in
proximity to the viewer.
With the correct level of depth
adjustments, pairs of stereo images pro-
vide the most realistic and natural user
experience. Farther objects are given
positive disparity, and nearer objects are
given negative disparity. Accurately
providing such disparity requires a ref-
erence object on which to focus; this is
called a convergence plane.
In addition, human eyes see a field of
view (FOV) that is dynamically variable
based on where the eyes are looking,
yielding a very flexible S3-D viewing experience at will
(Figure 1).
Content creation
In order to produce such an S3-D effect, content creation
needs to be done with two different camera sensors, and the
left- and right-image pair needs to be processed at 60 frames/
second (left and right at 30 frames/s independently).
Stereo camera pairs can be positioned in one of two
ways when creating S3-D imageseither in a towing
angle or in a flat angleto achieve the correct FOV.
Based on the sensor characteristics, resolution and
focal length, a designer will be able to decide on the
best recording distance between the stereo pair. Posi-
tioning of the stereo pair is extremely crucial for get-
ting the right convergence plane. The stereo pair can
be positioned at a distance of 65 mm (like human
eyes) to yield a large recording distance. In designing
a smartphone or other device with similar size attrib-
utes, the designer can consider keeping the position-
ing at a distance of 35 mm, to achieve a personalized
recording distance (1-meter to 3-meter range).
Such camera pairs, when placed on the gadgets, do
not necessarily align mechanically perfectly in transla-
tional and rotational directions (Figures 2 and 3).
There can be minor misalignment in the millimeters
while placing the sensor modules on the form factor
device. Such minor variations in physical placements
in translational and rotational directions can create
large misalignment variations in the image plane. This
imposes a huge challenge in terms of calibrating the
misalignments up front and correcting the misalign-
ment on a per-frame basis while the content is created.
Furthermore, a devices mechanical aspectseven
temperature variations and the occasional falling of
the gadgetcan create such misalignment between
the stereo pair of sensors. It therefore becomes vital to
correct such variations in real-time.
Once content is created, it is important to ensure it
is viewable on the target devices. System software
running in the gadget should be capable of doing the
following to provide successful S3-D content viewing
experiences:
Combine the stereo image pair and process using
the image signal processing (ISP) unit for the cor-
rect resolution, distortion corrections, image
quality tuning and more.
Decide the convergence plane at run-time using
efficient algorithms, and create disparity vectors
for the stereo pair at run-time to provide pleasing
viewer experiences.
Correct for the misalignments in translational
and rotational directions at run-time between the
stereo image pair, and apply the corrections off-
sets per frame.
Synchronize the 3A (auto-exposure, auto-white
balance, autofocus) between the sensor modules,
and fine-tune the image tuning parameters.
These operations require very sophisticated hardware
accelerators that can run and process the stereo pair of high-
resolution images. Such accelerators are fundamental to next-
generation application processors.
Through convergence and misalignment corrections,
processed image pairs are passed to the video accelerators of
34 Electronic Engineering Times June 6, 2011
DESIGN PRODUCTS
+
Figure 1
the application processors to encode data in 3-D formats.
Todays H.264 codec offers an extension to process the S3-D
information using supplementary enhancement information
(SEI), which describes the format and layout of the encoded
S3-D scene.
Emerging standards such as Multi-View Codec (MVC) let
designers encode more than two views for true S3-D effects
using multiple views. MVC codecs correlate the left- and
right-view pair for spatial predictions and motion estima-
tions for effective bit rate savings while encoding. Utilizing
the information between the left and right pair for effective
bandwidth reduction can improve the system data usage dur-
ing an S3-D video conference, for example, since users in such
instances are limited by network bandwidth.
Video encoders and decoders have S3-D awareness based on
the content layout. The left and right images can be formatted
in multiple ways (side by side, top/bottom, interleaved [col-
umn/row] and more). Based on the formatted layout gathered,
information is decoded and provided back to the displays sub-
system for rendering the data in stereoscopic fashion.
Generating S3-D experiences
Stereoscopic viewing experiences can be generated in multi-
ple forms. Two of the most popular ways to view S3-D are
through LCD shutter glasses and on autostereoscopic LCD
panels. Shutter glasses achieve S3-D experiences by rendering
50 percent of the rendered pictures for the left eye and the
other 50 percent for the right eye. A technique called time-
sequential multiplexing then alternately displays the left-
and right-eye images every time the computer refreshes
(draws) the screen.
Turning the shutters on the left and right lenses of the
glasses using the sync signals generated from the TV creates
an S3-D effect for users. It is important to realize that syn-
chronizations need to happen very fast (faster than can be
perceived) to ensure that a user thinks he or she is seeing true
S3-D. That requires immense processing power on the part of
the display subsystem of application processors, especially
when dealing with high-definition video.
For glasses-free 3-D, autostereoscopic LCD panels display
multiple views on the LCD panel. Examples of autostereo-
scopic displays include parallax barrier, lenticular and time-
sequential LCD panels.
The parallax barrier, placed in front of the LCD, consists
of a layer of material with a series of precision slits, allow-
ing each eye to see a different set of pixels and thereby creat-
ing a sense of depth through parallax. The viewing angle of
a parallax barrier LCD is limited, and the resolution of the
pixel count is reduced by half in the horizontal direction;
half the pixel count is seen by the left eye and half by the
right eye.
Lenticular displays use two-dimensional arrays of lenslets
designed so that when the arrays are viewed from slightly dif-
ferent angles, an S3-D effect is created. Time-sequential LCD
panels use an S3-D film (creating an angular view of light
flow through the film) in front of the LCD, controlling the
backlights placed on either side of the LCD at a 120-Hz
refresh rate to create a 3-D viewing experience for the users.
Unlike parallax barrier LCD panels, 3-D film-based time-
sequential panels produce a full-resolution S3-D experience.
Autostereoscopic panels are becoming popular in mobile
devices. The panels need extensive display processing capabil-
ities at the pixel level to format and create an S3-D viewing
experiences in real-time. The display processing has to be
effective at column/row/pixel interleaving for HD-resolution
stereo pairs at 60 frames/s.
S3-D viewing quality poses many challenges, and it varies
with respect to the size of the LCD screen and the angle at
which the user is viewing the content. It is important for the
created S3-D content to address convergence issues and mis-
alignment corrections, and to enable the appropriate level of
disparity in the video. If this is not done effectively, the view-
ing experiences can irritate human eyes.
Research continues with respect to disparity corrections,
depth grading and scene ramping (changing disparity based
on the scene pattern changes) to provide positive viewing
experiences.
The computational power needed to run such content-cre-
ation algorithms and pixel-level display processing subsys-
tems requires that application processors emerge to meet the
needs of S3-D HD systems. Devices with immense processing
power inside can provide pleasing and natural viewing expe-
riences to users, adding the dimension for which S3-D will be
known.
Keep an eye out this year for S3-D-enabled mobile devices.
p
Veera Manikandan Raju is engineering manager for
Texas Instruments Natural User Interface group, which
is part TIs Wireless business unit. He studied at the
Regional Engineering School of Trichirappalli, India.
June 6, 2011 Electronic Engineering Times 35
DESIGN PRODUCTS
+
Figure 3
Figure 2
6,898,700,000
The approximate number of
people on earth.
At Allied Electronics, youre
more than just a number.
We are here to help you get what
you need when you need it.
Call 1.800.433.5700 to
experience Allieds first-class service.
Local sales offices
D
edicated account managers
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THINK ALLIED
SM
Electronic Engineering Times June 6, 2011 37
DESIGN PRODUCTS
+
A FEW YEARS AGO, when I was
searching for a new phone, I dearly
wanted a Wi-Fi-enabled model. But
none of the cell-phone vendors in my
vicinity carried one in stock. In fact, a
number of them responded to my
inquiries with blank looks, as if Id been
speaking a foreign language.
Fast forward to todays wireless cli-
mate, where the passage of a few years
has yielded some serious technical
innovation.
In light of Qualcomms recent pur-
chase of Atheros Communications,
UBM TechInsights decided to review
the product offerings of both Atheros
and Qualcomm to assess the impact
on the handset market, including sili-
con vendors, in our research for our
study on the WPAN market landscape
(http://tiny.cc/iy6lp).
Atheros is known for its wireless
LAN (Wi-Fi) products, from which it
derives close to 80 percent of its rev-
enue. Over the past six years, however,
the company has been steadily trying to
diversify its offerings with five acquisi-
tions. It now offers Bluetooth, GPS, Eth-
ernet, powerline networking and
passive optical network solutions.
The study undertaken by UBM
TechInsights looked at 220 handsets
with integrated Qualcomm basebands
over a 10-year period. The study also
gauged the technologys adoption rate
as a measure of total systems vs. sys-
tems with Bluetooth and/or Wi-Fi.
Bluetooth, which began to be de-
ployed starting in 2003, had achieved a
100 percent adoption rate in handsets
by 2010.
During this same period, Wi-Fi
deployment significantly lagged that
for Bluetooth, as it had to wait for the
market, as well as the technology, to
converge. From 2008, however, Wi-Fi
deployment began to experience explo-
sive growth, and by 2010 the technolo-
gy had a 92 percent adoption rate. That
conclusion came from a sample set for
2010 that consisted of 26 phones.
Also interesting in terms of the study
was the adoption rate for combination
chips. (A combo chip is a multifunction
chip or integrated package [multichip
module, or MCM] with Bluetooth and
Wi-Fi; in many cases, combo chips
include FM support as well.) Some com-
panies, such as Murata, are now creat-
ing combo MCMs that have a very
small footprints. A select number of sili-
con providers, such as Broadcom and
Mfr. unknown
GPS LNA?
Memsic
#MMC314xMS
3-axis compass
Die #4.1 Memsic, compass processor
Die #4.2 Memsic, magnetic sensor (qty 3)
Bosch Sensortec
#BMA150
3-axis MEMS accelerometer
Die #8.1 Bosch, signal processor
Die #8.2 Bosch, MEMS sensor
Atheros
#AR6003
Single-chip Wi-Fi
Fairchild Semiconductor
#FSA9280AUMX
USB multimedia switch
Murata
#XM2400SN
SP3T switch
Broadcom
#BCM2078
Bluetooth + FM radio
Wide Bluetooth, Wi-Fi adoption
seen in handsets
By Gordon Holstead
UNDER
THE HOOD
Gordon Holstead
(gholstead@ubmtechinsights.com)
is senior analyst at UBM
TechInsights.
Texas Instruments, have created single-
chip Bluetooth/Wi-Fi/FM solutions, and
the module manufacturers are taking
advantage of that availability.
The trend toward adoption of the
single-chip silicon solution was at 62
percent in 2010, compared with 69 per-
cent for the combo module (MCM).
There is an upward trend toward inte-
gration of connectivity functionality
such as Wi-Fi, Bluetooth and FM; today
most combination products are single-
chip silicon solutions.
An example of a popular and simpli-
fied solution from a module manufactur-
er, such as Murata or Samsung, contains
a single die with an additional set of dis-
crete components, such as the Samsung
module found in the Samsung Galaxy
Spica. This handset uses the Broadcom
BCM4325, a single-pole/double-throw
(SPDT) switch and various discretes. The
module measures 8.25 x 7.75 mm.
Less common in modules are multi-
die, multifunction solutions, like the one
found in the Sony Ericsson X2. In this
case, the module maker, Murata, has inte-
grated an Atheros AR6002 (Wi-Fi) chip
and a single-die Qualcomm Bluetooth
with two switches and other compo-
nents. The package size is 9.70 x 9.17 mm.
Some companies are still choosing to
populate the main circuit board with
multidie and discrete components, as can
be seen in the Samsung GT-I5503 Galaxy
5, which uses the Atheros AR6003 (for
Wi-Fi) together with a Broadcom
BCM2078 (Bluetooth/FM) chip.
With adoption rates of more than 60
percent for single-die multifunction
(Bluetooth/Wi-Fi) solutionsmany of
which are offered by companies like
Atheros, Broadcom and Marvellit
seems Qualcomm had better move fast
to expand its product family to include
single-package (that is, MCM) wireless
connectivity solutions. It could be a few
years however, before we see a single-
package solution from Qualcomm, even
with its acquisition of Atheros.
Broadcom and Texas Instruments
currently command the bulk of design
wins in the combo Bluetooth/Wi-Fi/FM
market, as weve seen in numerous tear-
downs conducted over the past year on
numerous handsets and tablets. On the
integration front, Texas Instruments
released a quad-radio (Bluetooth/Wi-
Fi/FM/GPS) single-die solution, the
WL1283, which was the combo chip of
choice for the RIM BlackBerry Play-
Book. A product announcement from
Broadcom on a quad-radio single-die
solution is still forthcoming; but with
Texas Instruments having successfully
designed a solution, the opportunity for
significant market share and a chance
to displace Broadcom as the leader in
the connectivity market are now in that
companys control.
Even so, Qualcomm remains well
positioned to capture a portion of the
connectivity market, if it can provide
a cost-effective integrated solution that
leverages its new partnership with
Atheros.
p
38 Electronic Engineering Times June 6, 2011
DESIGN PRODUCTS
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June 6, 2011 Electronic Engineering Times 41
DESIGN PRODUCTS
+
YOU WENT THROUGH a process to select an opera-
tional amplifier (op amp) for your circuit based on
the parameters most critical to your application.
Some of the parameters you reviewed may have
included supply voltage, gain bandwidth product,
slew rate and input noise voltage, to name a few.
You also accounted for input common-mode range,
a key parameter for all op-amp applications in your
circuit, right? If your answer is no, you should contin-
ue reading this article. Even if your answer is yes, you
may still find this material useful.
Engineers who have worked with op amps
throughout their careers have likely experienced sit-
uations where an op amp was behaving in an unex-
pected manner. The nice thing about op amps is that
the output often tells the story. In many cases, if
something is not quite right, it shows up in an obvi-
ous way at the output pin. Undesirable output wave-
forms can be caused by limitations at the output
stage. Perhaps an oscillation is observed that is
caused by too much capacitance on the output. Or
maybe clipping occurs before reaching the full rail
voltage because the output stage is limited to voltage
swings less than the supply-rail voltage.
It is also possible for strange behavior to appear at
the op amps output that has nothing to do with the
output stage. Sometimes the undesirable output sig-
nal may result from something wrong at the input
side of the device. One of the most common issues
experienced with op amps is violation of the devices
input common-mode range. But what exactly is input
common-mode range, and what is the impact of vio-
lating or exceeding it?
Defining input common-mode range
When speaking of op-amp inputs, input common-mode volt-
age (V
ICM
) is one of the first terms of which an engineer thinks,
but may lead to some initial confusion. V
ICM
describes a partic-
ular voltage level and is defined as the average voltage at the
inverting and non-inverting input pins (Figure 1). It is com-
monly expressed as: V
ICM
= [V
IN
(+)+V
IN
()]/2.
Another way to think of V
ICM
is that it is the voltage level
common to both non-inverting and inverting inputs, V
IN
(+)
and V
IN
(). As it turns out, in most applications V
IN
(+) is
very close to V
IN
() because closed-loop negative feedback
causes one input pin to closely track the other such that the
difference between V
IN
(+) and V
IN
() is close to zero.
This is true for many common circuits, including voltage
followers, inverting and non-inverting configurations. In
these cases it is commonly assumed that V
IN
(+) = V
IN
() =
V
ICM
, since these voltages are approximately the same.
Another term used to describe op-amp inputs is input com-
mon-mode range (V
ICMR
), or more correctly input common-mode
voltage range. This is the parameter most often used in
datasheets and also the one where circuit designers should be
most concerned. V
ICMR
defines a range of common-mode input
voltages that results in proper operation of the op-amp device,
and describes how close the inputs can get to either supply rail.
Another way to think of V
ICMR
is that it describes a range
defined by V
ICMR_MIN
and V
ICMR_MAX
. As shown in Figure 2,
V
ICMR
is described by:
Are you violating your op amps input
common-mode range?
By Todd Toporski
PLANET ANALOG
Figure 1: Input common-mode voltage for an op amp.
Figure 2: Input common-mode voltage range for op amp.
42 Electronic Engineering Times June 6, 2011
DESIGN PRODUCTS
+
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V
ICMR
= V
ICMR_MAX
V
ICMR_MIN
Where
V
ICMR_MIN
= limit relative to VCC supply rail
V
ICMR_MAX
= limit relative to VCC+ supply rail
When V
ICMR
is exceeded, the normal linear operation of the op amp is not guar-
anteed. Therefore, it is critical to ensure that the entire range of the input signal is
fully understood and that V
ICMR
is not exceeded.
Another point of confusion may be that V
ICM
and V
ICMR
are not standardized
abbreviations and various datasheets from various IC suppliers often use different
terminology including V
CM
, V
IC
, V
CMR
, etc. Consequently, it is necessary to under-
stand that the specification youre looking for is more than a particular input voltage
it is an input voltage range.
V
ICMR
varies among op amps
The input stage of an op amp is dictated by design specifications and the type of op-
amp process technology used. For example, the input stage of a CMOS op amp is dif-
ferent from that of a bipolar op amp, which is different than that of a JFET op amp,
etc. While the specific details of op-amp input stages and process technologies are
beyond the scope of this article, it is important to note these differences exist among
various op-amp devices.
Table 1 shows several examples of op amps from TI and their V
ICMR
. The Max Sup-
ply Range column describes split-supply and single-supply (in parentheses) limita-
tions. From the table it is clear that the input range, V
ICMR
, is quite different from op
amp to op amp. Depending on the type of device, V
ICMR
may fall within or beyond
the supply rails. Hence, never assume that an op amp can receive a particular input
signal range until it is verified in the datasheet specifications.
Table 1: V
ICMR
examples for several different types of op amps.
Device Technology Max Supply Range (V) V
ICMR_MIN
V
ICMR_MAX
TLE2062A JFET input VCC+/ = +/19 V (38 V) (VCC-) + 3.4 V (VCC+) 1 V
TLC2272 LinCMOS VCC+/ = +/8 V (16 V) (VCC-) 0.3 V (VCC+) - 0.8 V
TL971 BiCMOS VCC+/ = +/7.5 V (15 V) (VCC-) + 1.15 V (VCC+) 1.15 V
OPA333 CMOS/R-R input VCC+/ = +/2.75 V (5.5 V) (VCC-) 0.1 V (VCC+) + 0.1 V
OPA735 CMOS VCC+/ = +/6 V (12 V) (VCC-) 0.1 V (VCC+) 1.5 V
One special case worth mentioning for wide input ranges is the rail-to-rail input op
amp. Although the name implies an op amp whose input can span the entire supply-
rail range, not all rail-to-rail input devices cover the entire supply range as many
might assume. Its true that many rail-to-rail input op amps do span the entire supply
range (such as the OPA333 in Table 1), but there are others that fall a little short and
are misleading in their description. Again, it is critical to review the specified input
range in the datasheet.
Examples of violating V
ICMR
Violating V
ICMR
is commonly seen in single-supply op-amp applications where the
negative rail is often ground, or 0 V, and the positive rail is some positive voltage such
as 3.3 V, 5 V, or higher voltages. In these applications, the input signal range typically
is not very wide, and the input signal and V
ICMR
must be well understood to make
sure proper op-amp operation results.
p
Todd Toporski is a member of Group Technical Staff at Texas Instruments where he special-
izes in analog applications.
l MORE Read the full story at www.eetimes.com/4215414.