DM816x/C6A816x/AM389x DDR3 Bring-up Overview

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Introduction
DDR3 board bring-up requires additional steps vs. DDR2. This presentation outlines the procedure required for a successful bring-up of a DM816x/C6A816x/AM389x DDR3 system. In order to achieve higher data transfer rates DDR3 has built in compensation for system flight times. System flight time is a function of board routing, for both read and write. For the automatic compensation to converge it need to be seeded with board routing information.
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DDR3 SDRAM Fundamentals

DDR3 1.5V supply vs. 1.8V DDR2. 8-burst-deep pre-fetch buffer vs. 4-burst-deep DDR2 System-level flight-time compensation Introduction of CWL (CAS write latency) per clock bin On-die I/O calibration engine READ and WRITE calibration Standard Name
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

JEDEC Standard Memories

I/O Bus Clock (MHz) Data Rate (MT/s)

Supported on Device
I/O Bus Clock (MHz) Data Rate (MT/s)

400 533 667 800

800 1066 1333 1600

398.25 531 666 796.5

796.5 1062 1333 1593

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DDR3 SDRAM Leveling

System-level flight-time compensation - Goals
Aligning DQS w.r.t DDR clock during write operation. Aligning ADDR/CMD w.r.t DDR clock. Aligning DQ w.r.t. DQS during write operation. Offset DQ w.r.t DQS during read operation. Read FIFO WE alignment.

Leveling Mechanism
Algorithm based leveling searches
Executed after each device power-up. Compensates for the specific board delays and the specific silicon performance (both SDRAM and Device).

Algorithm starting point must be seeded for correct operation

Correct seed values are defined by the customers board routing. Seed values need to be determined once per board layout design.
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DDR3 Bring-up
The following steps are required (once per board design) 1. Calculate seed values for the leveling mechanism.
a) DDR3 routing measurements from board and critical memory parameters are fed into a calculator. b) Calculator provides the initial seed values.

2. Validate initial seed values in the system

a) Seed values are input into a program that runs on device in the target system. b) Program searches to determine good seed parameters.

3. Update uboot code to correctly configure DDR

1. Good seed parameters merged into the uboot code. 2. Other critical EMIF configuration items e.g. CAS latency are merged into the uboot code.

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