Linear Integrated Circuits

Date:

Experiment No: 1
Study of Data sheets ( A 741, OP-07, LM 311, LM 308)
Aim: To study Data sheets of different Operational amplifiers such as A 741,OP-07, LM 311,LM 308 The information found on the data sheets can be broken into following groups. 1. At the top of the data sheet is a device number and brief description of the basic type of the device. 2. A general description is given that includes the construction process. 3. Absolute maximum ratings for the proper operation of the device are specified. 4. The pin configuration (connection diagram), package type and other information are given. 5. The internal schematic diagram is given. 6. Electrical characteristics and parameters values under specific conditions are also given. The features of A 741 are as follows. 1. No external frequency compensation is required. 2. Short circuit protection. 3. Offset null capability. 4. Large common-mode and differential voltage range. 5. Low power consumption. 6. No latch-up problem.

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Comparison Table. IC/Parameters Vio IB Iio I/P Resistance O/P Resisitance CMRR Slew rate Large signal Voltage gain O/p voltage swing Questions: 1. Define and explain different electrical characteristics of Op-amp. A 741 OP07` LM 311 LM 308

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Date:

Experiment No: 2 To calculate Different electric parameters using IC741. Aim: 1) To measure input offset voltage.
2) To measure input Bias current (IB) 3) To measure CMRR 4) To measure Slew rate

Part A Theory:
For an operational amplifier, it is expected that, on shorting both, the inverting and noninverting terminals to ground, o/p voltage should be zero. However, for a practical opamp, due to mismatching between circuitry that processes non-inverting and inverting terminal voltages/p voltage is not zero when both the i/ps are grounded. The amount of i/p voltage to be connected between i/p terminals of an op-amp to make the o/p zero is called as i/p offset voltage.(Vio) The value as well as polarity of Vio for each IC is different even if it is of the same number. Measurement of Vio: To improve the accuracy of reading, we can amplify the i/p-offset voltage by using Rf and R1. The formula for o/p voltage is Vo=(1+Rf/R1) Vio. Using this formula, we can find the Vio. Circuit Diagram:

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Apparatus:
IC-741, Power supply, Breadboard, Multimeter.

Procedure:
1. Check all connections. 2. Assemble the circuit on the breadboard. 3. Measure the o/p voltage Vout and write the readings. 4. Compare Vio with the value specified by manufacturer. 5. Calculate the value of Vio.

Observation Table:
For IC 741: Vout = ___________.V

Calculations:
Vio=Vout= _________.V

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Part B Theory:
The ideal op-amp has infinite i/p resistance. It means that, the current taken by the i/p terminal of an op-amp is zero. However, I/p terminals of practical op-amp draw a small amount of current. This current is required for biasing the internal transistors. Such current is known as Input Bias Current. Input Bias Current: It is the average of currents that flows into inverting and noninverting terminals of OP-amp. IB = [I(-) + I(+)]/2 For IC 741, IB=80nA(typical) and 200nA (max). Input offset current: The algebraic difference between the currents into inverting and non-inverting terminals is referred as input offset current. Iio = I (B+) I (B-) The value of offset current is usually in order of nA. Circuit Diagram:

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Procedure:
1. Check all connections. 2. Assemble the circuit on the breadboard. 3. Measure the o/p voltage Vout and write the readings.

Observations:
Sr.No. 1 2 3 4 SW1 ON OFF ON OFF SW2 ON ON OFF OFF Formula for VO Vio Vio I(B+) R1 Vio + I(B-) R2 Vio + I(B-) R2 I(B+) R1 Vo observed

Calculations:

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Part C Theory:
Common mode rejection ratio is defined as ratio of differential voltage gain to the common mode gain.

CMRR = Ad/Acm
When operated in differential mode, the op-amp produces large noise or hum pickup. Thus it is to connect op-amp in common mode to reduce noise. For IC 741 CMRR is typically 90dB.

Circuit Diagram:

Procedure:
1. Make connections as per circuit diagram. 2. Apply 5Vpp signbal at 1KHz frequency. 3. Measure Vo(Cm).

Observations: Vocm= ________V. Calculations: Acm= Ad/Acm

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Ad=Rf/R1

CMRR = Ad/Acm

In dB CMRR = 20 log (Ad/Acm)

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Part D Theory:
Slew rate is defined as rate of change of output voltage per change in input frequency. Slew rate is one of the dynamic limitations of op-amp. Slew rate is caused by saturation of internal stages of op-amp and also due to current limiting, when a high frequency, large amplitude signal is applied.

Circuit diagram:

Procedure:
1. Check all the connections. 2. Set the square wave frequency to 50KHz 5Vpp. And connect as input to the opamp. 3. Observe the o/p waveform simultaneously. 4. Calculate the slope. 5. Draw i/p and o/p waveforms.

Observations:
Observed Slew rate: __________________V/ sec. Calculations:

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Conclusion:

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Date:

Experiment No: 3 Study of Op-amp as inverting and non-inverting amplifier. Aim: To study op-amp as inverting and non-inverting amplifier for both DC and AC
inputs.

Apparatus:
Function generator, Power supply, CRO.DMM, Breadboard, Ic741, Resistors. Etc

Theory:
In inverting amplifier one input is applied to inverting input terminal. The noninverting terminal is grounded. Since V1=oV V2=Vin Vo= -Avin The ve sign indicates that the o/p is inverted i.e. out of phase w.r.t i/p. Thus in inverting amplifier the i/p signal is amplified by gain A and also inverted at o/p. In inverting amplifier one input is applied to inverting input terminal. The noninverting terminal is grounded. Since V2=oV V1=Vin Vo= Avin The +ve sign indicates that the o/p is. in phase w.r.t i/p. Thus in noninverting amplifier the i/p signal is amplified by gain A.

Procedure:
For DC i/p (inverting amplifier): 1. Connect the circuit as shown in fig. 2. Apply dc i/p to inverting i/p terminal. 3. Observe the o/p voltage. 4. Compare with theoretical o/p. For DC i/p (non-inverting amplifier): 1. Connect the circuit as shown in fig. 2. Apply dc i/p to non- inverting i/p terminal.

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3. Observe the o/p voltage. 4. Compare with theoretical o/p. For AC i/p (inverting amplifier):: 1. Connect the circuit as shown in fig. 2. Apply ac i/p voltage 1Vp-p to inverting i/p terminal. 3. Observe the o/p voltage. 4. Calculate gain. 5. Plot graph of i/p frequency Vs o/p gain . For AC i/p (non-inverting amplifier): 1. Connect the circuit as shown in fig. 2. Apply ac i/p voltage 1Vp-p to non- inverting i/p terminal. 3. Observe the o/p voltage. 4. Calculate gain. 5. Plot graph of i/p frequency Vs o/p gain .

Circuit Diagram:

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Observation Table: For DC i/p Sr.no Vin Vo (Observed) Inverting Vo (Theoretical) Vo (Observed) Non-Inverting Vo (Theoretical)

Inverting For AC i/p: For Vin = ______Vp-p Sr.no Fin (Hz) Vo (Observed) Gain (dB) Vo (Theoretical)

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Non-Inverting Sr.no

Fin (Hz)

Vo (Observed)

Gain (dB)

Vo (Theoretical)

Calculations:
For DC i/p: Vo= (-Rf/R1) Vin Vo= (1+Rf/R1) Vin

For AC i/p: Gain = 20 log(Vo/Vin)

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Conclusion:

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Date:

Experiment No: 4 Op-amp as a summing, averaging and scaling amplifier Aim: 1) To study op-amp inverting amplifier as a summing, averaging and scaling
amplifier. 2) To study op-amp non-inverting amplifier as a summing and averaging amplifier.

Apparatus:
Function generator, Power supply, CRO.DMM, Breadboard, IC741, Resistors. Etc

Theory:
Inverting configuration: As shown in fig. Inverting configuration with three i/ps Va, Vb, Vc. Depending on relationship between the feedback resistor Rf and i/p resistor Ra, Rb and Rc the circuit can be used as summing amplifier, a scaling amplifier and averaging amplifier. The circuit function can be verified by examining the expression for the o/p voltage Vo, which is obtained from Kirchoffs current equation at node V2 Ia +Ib + Ic=IB +If As IB=0A and V1=oV=V2 Va/Ra + Vb/Rb + Vc/Rc = - Vo/Rf OR V0 = - ( Rf/Ra Va + Rf/Vb Vb + Rf/Rc Vc) a) Summing Amplifier: If in the circuit, Ra =Rb =Rc=R Then Vo= - Rf/R (Va +Vb + Vc) And if Rf=R Vo= - (Va +Vb + Vc) b) Scaling OR Weighted amplifier: If each i/p voltage is amplified by different factor in other words, weighted differently at o/p, is then called as a scaling or weighted amplifier. Vo= - (Rf/Ra Va + Rf/Rb Vb + Rf/Rc Vc) Where Rf/Ra Rf/Rb Rf/Rc

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b) Averaging amplifier Vo is average of inputs voltages, For that Ra =Rb =Rc =R and gain of amplifier must be 1. Rf/R =i/n where n= no. of I/ps We want Rf/R =3 Vo= -(Va+Vb +Vc)/3 Non-inverting configuration: We know that i/p resistance Rif of the non-inverting amplifier is very large. Therefore using Superposition theorem the voltage V1 at non-inverting terminal is V1 =Va/3 + Vb/3 + Vc/3 If the gain of amplifier =1 V1 = (Va +Vb +Vc)/3 Summing amplifier: If (1 +Rf/R1) is equal to number of i/ps the o/p voltage becomes equal to sum of all i/p voltages. i.e. if (1 +Rf/R1) =3 Vo= Va +Vb + Vc Hence the circuit is called a non-inverting summing amplifier.

Procedure:
1. Connect the circuit as per ckt. diagram. 2. Apply three i/p voltages Va, Vb, Vc at inverting i/p terminal. 3. Observe o/p voltage at o/p terminal. 4. Do suitable calculations.

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Circuit Diagram:

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Observation Table: Inverting configuration (DC inputs)

For summing amplifier: Va(V) Vb(V) Vc(v) Vo (TH) Vo (Observed)

For scaling amplifier: Va (V) Scaling Factor

Vo (TH)

Vo (Observed)

For averaging amplifier: Va (V) Vb (V)

Vc (V)

Vo (TH)

Vo (Observed)

For Non-inverting configuration:

For summing amplifier: Va (V) Vb(V) Vc(v) Vo (TH) Vo (Observed)

For averaging amplifier: Va (V) Vb (V)

Vc (V)

Vo (TH)

Vo (Observed)

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Inverting configuration (AC inputs)

For summing amplifier: Va(V) Vb(V) Vc(v) Vo (TH) Vo (Observed)

For scaling amplifier: Va (V) Scaling Factor

Vo (TH)

Vo (Observed)

For averaging amplifier: Va (V) Vb (V)

Vc (V)

Vo (TH)

Vo (Observed)

For Non-inverting configuration:

For summing amplifier: Va (V) Vb(V) Vc(v) Vo (TH) Vo (Observed)

For averaging amplifier: Va (V) Vb (V)

Vc (V)

Vo (TH)

Vo (Observed)

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Calculation:

Conclusion:

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Date: Experiment No: 5 Op-amp as a Schmitt Trigger. Aim: Study of Schmitt Trigger using IC 741 Apparatus:
Function generator, Power supply, CRO.DMM, Breadboard, Ic741, Resistors. Etc

Theory:
Schmitt trigger converts irregular-shaped waveforms to a square wave or pulse. It is also known as squaring circuit. The i/p voltage Vin triggers (changes the state of) the o/p Vo every time it exceeds certain voltage levels called the upper threshold voltage Vut and lower threshold Vil, as shown in fig. These threshold voltages are obtained by using the voltages divider R1 R2, where the voltage across R1 is fed back to (+) i/p. The voltage across R1 is a variable reference threshold voltage that depends on the value and polarity of the o/p voltage Vo.When Vo= + Vsat, the voltage across R1 is Vut. The i/p Vin must be slightly more positive than Vut in order to cause the Vo to switch from +Vsat to Vsat. As long as Vin<Vut,Vo is at +Vsat. Using the Voltage divider rule, Vut = (R1/R1 +R2 ) (+Vsat) On the other hand, when Vo = -Vsat,thye voltage across R1 is referred to as Vlt.Vin must be slightly more negative tyhan Vlt in order to cause Vo to switch from Vsat to +Vsat.i.e. Vin>Vlt. Vlt = ( R1/R1+R2) (-Vsat) Thus, if threshold voltages Vut and Vlt are made larger than input noise voltages, the positive feedback will eliminate the false transition.Also the + f/b because of its regenerative action,will make Vo switch faster between +Vsat and Vsat. The hystersis voltage is difference between Vut and Vlt. Vhy = Vut Vlt = R1/R1+R2 [+vsat (-Vsat) ]

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Circuit Diagram:

Procedure:
1. 1.Connect the circuit as per ckt. Diagram

2. For Schmitt Trigger set input signal (say 1V, 1 KHz) using signal generator. 3. Observe the input and output waveforms on the CRO.
4. Plot the graphs: Vi vs Time, VO vs Time.

Calculation:
Vut = (R1/R1 +R2 ) (+Vsat)

Vlt = ( R1/R1+R2) (-Vsat) For Hystresis Vhy = Vut Vlt = R1/R1+R2 [+vsat (-Vsat) ]

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Conclusion:

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Date: Experiment No: 6 Butterworth Filter( 1st Order LPF and HPF) Aim To study butterworth filter (LPF, HPF)
1.To find out fc(cutoff frequency)LPF 2.To find out fc(cutoff frequency)HPF

Apparatus:
Function generator, Power supply, CRO.DMM, Breadboard, Ic741, Resistors, Capacitors Etc

Theory:
PART A

fig shows a first order low pass butter worth filter that uses an RC network for filtering .note that op-amp is used in non-inverting configuration; hence it doesn't load down RC network .Resistors R1and Rf determine the gain of filter. According to the voltage divider rule the voltage at non-inverting terminal (across capacitor c) is V1=-(jXc/R-JXc)*Vin Where, J=sqrt(-1) and -JXc=i/(2*pie*f*c) Simplifying the equation we get , V1=Vin/(1+j*2*pie*F*R*C) The output voltage is Vo=(1+Rf/R1)*v1 i.e vO=(1+Rf/R1)*(Vin/1+J*2*PIE*F*R*C) OR Vo/Vin=Af/(1+J (f/fh)).........1 Where Vo/Vin=gain of the filter as a function of frequency Af=1+(Rf/R1)=pass band gain of filter F=frequency of input signal Fh=1/(2*pie*R*C)=high cutoff frequency of filter The gain magnitude and phase angle equation of low pass filter can be obtain by converting (1) into its equivalent polar form as follows:
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Vo\Vin|=Af/sqrt(1+(f/fH)2).......2 Magnitude eq (2) 1.At very low frequency,that is,f<fH, |Vo/Vin|=Af 2.at f=fH |Vo/Vin|=0.707*AF 3.AT F>Fh

Vo/Vi|<Af

Thus low pass filter has constant gain Af from 0hz to high cutoff frequency fH.at fH gain is 0.707AF,after fH decreases at constant rate with increase in frequency. That is, when frequency is increased tenfold, the voltage gain is divided by 10.in other words; gain decreases 20db each time the frequency is increased by 10.Hence the rate at which gain rolls off after fH is 20db /decade. Frequency f=fH is called the cutoff frequency because the gain of filter at this frequency is down by 3db from 0hz.other equivalent term for cutoff frequency are -3db frequency, break frequency or corner frequency. CIRCUIT DIAGRAM:

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Procedure:
1. Connect the circuit as per the circuit diagram 2. Give the input signal as specified 3. Switch on the dual power supply. 4. Note down the outputs from the CRO. 5. Draw the necessary waveforms on the graph sheet

Observation table:
For Vin=1 vpp

Sr.no

Fin

Vo

Gain (db)

Calculation:

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Conclusion:

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Date: Experiment No: 7 Study of Precision Rectifier. Aim To study IC 741 as

1) Half wave precision rectifier. 2) Full wave precision rectifier.

Apparatus:
Function generator, Power supply, CRO, Breadboard, IC-741 Resistors, Capacitors, Diode Etc

Theory:
The diode acts as a rectifier, which changes ac signal into dc signal. But the diode doesnt conduct until voltage drop across it is greater than 0.3 V for Ge and 0.7 V for Si. When a small signal is applied neither of these diode alone is suitable for rectification of small signal less below threshold or cut in voltage of it. By using diode with op-amp we can rectify small signals also. The circuit is called as Precision Rectifier. CIRCUIT DIAGRAM: Half wave Rectifier:

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Full wave Rectifier

Procedure:
1. Connect the circuit as per the circuit diagram 2. Apply the 1KHz and 0.2 Vp-p sine wave as i/p to the half wave rectifier. 3. Switch on the dual power supply.

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4. Observe outputs from the CRO. 5. Then apply the sine wave to i/p of full wave rectifier and observe the o/p on the CRO. 6. Draw the graph for i/p and o/p.

Conclusion:

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Experiment No: 8 Study of Wien Bridge Oscillator. Aim To study IC 741 as

3) Wien Bridge oscillator

Apparatus:
Function generator, Power supply, CRO, Breadboard, IC-741, Resistors, Capacitors Etc

Theory:

Circuit Diagram:

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Procedure:
1. Connect the circuit as per the circuit diagram 2. From given value of R and C ,calculate frequency of oscillation(fo). 3. Connect the DC power supply.
4. Check the output at pin-6 of IC741 for oscillations.

Calculations: F0=1/2RC Theoretical Practical

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Conclusion:

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Experiment No: 9 Study of Square wave Generator using op-amp. Aim To study IC 741 as square wave generator. Apparatus:
Function generator, Power supply, CRO, Breadboard, IC-741, Resistors, Capacitors Etc

Theory:
The principle of generation of square wave o/p is to force an op-amp to operate in saturation region, that is, the o/p of op-amp is forced to swing between positive saturation(+Vsat) and negative saturation(-Vsat), thus the resulting o/p of op-amp is square wave. The o/p of op-amp is positive saturation & negative saturation, depending on whether the differential voltage is positive or negative. The voltage across R1 due to Vsat is: V1=[R1/(R1+R2)] x (-Vsat) The voltage across R1 due to +Vsat is: V1=[R1/(R1+R2)] x (+Vsat) The time period T of the w/f T=2Rc ln[2R1+R2)/R2] The frequency is :

f0=1/T Design Problem:

Design a square wave generator using op-amp for frequency of 1kHz.

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Circuit Diagram:

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Procedure:
1. Connect the circuit as per the circuit diagram 2. Connect the DC power supply.
3. Check the output at pin-6 of IC741.

4. Observe the waveform across the capacitor.

Conclusion:

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Date:

Experiment No: 10 Timer IC 555 (Astable multivibrator mode) and Astable multivibrator as a Square wave oscillator. Aim To study Timer IC 555 as
4) Astable Multivibrator mode. 5) Square wave oscillator.

Apparatus:
Function generator, Power supply, CRO.DMM, Breadboard, IC-555 Resistors, Capacitors Etc

Theory:
As shown in Fig. The timer 555 connected as an astable multivibrator. Initially, when the output is high, capacitor C starts charging towards Vcc through RA and RB. As soon as voltage across the capacitor equals 2/3 Vcc, comparator 1 triggers the flip-flop, and the output switches low .Now capacitor C starts discharging through RB and transistor Q1. When the voltage across C equals 1/3 Vcc, comparator 2s output triggers the flip-flop, and output goes high. Then the cycle repeats. The output voltage and capacitor voltage waveforms are as shown. As shown the capacitor is periodically charges and discharges from 2/3 Vcc to 1/3 Vcc respectively. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by Tc= 0.69 (RA + RB)*C Where RA And RB are in Ohms and C in Farads. Similarly, the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the output is low and is given by Td = 0.69 (RB) * C Thus the total period of the output waveform is T = Tc + Td = 0.69 ( RA + 2RB) * C Thus, frequency of oscillations is Fo= 1/T = 1.45/ ( RA + 2RB) * C The Duty cycle is given by % duty cycle = Tc /T * 100
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= RA + RB/ RA + 2 RB * 100. PART B Astable as a square wave oscillator Without reducing Ra = 0 , the astable multivibrator can be used to produce a square wave output simply by connecting diode D across resistor RB, as shown in Fig. The capacitor C charges through RA and diode D to appox. 2./3 VCC and discharges through RB and terminal 7 i.e. transistor until the capacitor voltage equals appox. RA must be a combination of a fixed resistor and pot. So that the pot can be adjusted for the exact square wave.

Circuit Diagram:

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Procedure:
1. Connect the circuit as per the circuit diagram 2. Switch on the dual power supply. 3. Note down the outputs (Ton Toff) from the CRO. 4. Draw the necessary waveforms on the graph sheet

Calculations:

Observation Table: Tc Therotically Practically Conclusion: Td Duty cycle

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Experiment No: 11 Study of NE565 PLL. Aim

1) To study the operation of NE 565 PLL. 2) To use NE 565 as a multiplier

Apparatus:
Function generator, Power supply, CRO, Breadboard, IC-565, Resistors, Capacitors Etc

Theory:
The basic block diagram of PLL is as shown in Figure. The feedback system consist of 1. Phase Comparator/ Detector 2. A low pass filter 3. An error amplifier 4. A Voltage Controlled Oscillator(VCO) The VCO is a free running multivibrator and operates at a set frequency f 0 called free running frequency. This frequency is determined by the external timing capacitor and an external resistor. It can also be shifted to either side by applying a DC control Vc to an appropriate terminal of IC. The frequency deviation is directly proportional to the dc control voltage and hence it is called a Voltage Controlled Oscillator. If an input signal Vs of frequency fs is applied to the PLL, the phase detector compares the phase and frequency of the incoming signal to that of output V0 of the VCO. If the two signals differ in phase and/or frequency, an error signal Ve is generated. The phase detector is basically a multiplier and produces the sum (fs+f0) and difference (fs-f0) components at its output. The high frequency component (fs+f0) is removed by the low pass filter and the difference frequency component is amplified and applied as a control voltage Vc to VCO. The signal Vc shifts the VCO frequency in a direction to reduce the frequency difference between fs and f0.Once this action starts ,we say the signal is in capture range. The VCo continues to change the frequency till its output frequency is exactly the same as input signal frequency. The circuit is said to be locked. Once locked, the output frequency f0 of VCO is exactly identical to fs except for a finite phase difference . This phase difference generates a corrective control voltage Vc to

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shift the VCO frequency from f0 to fs and thereby maintain the lock. Once locked, the PLL tracks the frequency changes of the input signal. Thus the PLL goes through three stages: i) Free Running ii) Capture iii) Locked or Tracking input vs

fs

Phase Detector

v0 f0 v0

Low-pass filter VCO

Amplifier A

vc

Circuit Diagram:

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Procedure:
1. Make the connections of PLL as shown in Figure 1.
2. Measure the free running frequency of VCO at pin 4, with the input signal Vin

set to 0V. Compare it with the calculated value=0.25/RTCT.

3. Now apply the input signal of 1 Vpp square wave at 1kHz to pin 2. Connect one channel of the scope to pin 2 and display this signal on the scope. 4. Gradually decrease the input frequency till the PLL is locked to the input

frequency. This frequency f1 gives lower end of capture range. Go on increasing the input frequency, till the PLL tracks the input signal, say, to a frequency f2. This frequency f2 gives the upper end of lock range. If input
frequency is increased further, the loop will get unlocked. 5. Now gradually decrease the input frequency till the PLL is again locked. This

is the frequency f3,the upper end of capture range. Keep on decreasing the input
frequency until the loop is unlocked. This frequency f4 gives the lower end of lock range. 6. The lock in range fL= (f2-f4). Compare it with the calculated value of 7.8 f0/12. Also the capture range is fc= (f3-f1) compare it with the calculated value of capture range fc=[ fL/(2)(3.6)(103) x C]1/2 7. To use PLL as a multiplier, make the connections as shown in Figure 2. The

circuit uses 4-bit binary counter 7490 used as a divide-by-5 circuit.

8. Set the input signal at 1 Vpp square wave at 500 Hz. 9. Vary the VCO frequency by adjusting the 20k potentiometer till the PLL is locked. Measure the output frequency. It should be 5 times the input frequency. 10. Repeat steps 8,9 for input frequency of 1kHz and 1.5 kHz.

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Calculations:

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Conclusion:

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