ECE 372 1st Midterm

ECE 372 Midterm Exam Fall 2004

In this exam only pencil/pen are allowed. Please write your name on the front page. If you unstaple the papers write your name on the loose papers also. Please do not use additional paper. If you write on the back please indicate where the notes belong to and also indicate on the front that there is additional information on the backside. The approximate point value is shown in brackets [] following the problem number. You have 1 hour to complete the exam. Please note that some questions give significantly more points and are more complex to solve. Organization 0a) [2] What are the first or last names of our 3 TAs?

0b) [2] Can you name 2 people form technical support services (stockroom)?

Introduction 1a) [2] What is the difference between a micro controller and a micro processor?

1b) [2] What is the difference between a common computer system and an embedded computer system?

ECE 372 1st Midterm HC11 CPU / Microcontroller 2 a) [3] List all functional components of our microcontroller (built into microcontroller) 2 b) [5] explain what they are used for 2 c) [2] give suggestion what can be attached to the unit or what other unit is connected to it (do not list more than two) Functional Unit Purpose Connected to

ECE 372 1st Midterm 3 a) [2] Our microcontroller has a register based design. List all registers by completing the list below (do not list configuration registers = $10xx) 3 b) [3] List the purpose of the register (do not list more than 2 purposes) Register Purpose - Condition Code Register (general answer, more details in next question)

- Program Counter

ECE 372 1st Midterm 3 c) [5] The Condition Code Register is based on 8 bits. All bits indicate certain conditions of the microcontroller. List the function of up to 5 of these bits. Bit Function ZERO

3 d) [2] The system you constructed in the laboratory indicates that the program counter points to $4000. Is there a problem with that?

ECE 372 1st Midterm UofA system hardware 4 a) [3] Our microcontroller can be operated in expanded mode but also in bootstrap mode and single chip mode. What is the difference between them?

4 b) The normal operation mode of our micro controller involves a multiplexed bus. A bus is composed of data, address and control lines. - [2] What is a multiplexed bus?

- [4] What control lines do we have and what is their purpose?

- [1] How many data lines and how many address lines do we have?

- [1] How many physical pins are associated with the address and data lines?

ECE 372 1st Midterm 4 c) [4] In the laboratory you built a reset circuit. Why do we not simply use a pushbutton to ground reset if we want to restart the microcontroller (or what is the purpose of those 2 integrated circuits you wired to the reset pin)?

ECE 372 1st Midterm Basic Instruction Cycle You want to execute ABA. 5a) [1] What does this instruction do?

5b) [4] Which part of this process would you consider to be Fetch, Decode and Execute? Think of what happens inside the microcontroller and associate the steps to fetch, decode and execute. Fetch

Decode

Execute?

ECE 372 1st Midterm Data Formats 6) You read a faulty EEPROM and found that sometimes you read a binary value of 0011 0011 and sometimes a value of 1001 0011 at the same memory location. What does this data represent in 6 a) [1] Hexadecimal

6 b) [3] HC11 instruction. You need to state MNEMONIC instruction name Addressing mode Function of the instruction (speculate if you do not know)

6 c) [2] ASCII encoded value (give character as result if possible)

6 d) [1] Binary Coded Decimal value (give result in decimal)

6 e) [3] PC relative offset (give result in signed decimal)

ECE 372 1st Midterm Assembly Programming 7 a) [10] This is a very short program. Please fill in the gaps. Shaded area=nothing can be filled in.

Label MAIN

Instruction LDX

LOOP

INX

ORG DC.W END

*) counts at least one point.

Operand EEPROM Address #$ $8000 $8001 $8002 $8003 #$ $8004 $8005 $8006 LOOP $8007 $8008 $8009 $FFFE $FFFE MAIN $FFFF

Contents $CE $00 $00 $ $8C $00 $03 $25 $ $80

7 b) [2] What is happening in register X in this program? If the program counter points to $8009 what is the contents of register X?

ECE 372 1st Midterm 7c) [10] For each E clock cycle (actually each half cycle) show what values will be on the pins (AD0..7,A8..15) when the previous program is executed. Assume that the reset switch was pressed and show what happens from that point on forward. Fill in comments where appropriate. Only go through the loop one time.

$FFFE Reset Start

$FF80

$FFFF

$FF $8000 LDX

$80CE

$8001

$80..

10

ECE 372 1st Midterm Appendix Page0 ASCII table Assembly Commands for X register

11

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M68HC11ERG/AD

Hexadecimal to ASCII Conversion

Table 2. Hexadecimal to ASCII Conversion
Hex $00 $01 $02 $03 $04 $05 ASCII NUL SOH STX ETX EOT ENQ ACK BEL beep BS back sp HT tab LF linefeed VT FF CR return SO SI DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESCAPE FS GS RS US Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F ASCII SP space ! Hex $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F $50 $51 $52 $53 $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F ASCII @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ under Hex $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A $7B $7C $7D $7E $7F ASCII

` grave
a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ DEL delete

quote
# $ % &

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$06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F

apost.
( ) * + , comma

- dash . period
/ 0 1 2 3 4 5 6 7 8 9 : ; < = > ?

58

M68HC11E Series Programming Reference Guide

MOTOROLA

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8
DIR ACCA INH 0001 1 SBA CBA CMP SBC COM LSR SUBD AND BIT ROR ASR ASL ROL DEC STA EOR ADC ORA ADD INC TST JMP CLR 4 5 6 7 XGDX 8 9 BSR LDS STS A B STOP C D CPX JSR PAGE 4 LDX STX E F LDD STD LDA STA ADDD BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE 2 3 SWI WAI MUL PSHX RTI ABX RTS PULX PSHB PSHA TXS DES PULB PULA BRN INS BRA TSX NEG SUB 2 3 4 5 6 7 8 9 A B C D 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 E REL INH ACCA ACCB IND,X EXT IMM DIR IND,X EXT IMM DIR IND,X ACCB EXT 1111 F 0 1 2 3 4 5 6 7 8 9 A B C D E F BSET BCLR TAB TBA DAA ABA BSET BCLR 1 IND,X

Opcode Maps M68HC11ERG/AD

Page 1

INH

MSB

0000

LSB

0000

TEST

0001

NOP

0010

IDIV

BRSET

0011

EDIV

BRCLR

0100

LSRD

0101

ASLD

0110

TAP

0111

TPA

1000

INX

PAGE 2

1001

DEX

M68HC11E Series Programming Reference Guide

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1010

CLV

PAGE 3

1011

SEV

1100

CLC

1101

SEC

1110

CLI

BRSET

1111

SEI

BRCLR

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Instruction Set Details M68HC11 Instruction Set

ABX
Operation: Description:

Add Accumulator B to Index Register X

IX (IX) + (ACCB)

ABX

Adds the 8-bit unsigned contents of accumulator B to the contents of index register X (IX) considering the possible carry out of the low-order byte of the index register X; places the result in index register X (IX). Accumulator B is not changed. There is no equivalent instruction to add accumulator A to an index register.

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Condition Codes and Boolean Formulae:

None affected Source Form: ABX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

ABX (INH) Cycle 1 2 3 Addr OP OP + 1 FFFF Data 3A R/W 1 1 1

M68HC11 Rev. 6 MOTOROLA Instruction Set Details For More Information On This Product, Go to: www.freescale.com

Reference Manual 493

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Instruction Set Details

BLO
Operation: Description:

Branch if Lower (Same as BCS)

PC (PC) + $0002 + Rel i.e., if (ACCX) < (M) if (C) = 1 (unsigned binary numbers)

BLO

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If the BLO instruction is executed immediately after execution of any of the instructions, CBA, CMP(A, B, or D), CP(X or Y), SBA, SUB(A, B, or D), the branch will occur if and only if the unsigned binary number represented by ACCX was less than the unsigned binary number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C bit in the CCR. See BRA instruction for further details of the execution of the branch.

Condition Codes and Boolean Formulae: Source Form:

None affected BLO (rel)

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 Addr OP OP + 1 FFFF BLO (REL) Data 25 rr R/W 1 1 1

The following table is a summary of all branch instructions.

Test r>m rm r=m rm r<m r>m rm r=m rm r<m Carry Negative Overflow r=0 Always Boolean Z + (N V) = 0 NV=0 Z=1 Z + (N V) = 1 NV=1 C+Z=0 C=0 Z=1 C+Z=1 C=1 C=1 N=1 V=1 Z=1 Mnemonic BGT BGE BEQ BLE BLT BHI BHS/BCC BEQ BLS BLO/BCS BCS BMI BVS BEQ BRA Opcode 2E 2C 27 2F 2D 22 24 27 23 25 25 2B 29 27 20 Complementary rm BLE r<m BLT rm BNE r>m BGT rm BGE rm BLS r<m BLO/BCS rm BNE r>m BHI rm BHS/BCC No Carry BCC Plus BPL No Overflow BVC r0 BNE Never BRN Branch 2F 2D 26 2E 2C 23 25 26 22 24 24 2A 28 26 21 Comment Signed Signed Signed Signed Signed Unsigned Unsigned Unsigned Unsigned Unsigned Simple Simple Simple Simple Unconditional M68HC11 Rev. 6 Instruction Set Details For More Information On This Product, Go to: www.freescale.com MOTOROLA

Reference Manual 512

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Instruction Set Details M68HC11 Instruction Set

BLS
Operation: Description:

Branch if Lower or Same

PC (PC) + $0002 + Rel i.e., if (ACCX) (M) if (C) + (Z) = 1 (unsigned binary numbers)

BLS

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If the BLS instruction is executed immediately after execution of any of the instructions, CBA, CMP(A, B, or D), CP(X or Y), SBA, SUB(A, B, or D), the branch will occur if and only if the unsigned binary number represented by ACCX was less than or equal to the unsigned binary number represented by M. Generally not useful after INC/DEC, LD/ST, TST/CLR/COM because these instructions do not affect the C bit in the CCR. See BRA instruction for further details of the execution of the branch.

Condition Codes and Boolean Formulae: Source Form:

None affected BLS (rel)

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 Addr OP OP + 1 FFFF BLS (REL) Data 23 rr R/W 1 1 1

The following table is a summary of all branch instructions.

Test r>m rm r=m rm r<m r>m rm r=m rm r<m Carry Negative Overflow r=0 Always Boolean Z + (N V) = 0 NV=0 Z=1 Z + (N V) = 1 NV=1 C+Z=0 C=0 Z=1 C+Z=1 C=1 C=1 N=1 V=1 Z=1 Mnemonic BGT BGE BEQ BLE BLT BHI BHS/BCC BEQ BLS BLO/BCS BCS BMI BVS BEQ BRA Opcode 2E 2C 27 2F 2D 22 24 27 23 25 25 2B 29 27 20 Complementary rm BLE r<m BLT rm BNE r>m BGT rm BGE rm BLS r<m BLO/BCS rm BNE r>m BHI rm BHS/BCC No Carry BCC Plus BPL No Overflow BVC r0 BNE Never BRN Branch 2F 2D 26 2E 2C 23 25 26 22 24 24 2A 28 26 21 Comment Signed Signed Signed Signed Signed Unsigned Unsigned Unsigned Unsigned Unsigned Simple Simple Simple Simple Unconditional Reference Manual Instruction Set Details For More Information On This Product, Go to: www.freescale.com 513

M68HC11 Rev. 6 MOTOROLA

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Instruction Set Details

CPX
Operation: Description:

Compare Index Register X

(IX) (M : M + 1)

CPX

Compares the contents of index register X with a 16-bit value at the address specified and sets the condition codes accordingly. The compare is accomplished internally by doing a 16-bit subtract of (M : M + 1) from index register X without modifying either index register X or (M : M + 1).

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Condition Codes and Boolean Formulae:

N R15 Set if MSB of result is set; cleared otherwise. Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if result is $0000; cleared otherwise. V IX15 M15 R15 + IX15 M15 R15 Set if a twos complement overflow resulted from the operation; cleared otherwise. C IX15 M15 + M15 R15 + R15 IX15 Set if the absolute value of the contents of memory is larger than the absolute value of the index register; cleared otherwise. Source Form: CPX (opr)

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 4 5 6 7 CPX (IMM) CPX (DIR) CPX (EXT) CPX (IND,X) CPX (IND,Y) Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W OP 8C 1 OP 9C 1 OP BC 1 OP AC 1 OP CD 1 OP + 1 jj 1 OP + 1 dd 1 OP + 1 hh 1 OP + 1 ff 1 OP + 1 AC 1 OP + 2 kk 1 00dd (00dd) 1 OP + 2 ll 1 FFFF 1 OP + 2 ff 1 FFFF 1 00dd + 1 (00dd + 1) 1 hhll (hhll) 1 X + ff (X + ff) 1 FFFF 1 FFFF 1 hhll + 1 (hhll + 1) 1 X + ff + 1 (X + ff + 1) 1 Y + ff (Y + ff) 1 FFFF 1 FFFF 1 Y + ff + 1 (Y + ff + 1) 1 FFFF 1

Reference Manual 534 Instruction Set Details For More Information On This Product, Go to: www.freescale.com

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Instruction Set Details

DEX
Operation: Description:

Decrement Index Register X

IX (IX) $0001 Subtract one from index register X

DEX

Only the Z bit is set or cleared according to the result of this operation. Condition Codes and Boolean Formulae:

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Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if result is $0000; cleared otherwise. Source Form: DEX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 Addr OP OP + 1 FFFF DEX (INH) Data 09 R/W 1 1 1

Reference Manual 540 Instruction Set Details For More Information On This Product, Go to: www.freescale.com

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Instruction Set Details M68HC11 Instruction Set

INX
Operation: Description:

Increment Index Register X

IX (IX) + $0001 Adds one to index register X

INX

Only the Z bit is set or cleared according to the result of this operation. Condition Codes and Boolean Formulae:

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Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if result is $0000; cleared otherwise. Source Form: INX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 Addr OP OP + 1 FFFF INX (INH) Data 08 R/W 1 1 1

M68HC11 Rev. 6 MOTOROLA Instruction Set Details For More Information On This Product, Go to: www.freescale.com

Reference Manual 547

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Instruction Set Details

LDX
Operation: Description:

Load Index Register X

IXH (M), IXL (M + 1)

LDX

Loads the most significant byte of index register X from the byte of memory at the address specified by the program, and loads the least significant byte of index register X from the next byte of memory at one plus the address specified by the program.

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Condition Codes and Boolean Formulae:

V 0

N R15 Set if MSB of result is set; cleared otherwise. Z R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if result is $0000; cleared otherwise. V 0 Cleared Source Form: LDX (opr)

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 4 5 6 LDX (IMM) LDX (DIR) LDX (EXT) LDX (IND,X) LDX (IND,Y) Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W Addr Data R/W OP CE 1 OP DE 1 OP FE 1 OP EE 1 OP CD 1 OP + 1 jj 1 OP + 1 dd 1 OP + 1 hh 1 OP + 1 ff 1 OP + 1 EE 1 OP + 2 kk 1 00dd (00dd) 1 OP + 2 ll 1 FFFF 1 OP + 2 ff 1 00dd + 1 (00dd + 1) 1 hhll (hhll) 1 X + ff (X + ff) 1 FFFF 1 hhll + 1 (hhll + 1) 1 X + ff + 1 (X + ff + 1) 1 Y + ff (Y + ff) 1 Y + ff + 1 (Y + ff + 1) 1

Reference Manual 554 Instruction Set Details For More Information On This Product, Go to: www.freescale.com

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Instruction Set Details

PULX
Operation: Description:

Pull Index Register X from Stack

SP (SP) + $0001; (IXH) SP (SP) + $0001; (IXL)

PULX

Index register X is pulled from the stack (high-order byte first) beginning at the address contained in the stack pointer plus one. The stack pointer is incremented by two in total. Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers so the subroutine will appear not to have affected these registers.

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Condition Codes and Boolean Formulae:

None affected Source Form: PULX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 4 5 Addr OP OP + 1 SP SP + 1 SP + 2 PULX (INH) Data 38 get IXH get IXL R/W 1 1 1 1 1

Reference Manual 568 Instruction Set Details For More Information On This Product, Go to: www.freescale.com

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Instruction Set Details M68HC11 Instruction Set

PSHX
Operation: Description:

Push Index Register X onto Stack

(IXL), SP (SP) $0001 (IXH), SP (SP) $0001

PSHX

The contents of index register X are pushed onto the stack (low-order byte first) at the address contained in the stack pointer. The stack pointer is then decremented by two. Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Just before returning from the subroutine, corresponding pull instructions are used to restore the saved CPU registers so the subroutine will appear not to have affected these registers.

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Condition Codes and Boolean Formulae:

None affected Source Form: PSHX

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 4 Addr OP OP + 1 SP SP 1 PSHX (INH) Data 3C (IXL) (IXH) R/W 1 1 0 0

M68HC11 Rev. 6 MOTOROLA Instruction Set Details For More Information On This Product, Go to: www.freescale.com

Reference Manual 565

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Instruction Set Details M68HC11 Instruction Set

STX
Operation: Description:

Store Index Register X

M (IXH), M + 1 (IXL)

STX

Stores the most significant byte of index register X in memory at the address specified by the program, and stores the least significant byte of index register X at the next location in memory, at one plus the address specified by the program.

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Condition Codes and Boolean Formulae:

V 0

N IX15 Set if MSB of result is set; cleared otherwise. Z IX15 IX14 IX13 IX12 IX11 IX10 IX9 IX8 IX7 IX6 IX5 IX4 IX3 IX2 IX1 IX0 Set if result is $0000; cleared otherwise. V 0 Cleared Source Form: STX (opr)

Addressing Modes, Machine Code, and Cycle-by-Cycle Execution:

Cycle 1 2 3 4 5 6 Addr OP OP + 1 00dd 00dd + 1 STX (DIR) Data DF dd (IXH) (IXL) R/W 1 1 0 0 Addr OP OP + 1 OP + 2 hhll hhll + 1 STX (EXT) Data FF hh ll (IXH) (IXL) R/W 1 1 1 0 0 STX (IND,X) Addr Data OP EF OP + 1 ff FFFF X + ff (IXH) X + ff + 1 (IXL) R/W 1 1 1 0 0 STX (IND,Y) Addr Data OP CD OP + 1 EF OP + 2 ff FFFF Y + ff (IXH) Y + ff + 1 (IXL) R/W 1 1 1 1 0 0

M68HC11 Rev. 6 MOTOROLA Instruction Set Details For More Information On This Product, Go to: www.freescale.com

Reference Manual 583