SYSTEMATIC YIELD LEARNING BASED ON

EMBEDDED TEST
WHITE PAPER

OCTOBER 2006
 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

TABLE OF CONTENTS

TABLE OF CONTENTS............................................................................................................................ 2

THE GROWING YIELD PROBLEM...................................................................................................... 3

WHAT IS YIELD LEARNING ................................................................................................................. 5

REQUIREMENTS FOR EFFECTIVE YIELD LEARNING................................................................. 6

ROLE OF TEST IN YIELD LEARNING ................................................................................................ 7

A SYSTEMATIC YIELD LEARNING SOLUTION BASED ON EMBEDDED TEST...................... 8

SYSTEMATIC YIELD LEARNING RESULTS ................................................................................... 11

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

THE GROWING YIELD PROBLEM

The profitability and overall viability of the semiconductor IC industry is heavily dependant on achieving
appropriate product yields. As designs sizes increase and geometries shrink, semiconductor yields must
be maintained at acceptable levels. In addition, the time required to achieve the acceptable volume yield
levels (time-to-yield), is also very important. There is wide acceptance that nanometer scale effects have a
significant impact on both nominal yield levels and time-to-yield numbers at the 90nm and the emerging
65nm nodes.

The graph in figure 1, from a study by independent research firm I.B.S. Corp., provides some alarming
trend information regarding the sources of yield limiters. According to the study, factors effecting
nominal yield fall under three categories:

• Defect density based: purely a process related factor. Historically the main factor effecting yield
and addressed through tighter process controls and equipment adjustments.

• Lithography based: both a process and design related factor. This factor is growing in importance
and is being addressed through improved OPC (Optical Proximity Correction) and PSM (Phased
Shift Masking) tools and techniques.

• Performance based: relates to design performance. This is becoming highly sensitive to design-
process interactions.

As outlined in the IBS study, the performance based factor has become the dominant yield limiting
category at the 90nm node. The trend line points to this becoming even more dominant at the 65nm node.
This yield limiter category is the least understood of all and becomes more complex with each new
process technology. Indeed, with tighter processes and increasingly complex designs, subtle defects and
Defect Density Based
100
90
80
Lithography Based
70
Nominal Yield %

60
Performance Based
50
40
30
20
10
0
0.35um 0.25um 0.18um 0.13um 90nm

Source: IBS Corp Feature Dimension

Figure 1: Yield Limiting Factors

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

process-design interactions are resulting in an exploding number of different performance issues.

Core-1
Exact same
cores with
mirror image
Core-2 layouts
Source (IBM)

Figure 2: Design-Process Interaction

Figure 2 (from “Model to Hardware Matching for nm Scale Technologies,” Si2 DFM Workshop 2005)
above demonstrates how the interaction of design and process can affect the performance and yield of
semiconductor parts. Core-1 and Core-2 are mirror images of the same core on the die. However, when
the die was tested, Core-2 was systematically found to be 15% slower than Core-1. This location specific
behavior of intellectual property (IP) on the design can have a dramatic effect on the behavior of the part
and on how it yields. Because of the design specific nature of yield issues, it is no longer sufficient to
simply improve the process technology, or create process specific design rules to address yield. Adaptive
approaches that can analyze and correct design specific yield issues are needed.

If effective solutions are not implemented soon, these yield limiting issues will, according to IBS, “cost
the IC industry billions of dollars and significantly delay the transition to 65nm technology.”

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

WHAT IS YIELD LEARNING

Yield learning is the iterative process – extending from design to volume production - to identify yield
limiters and to gather actionable information to improve time-to-yield and overall yield. Although there
are certain yield considerations during design, the yield learning process, as shown in figure 3, is
currently centered on the manufacturing phase of silicon. The initial step in this process is silicon bring-
up, which begins immediately following the availability of first silicon. The results of the bring-up
exercise are fed back to the product team, constituting the first phase of yield learning. If the first silicon
does not meet the functional requirements, a silicon debug process is initiated. The root cause could be a
design flaw, a process issue related to defectivity or a lithography problem. Once the cause of the failure
has been identified, the learned information is fed back to design, fab and test. A decision is then made on
the best way to address the problem. The manufacturing process may need to be adjusted, or increasingly,
a design modification might require a design re-spin.

Design
Silicon Characterization Volume
FAB Bring-up / Debug & Yield Ramp Production

Test Bring-up Yield

Results Design / Monitoring
Process
Failure Marginalities Excursion
Feedback Analysis Analysis

To Design,
FAB & Test
YIELD LEARNING INFORMATION

Figure 3: Yield Learning Process

Once a part meets its functional requirements, it can be sampled to the market. At this stage product
engineering (PE) starts the characterization process, verifying that the part will meet its performance and
yield requirements across the boundaries of the process parameters and the boundaries of the application
operating conditions. During the subsequent yield ramp phase an increasing number of parts are built and
the critical parameters closely monitored across the range of the allowed manufacturing and operating
conditions. The yield learning information gathered during characterization and yield ramp is fed back to
the design, test and fab functions to determine if any adjustments are required.
Yield learning during volume production consists of collecting sample data from manufactured parts to
make sure that the manufacturing process remains on track. The information gathered is again fed back to
the design, test and fab functions. In the case of a yield excursion, the yields fall below a desired
threshold. A yield excursion analysis exercise is then performed. The results of this analysis are used to
decide on the best course of action to remedy the problem, and to get yields back to the right levels.

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

REQUIREMENTS FOR EFFECTIVE YIELD LEARNING

To meet strict time-to-market and time-to-yield requirements, semiconductor manufacturers must follow a
structured and efficient yield learning process. This process must meet the following requirements:

Requirement 1: Detailed, Accurate and Timely Data

The first requirement for effective yield learning is the availability of comprehensive information.
Detailed data is required from the different stages of silicon manufacturing and test, such as Metrology,
eTest, Sort and Final test. Furthermore, the granularity of the data should comprehend die and sub-die
information as well as equipment and environmental information.

Sub-die data is increasingly important since process variations, which were typically noticed on a lot-by-
lot or wafer-by-wafer basis, are now becoming prevalent on an inter-die and intra-die basis. Additionally,
design-process interactions also require sub-die data to characterize how different design elements are
interacting with the process to limit yields and performance. For failure analysis purposes this sub-die
data must go down to the abstraction level of individual memory and logic elements.

Requirement 2: Effective Analysis and Decision Making

Once the challenge of data comprehensiveness and availability has been solved, the next requirement is to
have mechanisms to effectively analyze this data, such that actionable information is generated. An
effective analysis infrastructure must be:

• Structured such that the data model can comprehend hierarchical attributes ranging from sub-
die level components such as memories, flops and nets to package-level information such as
pins and pin-groups. The data model must also comprehend equipment and environmental
attributes.

• Comprehensive and accurate such that ALL cause-and-effect relationships are evaluated and
done so in a statistically accurate fashion.

• Repeatable such that best known methods can be captured and reused.

• Scalable such that the analysis scales as data volumes grow.

• Able to provide actionable information as an output of analysis, enabling users to,

metaphorically speaking, turn the appropriate knobs.

• Collaborative between team members, such that results of analysis can be shared and discussed
leading to faster decision making.

Requirement 3: Structured Feedback Mechanism to Design, FAB and Test

Finally, the process to feed back yield learning data to the various users of the information, namely the
design, test and fab functions has to be more streamlined, efficient, predictable and well structured. The
information should be actionable, and ultimately govern the actions of each design, manufacturing and
test step.

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

ROLE OF TEST IN YIELD LEARNING

Test plays a crucial role in the yield learning process, first in being the measurement that determines how
well a semiconductor part performs against its specifications, and secondly in collecting measurements
and parameters at different stages of semiconductor manufacturing to help determine the causality of a
yield or performance issue. As discussed earlier, the first requirement for structured yield learning is to
have detailed, timely and accurate data available for analysis and decision making. This data can come
from various stages of semiconductor manufacturing, and increasingly should also come from the internal
Design-for-test (DFT) structures being used to extract internal states and results from within the die.

Manufacturing Stage Test

Test data is collected at various stages of the semiconductor manufacturing process from the wafer, die
and packaged parts. The key stages of test during the manufacturing process are:

eTest: Electrical test performed at the wafer level to measure the electrical characteristics (e.g., sheet
resistance, threshold voltages) at particular locations on the wafer. Test structures used to do eTest are
typically located within the scribe lines of the wafer.

Wafer Acceptance Test (Sort): Test performed at the wafer level typically simultaneously on multiple die
to determine which die to keep and the respective performance bins to put them in.

Final Test: Test performed on the manufactured part after it has been packaged.

Sub-Die Level Test and Diagnostics

According to the 2005 International Technology Roadmap for Semiconductors (ITRS) report, proper DFT
and BIST techniques that isolate defects down to the physical location on the die are essential for yield
improvement. Test and diagnostics data that characterizes the behavior of an IC at the design component
or sub-die level are crucial in an effective yield learning process. Sub-die level data is needed to diagnose
critical problems during silicon bring-up and failure analysis, and to better characterize the design-process
interactions which, as discussed earlier in this paper, are increasingly the root cause of yield problems.

If significant problems are identified during the silicon bring-up stage a failure analysis process is
initiated. During this process diagnostics test data is captured for a select set of failing parts and analyzed
to determine the likely causes of failure. Depending on the diagnostics solution in use, the most likely
culprits can be identified down to the net, gate or memory-bit levels. Further analysis can help identify the
cause of the failure and its correlation to environmental data such as voltage, temperature and frequency.

Design-process interactions have become major contributors to yield loss. The only way to identify how
design components interact with the manufacturing process to affect product yields is to capture detailed
failure and performance information from within each die across multiple wafers and lots. This
information can then be analyzed to understand how various design components limit yields and
performance. For example, sub-die data can reveal the specific logic blocks or memories that are failing
the most often and the conditions to which these failures are correlated. This information is vital in
figuring out the deisgn, fab or test adjustments needed to remedy the problem.

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

Embedded Test Solution Providing the Most Detailed and Accurate Data
The first requirement for effective yield learning is the availability of detailed and accurate data that
profiles the capabilities and performance of the semiconductor part at both the pin and sub-die levels.
LogicVision provides unique capabilities for fast and accurate test and debug of silicon devices based on
two families of products, ETCreate™ and ETAccess™.

ETCreate products consist of embedded IP and corresponding design automation software that provide
embedded test and measurement capabilities for different components of an ASIC/SOC design. The
automation tools create, integrate and verify customized embedded test and measurement design
components, referred to as controllers, based on specific requirements of the design. Controllers can be
created for the test and measurement of virtually all components of an SOC: logic, memories, high speed
I/Os and mixed signal circuits. As depicted in figure 4, controllers are distributed throughout the design
using a scalable hierarchical communication infrastructure based on the IEEE 1149.1 and 1500 standards
making communication simple and efficient. The controllers all operate at full functional speeds and are
capable of very accurate detection of performance related defects as well as highly accurate measurement
of performance parameters. These controllers are “eyes in the die” that not only enable high quality and
low cost manufacturing test, but also provide the capability to detect and diagnose failures deep within the
die.
When a design is signed-off, the LogicVision design automation tools create a LogicVision Database
(LVDB™) which contains extensive information on all the embedded test and measurement capabilities
inserted into the design, as well as information about the design itself.

ETAccess is real-time software

integrated within ATE platforms for At-
At-speed embedded test,
interactive or automated testing, diagnostics and repair for memories
debugging, characterizing and data- At-
At-speed
logging of silicon incorporating embedded test
embedded test and measurement and diagnostics
technology described within an LVDB ETM
ETM for logic
handoff database. The tight coupling of
ETL
ETL
the ETAccess software with the
ETM
ETM High precision
embedded test and measurement ETM
ETM
embedded test
capabilities allows for very accurate WTAP
WTAP
and measurement
and detailed failure identification and
of Serdes I/O
performance characterization. ETL
ETS
ETS
ETL
ETL
ETL

WTAP
WTAP
ETAccess comes in either a fully WTAP
WTAP Hierarchical
interactive version (ETDiagnostics™) TAP
TAP Access
for debug and characterization
activities, or in a batch version
(ETProduction™) for test program Figure 4: Hierarchical Embedded Test Architecture
based datalogging. The results obtained using the ETDiagnostics software can be used directly by either
design engineers to modify the design to correct performance issues or test engineers to modify test limits
and settings. The ETProduction software consists of routines that can be linked into the ATE test

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

program. Function calls are then placed within the test program to invoke the routines as needed to drive
diagnosis and subsequent datalogging of detected failures. This mechanism allows any level of
datalogging, from simple pass/fail to detailed performance measurements and diagnostics, to be
performed seamlessly during production testing. The results of this detailed datalogging can be analyzed
over time to detect and analyze systematic issues effecting performance and yield.

Automated Yield Analysis Based on Embedded Test

Yield Insight™ is a new product from LogicVision that leverages detailed test data, available from
LogicVision’s embedded test products, to provide powerful yield analysis and learning capabilities. Yield
Insight analyzes fab data and sub-die performance and failure data, captured from embedded test
structures across multiple die, wafers and lots to identify systematic yield issues and provide actionable
information to the design, fab and test functions to help remedy these issues.

Yield Insight’s graphical analysis and scripting capabilities (figure 5), allow users to automate and
standardize their analysis processes. Yield Insight provides pre-defined data handling, statistical analysis,
visualization and reporting components that can be used with the scripting capabilities to:
• Create data-mining rules that sift through the various permutations and combinations of test and
foundry data to automatically identify potential issues.
• Automate existing yield analysis procedures and make them predictable, repeatable and standard
across multiple designs, teams and locations.

Yield Insight can analyze yield issues down to the design component level and for example, identify
design blocks that are failing the most often and the factors that these failures are correlated to, or
determine how yields would be affected by changing memory redundancy. Yield Insight offers a highly
effective yield analysis environment that can be used during the entire semiconductor manufacturing and
test cycle, starting from silicon bring-up and characterization, and extending into the yield ramp and
volume manufacturing stages.

YieldInsight

Figure 5: YieldInsight Automated Analysis

Powerful Yield Learning Solution

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

The combination of ETCreate, ETAccess and Yield Insight (figure 6), provides a structured and powerful
yield learning platform that spans both the design and manufacturing phases of semiconductors. The
ETAccess product family, consisting of the ETDiagnostics and ETProduction products, provides the
backend infrastructure for extracting failure and performance information, while Yield Insight provides
the statistical and visualization engine to provide rapid identification of yield limiting issues and perform
root-cause analysis.

This integrated solution has the following unique and industry leading features:

• Powerful failure extraction and analysis capabilities that can only be achieved through
LogicVision’s embedded test technology. Traditional test and DFT methodologies do not have
similar capabilities to detect, much less characterize the new failure mechanisms common in
advanced processes.

• Tight link between failure information and statistical parametric analysis capabilities over
multiple die and wafers.

• Directed failure logging capability for highly efficient yield learning. This capability allows the
test overhead of logging additional data for yield learning purposes to be minimized by only
logging failure data that is crucial to ongoing analysis.

• An automated, rule-based approach to yield learning. Best practices can be encoded as rules that
can drive focused data-mining to automatically identify problematic behaviors and trends down
to the design component level.

ETCreate
ETCreate

Design
Silicon Characterization Volume
FAB Bring-up / Debug & Yield Ramp Production

Test

ETDiagnostics ETProduction
Feedback
To Design, Sub-die Data ETAccess
FAB & Test
YieldInsight
Yield Learning Test / Fab Data
Information

Figure 6: Structured Yield Learning Based on Embedded Test

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

SYSTEMATIC YIELD LEARNING RESULTS

Figure 7 outlines some examples of Yield Insight’s memory failure analysis and visualization capabilities.

Bit-Line Failure Rates

60
60
50 54
48
Fail Rate (%)

40
Memory Failure Rates 42
36
30

Fail Rate (%)

30
20 24
18
10
12
60
0 6
0
BP3
BP1
BP2

50

BL11
BL10

BL12
BL13
BL14
BL15
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BL8
BL9
Fail Rate (%)

40
BP2.M2 Bit Lines
ETM Controller 30

20

10
Condition Sensitivity
Memory Controller 0

Failure Rates
BP2.M1
BP2.M2
BP2.M3
BP2.M4
BP2.M5
BP2.M6

BP2 Memories
FREQUENCY

VDD

Figure 7: Memory Yield Analysis

The chart on the left depicts failures by memory controller; it can be seen that one of the controllers is
seeing more than 50% of the failures. The 2nd chart from the left provides the next level of detail on which
memories are failing under this controller. In this case Memory 2 is exhibiting a large fraction of the
failures. Chart 3 provides an even greater level of detail by showing failures by bit line for Memory 2. In
this case the chart indicates that a majority of the failures can be attributed to one of the bitlines. Finally,
an operating condition sensitivity analysis of the failures shows that there is a strong correlation of the
failures to operating voltage and a significant, but not as strong, correlation to frequency. This clearly
shows that if the yields are not acceptable, Memory 2 has to be looked at to identify fixes to the problem.
This information is fed back to the design group so that they can take it into consideration for new
revisions to the design or for future designs.

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 SYSTEMATIC YIELD LEARNING BASED ON EMBEDDED TEST

Yield Insight
Outlier Memory Analyzed all memories and have found 1 unusual
Warning Report
Repair Rate behavior
Redundancy Analyzed all memories and have found 1 unusual
Utilization behavior

Outlier Memory Redundancy Utilization Warning

100
10
100

75 8
75

% 50 6

Utilization %
% 50
4
25
25
2
0

1RW_512x8
0 0
BP2.M2

BP2.M5
BP2.M1

BP2.M3

BP2.M4

BP2.M6

2 Rows
Non-
Non-Repairable

1 Row
Repairable
Non-
Non-Repairable Good
Repairable
Good Memory Type 1RW_512x8 Redundancy Level
1RW_256x8 Memories

Figure 8: Automated Memory Redundancy Analysis

Figure 8 is an example highlighting the automated analysis capabilities of Yield Insight. The Warning
Report identifies potential problems based on the data mining rules defined by the user. In this example
the Warning Report is identifying an outlier memory, based on repair data. The memory in question has a
substantial non-repairable rate, that is, it could not be repaired for these instances causing a direct yield
hit. Clearly there is something wrong with the memory and also with the level of redundancy built for it.
This feedback will be very important for the design team.
The Warning Report is also identifying a potential redundancy utilization issue. It is identifying that in
the majority of cases one row of redundancy would have sufficed for a particular memory type. Designers
may be able to eliminate the 2nd redundant row to decrease the redundancy overhead and consequently
decrease the chip area.

Conclusion
As discussed in this paper, performance-based yield limiters dominate at 90nm and beyond, while
semiconductor yield is increasingly impacted by design-process interactions. To ensure that the overall
yields, as well as the time-to-yields remain acceptable, a structured approach to yield learning is needed.
LogicVision’s embedded test and yield analysis technologies are uniquely qualified to deliver a powerful,
versatile and automated platform, providing both the detailed information gathering and advanced
analysis capabilities required to support structured yield learning.

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