Introduction+to+ISE 12 2

Basic ISE tutorial
1 Overview of ISE and Synthesis Tools

Overview of ISE
ISE controls all aspects of the design flow. Through the Project Navigator interface, you can access all of the design entry and design implementation tools. You can also access the files and documents associated with your project.
Project Navigator Interface

The Project Navigator Interface is divided into four main subwindows, as seen in Figure 1-1. On the top left is the Sources window which hierarchically displays the elements included in the project. Beneath the Sources window is the Processes window, which displays available processes for the currently selected source. The third window at the bottom of the Project Navigator is the Transcript window which displays status messages, errors, and warnings. The fourth window to the right is a multi-document interface (MDI) window refered to as the Workspace. It enables you to view html reports, ASCII text files, schematics, and simulation waveforms. Each window may be resized, undocked from Project Navigator or moved to a new location within the main Project Navigator window. The default layout can always be restored by selecting View > Restore Default Layout. These windows are discussed in more detail in the following sections.
Figure 1-1: Project Navigator
Based on ISE In-Depth Tutorial (Xilinx) Adapted to a simple, non-clocked example design by Ragnar Johnsen, University of Agder
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Basic ISE tutorial Sources Window

This window consists of three tabs which provide project and file information for the user. Each tab is discussed in further detail below.
Sources Tab
The Sources tab displays the project name, the specified device, and user documents and design source files associated with the selected Design View. The Design View (Sources for) drop-down list at the top of the Sources tab allows you to view only those source files associated with the selected Design View, such as Synthesis/Implementation. Each file in a Design View has an associated icon. The icon indicates the file type (HDL file, schematic, core, or text file, for example). For a complete list of possible source types and their associated icons, see the ISE Help. Select Help > ISE Help Contents, select the Index tab and search for Source file types. If a file contains lower levels of hierarchy, the icon has a + to the left of the name. HDL files have this + to show the entities (VHDL) or modules (Verilog) within the file. You can expand the hierarchy by clicking the +. You can open a file for editing by doubleclicking on the filename.
Snapshots Tab
The Snapshots tab displays all snapshots associated with the project currently open in Project Navigator. A snapshot is a copy of the project including all files in the working directory, and synthesis and simulation sub-directories. A snapshot is stored with the project for which it was taken, and the snapshot can be viewed in the Snapshots tab. You can view the reports, user documents, and source files for all snapshots. All information displayed in the Snapshots tab is read-only. Using snapshots provides an excellent version control system, enabling subteams to do simultaneous development on the same design.
Libraries Tab
The Libraries tab displays all libraries associated with the project open in Project Navigator.
Processes Window
This window contains one default tab called the Processes tab.
Processes Tab
The Processes tab is context sensitive and it changes based upon the source type selected in the Sources tab and the Top-Level Source in your project. From the Processes tab, you can run the functions necessary to define, run and view your design. The Processes tab provides access to the following functions: Add an Existing Source Create New Source View Design Summary Design Utilities User Constraints Synthesis Implement Design Generate Programming File
Transcript Window
The Transcript window contains five default tabs: Console, Errors, Warnings, Tcl Shell, Find in Files. Console Displays errors, warnings, and information messages. Errors are signified by a red (X) next to the message, while warnings have a yellow exclamation mark (!). Warnings Displays only warning messages. Other console messages are filtered out. Errors Displays only error messages. Other console messages are filtered out.
Based on ISE In-Depth Tutorial (Xilinx) Adapted to a simple, non-clocked example design by Ragnar Johnsen, University of Agder 17.08.2010
Basic ISE tutorial

Tcl Shell Is a user interactive console. In addition to displaying errors, warnings and informational messages, the Tcl Shell allows a user to enter Project Navigator specific Tcl commands. For more information on Tcl commands, see the ISE Help. Find in Files Displays the results of the Edit > Find in Files function.
Error Navigation to Source

You can navigate from a synthesis error or warning message in the Transcript window to the location of the error in a source HDL file. To do so, select the error or warning message, right-click the mouse, and select Go to Source from the right-click menu.The HDL source file opens and the cursor moves to the line with the error.
Error Navigation to Answer Record

You can navigate from an error or warning message in the Transcript window to relevant Answer Records on the www.xilinx.com/support website. To navigate to the Answer Record(s), select the error or warning message, rightclick the mouse, and select Go to Answer Record from the right-click menu. The default web browser opens and displays all Answer Records applicable to this message.
Workspace
Design Summary
The Design Summary lists high-level information about your project, including overview information, a device utilization summary, performance data gathered from the Place & Route (PAR) report, constraints information, and summary information from all reports with links to the individual reports.
Text Editor
Source files and other text documents can be opened in a user designated editor. The editor is determined by the setting found by selecting Edit > Preferences, expand ISE General and click Editors. The default editor is the ISE Text Editor. ISE Text Editor enables you to edit source files and user documents. You can access the Language Templates, which is a catalog of ABEL, Verilog, VHDL, Tcl and User Constraints File templates that you can use and modify in your own design.
ISIM Simulator
The iSIM simulator can be used to simulate a test bench and test fixture within the Project Navigator framework. A VHDL test bench or Verilog test fixture is the input to the simulator.
Schematic Editor
The Schematic Editor is integrated in the Project Navigator framework. The Schematic Editor can be used to graphically create and view logical designs.
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2 HDL-Based Design
Getting Started
The following sections describe the basic requirements for running the tutorial based on a simple design example.
Starting the ISE Software

To start ISE: Double-click the ISE Project Navigator icon on your desktop.
Design Description
In this tutorial we will produce a design of a cirquit that turns eight LED-lamps (L0 L7) on and off as a function of three input buttons (btn-west, btn-east, btn-north) and four input slide switches (sw3, sw2, sw1, sw0). The design is split into a lower level module, bin_decode, which is used as a function block in the top level design, LED_control. The lower level module, bin_decode, will be a HDL based design and the top level, LED_control, will be a scematic based design. The functioning of the LED_control is defined as followes: When sw3 = 0 : sw2, sw1, sw0 = 000 sw2, sw1, sw0 = 001 sw2, sw1, sw0 = 010 sw2, sw1, sw0 = 011 sw2, sw1, sw0 = 100 sw2, sw1, sw0 = 101 sw2, sw1, sw0 = 110 sw2, sw1, sw0 = 111 When sw3 = 1 : btn_west = 1 btn_east = 1 btn_north = 1 else
=> L0 => L1, L0 => L2, L1, L0 => L3, L2, L1, L0 => L4, L3, L2, L1, L0 => L5, L4, L3, L2, L1, L0 => L6, L5, L4, L3, L2, L1, L0 => L7, L6, L5, L4, L3, L2, L1, L0
=> L7 => L4, L3 => L0 => all leds off
Inputs
The LED_control design have the physical inputs: sw(3:0) A bus of four slide switches. These inputs are also inputs to the HDL module. btn_west, btn_east, btn_north Push buttons used only in the top-level SCH design.
Outputs
The following are outputs signals for the design. L7, L6, L5, L4, L3, L2, L1, L0 These outputs control the LED lamps of the Spartan-3E demo board.
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Basic ISE tutorial Lower level HDL module

We will start with the design of the HDL module bin_decode. This module is defined by the following logical desription: When sw3=0 The lamps are switched on as follows: sw2, sw1, sw0 = 000 => L0 sw2, sw1, sw0 = 001 => L1, L0 sw2, sw1, sw0 = 010 => L2, L1, L0 sw2, sw1, sw0 = 011 => L3, L2, L1, L0 sw2, sw1, sw0 = 100 => L4, L3, L2, L1, L0 sw2, sw1, sw0 = 101 => L5, L4, L3, L2, L1, L0 sw2, sw1, sw0 = 110 => L6, L5, L4, L3, L2, L1, L0 sw2, sw1, sw0 = 111 => L7, L6, L5, L4, L3, L2, L1, L0 When sw3=1 all lamps are off.
Creating a New Project: Using the New Project Wizard

1. From Project Navigator, select File > New Project. The New Project Wizard appears. 2. Type project name LED_control and choose a project location (on the local PC).
Figure 2-1: New Project Wizard - Create New Project 3. Verify that Schematic is selected as the Top-Level Source Type and click Next. The New Project Wizard Device Properties window appears.
Basic ISE tutorial
Figure 2-2: New Project Wizard - Device Properties 4. Select the following values in the New Project Wizard - Device Properties window:
Product Category: All Family: Spartan3E Device: XC3S500E Package: FG320 Speed: -4 Synthesis Tool: XST (VHDL/Verilog) Simulator: ISim (VHDL/Verilog) Preferred Language: VHDL-200X. This will determine the default language for all processes that generate HDL
files. 5. Click Next andthen Finish,
Creating an HDL-Based Module

With ISE, you can easily create modules from HDL code using the ISE Text Editor. The HDL code is then connected to your top level HDL design through instantiation and is compiled with the rest of the design. You will now author a new HDL module bin_decode using the New Source wizard, specifying the name and ports of the component. The resulting HDL file is then completed in the ISE Text Editor. 6. Click Project/New source select VHDL module and type the filename bin_decode and location for the files and then Next.
Figure 2-3: New Source Wizard - Define Module 7. Give the names for input and outputs, in this example input bus sw (msb=3) and output buss L (msb=7) and then click Next. 8. Click Finish to complete the New Project Wizard.
Basic ISE tutorial

ISE will now create most of the VHDL framework. In the ISE Text Editor, the ports are already declared in the VHDL file, and some of the basic file structure is already in place. The file is colour-coded to enhance readability and help you recognize formal errors. Keywords are displayed in blue, comments in green, and values are black.
----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 11:23:59 06/11/2008 -- Design Name: -- Module Name: bin_decode - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity bin_decode is Port ( sw : in STD_LOGIC_VECTOR (3 downto 0); L : out STD_LOGIC_VECTOR (7 downto 0)); end bin_decode; architecture Behavioral of bin_decode is begin end Behavioral;
Figure 2-4: VHDL File in ISE Text Editor 9. Put the code shown in FIG-2-5 between begin and end Behavioral in the automaticly generated code. with sw select L <= "00000001" when "0000", "00000011" when "0001", "00000111" when "0010", "00001111" when "0011", "00011111" when "0100", "00111111" when "0101", "01111111" when "0110", "11111111" when "0111", "00000000" when others; Figure 2-5: Manually added VHDL code
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10. Save the file by selecting File > Save. 11. Select bin_decode in the Design window. 12. In the Processes window, double-click Check Syntax (eventually expand synthesize-XST to find it). You will use this code in a schematic top level and must create a symbol for the VHDL module so that it can be importet to the drawing. 13. Expand Design Utilities intheprocesseswindowand double-click Create Schematic Symbol. 14. Close the ISE Text Editor.
3 Schematic-Based Design
Overview of Schematic-Based Design
This chapter guides you through a FPGA schematic-based design procedure. After the design is successfully entered in the Schematic Editor, you will perform behavioral simulation, run implementation with the Xilinx Implementation Tools, perform timing simulation and configure and download to the Spartan-3E (XC3S500E) demo board.
Creating a New Source: Using New Source Wizard 1. From the top menu Project, select New Source. The New Source Wizard appears.
Figure 3-1 New Source Wizard 2. Select Schematic , type LED_control as the File Name and save in the same location as the other files. 3. Click Next and Finish 4. The Drawing window appears in the working area.
Manipulating the Window View

The View menu commands enable you to manipulate how the schematic is displayed. Select View > Zoom > In until you can comfortably view the schematic. The schematic window can be undocked from the Project Navigator framework by selecting Window > Float while the schematic is selected in the workspace. After being undocked, the schematic window can be redocked by selecting Window > Dock.
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Basic ISE tutorial Defining the LED_control Schematic

You have now created an empty schematic for LED_control. The next step is to add the components that make up the top-level design.
Adding I/O Markers

I/O markers are used to determine the ports on a macro, or on the top-level schematic. The name of each pin on the symbol must have a corresponding connector in the underlying schematic. Add I/O markers to the LED_control schematic to determine the top-level ports. To add the I/O markers: 1. Select Tools > Create I/O Markers. The Create I/O Markers dialog box opens.
Figure 3-2: Create IO Markes Wizard 2. In the Inputs box, enter sw(3:0) 3. In the Outputs box, enter LED(7:0) 4. Click OK. The I/O markers are added to the schematic sheet. Note: The Create I/O Marker function is available only for an empty schematic sheet. However, I/O markers may be added to nets at any time by selecting Add > I/O Marker and selecting the desired net.
Adding Schematic Components

Components from the device and project libraries for the given project are available from the Symbol Browser, and the component symbol can be placed on the schematic. The available components listed in the Symbol Browser are arranged alphabetically within each library. 1. From the menu bar, select Add > Symbol or click the Add Symbol icon from the Tools toolbar. This opens the Symbol Browser to the left of the schematic editor, displaying the libraries and their corresponding components. Note: The Options window changes depending on which tool you have selected in the Tools toolbar.
Figure 3-3: Add Symbol Icon
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Figure 3-4: Symbol Browser The first component you will place is the bin_decode module. 2. Select the bin_decode module, using one of two ways: Highlight the project directory category from the Symbol Browser dialog box and select the component bin_decode from the symbols list. or Select All Symbols and type bin_decode in the Symbol Name Filter at the bottom of the Symbol Browser window. 3. Move the mouse back into the schematic window. You will notice that the cursor has changed to represent the bin_decode symbol. 4. Move the symbol outline near the top and center of the sheet and click the left mouse button to place the object. Note: You can rotate new or existing components being added to a schematic by selecting Ctrl+R. 5. Use the procedure outlined in steps 1 through 4 above to place the following components on the schematic sheet: Three AND2 Four OR2 One Obuf8 Place the components as shown in Fig 3-5.
Figure 3-5: Component placement

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To exit the Symbols Mode, press the Esc key on the keyboard. For a detailed description of the functionality of Xilinx Library components, right-click on the component and select Object Properties. In the Object Properties window, select Symbol Info. Symbol information is also available in the Libraries Guides, accessible from the collection of software manuals on the web at http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_scm.pdf
Drawing Wires
Use the Add Wire icon in the Tools toolbar to draw wires (also called nets) to connect the components placed in the schematic. Perform the following steps to draw a net between the input symbol sw(3:0) and the input of bin_decode. 1. Select Add > Wire or click the Add Wire icon in the Tools toolbar.
Figure 3-6: Add Wire Icon. 2. Click the output pin of the sw(3:0) and then click the input pin on the bin_decode module. The Schematic Editor draws a net between the two pins. 3. Draw nets to connect the AND and OR components and hanging wires to the rest of the inputs and outputs as shown in Fig 3-7.
Figure 3-7: Lines between Components To specify the shape of the net: 1. Move the mouse in the direction you want to draw the net. 2. Click the mouse to create a 90-degree bend in the wire. To draw a net between an already existing net and a pin, click once on the component pin and once on the existing net. A junction point is drawn on the existing net.
Adding Buses
In the Schematic Editor, a bus is simply a wire that has been given a multi-bit name. To add a bus, use the methodology for adding wires and then add a multi-bit name. Once a bus has been created, you have the option of tapping this bus off to use each signal individually.
Adding Net Names

To add the net names: 1. Select Add > Net Name or click the Add Net Name icon in the Tools toolbar.
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Figure 3-8: Add Net Name Icon 2. Type sw(3) in the Name box. The net name sw(3) is now attached to the cursor. 3. Click the short input line attached to the upper AND2 component. The name is then attached to this net. The net name appears above the net if the name is placed on any point of the net other than an end point. 4. Repeat the procedure for the three long lines (nets) coming into the AND2 components and give them names (starting from top): btn_west, btn_east and btn_north. 5. Repeat with the names L(7:0) (from bin_decode), int_LED(7), int_LED(0), int_LED(4), int_LED(3) (from the OR outputs) and int_LED(7:0) (into obuf8). Draw lines to combine all the short input lines to the AND2 components into one net (sw(3)). You now have the drawing shown on Fig 3-9.
Figure 3-9: More Net Names added Note: Each of the wires with identical names are now electrically connected. In this case, the nets do not need to be physically connected on the schematic to make the logical connection. Bus lines are adressed by the bus name and line number (bus sw consist of lines sw0, sw1, sw2 and sw3).
Adding IO markers to an existing drawing

We will now add IO markes for the inputs btn_west, btn_east and btn_north. 1. Select Add > IO Marker or click the Add IO Marker icon in the Tools toolbar.
Figure 3-10: Add IO Marker Icon 2. Plase the cursor over the end of the line where you will connect the IO Marker and click the left mouse button. The IO Marker will take the name of the net it is connected to.
Correcting Mistakes
If you make a mistake when placing a component or connection, you can easily move or delete the component or line. To move the component, click the component and drag the mouse around the window. Delete a placed component in one of two ways: Click the component and press the Delete key on your keyboard. or
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Right-click the component and select Delete. Delete a line or line segment the same way as a component. In the options field you select to mark and delete the whole branch or just the line segment In the example drawing there is an error that you now must correct. The line segment connecting the upper inputs of the two lower OR2 ports must be removed.
Connecting nets
Nets with different names can not be connected. All nets with the same name are handled as one net. To pass a signal from one net to another you can use the component buf between the nets. In the example we will send the signals from L(6), L(5), L(2) and L(1) to int_LED(6), int_LED(5), int_LED(2) and int_LED(1) and place a buf in each connection. The buf component has no influence on the signal. 1. Place four buf components in the drawing and connect a line stub to the input and output of each buf. 2. name the input line stubs L(6), L(5), L(2), L(1) and the output line stubs int_LED(6), int_LED(5), int_LED(2), int_LED(1) 3. Name the upper input line stubs to the OR2 components L(7), L(0), L(4), L(3). The final drawing will look like Fig 3-11. Note: If the nets appear disconnected, select View > Refresh to refresh the screen.
Figure 3-11: Final drawing
Checking the Schematic

The LED_control schematic is now complete. Verify that the schematic does not contain logical errors by running a design rule check (DRC). To do this, select Tools > Check Schematic. The Console window should report that no errors or warnings are detected. If an error or warning is displayed, fix the reported problem before proceeding. To be sure that the project is updated, click Project > CleanupProjectFiles on the top menu before you do the schematics check.
Saving the Schematic

1. Save the schematic by selecting File > Save, or by clicking the Save icon in the toolbar. 2. Close the time_cnt schematic.
Figure 3-12: Save Icon

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4 Behavioral Simulation
ISE Simulator Setup
ISE Simulator (ISIM) is automatically installed and set up with the ISE 12.2 installer.
Required Files
The behavioral simulation flow requires design files, a test bench file, and Xilinx simulation libraries.
Design Files (VHDL or Schematic)

This chapter assumes that you have completed the design entry tutorial in either HDL-Based Design, or Schematic-Based Design. After you have completed one of these chapters, your design includes the required design files, and is ready for simulation.
Test Bench File

In order to simulate the design, a test bench file is required to provide stimulus to the design.
Design Simulation
Verifying Functionality using Behavioral Simulation
To verify the functionality of the counter module, create a test bench waveform containing input stimuli. Create the test bench waveform as follows: 1. Select the LED_control.sch file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select VHDL Test Bench as the source type, and type LED_control_tb in the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file LED_control. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type, and name. Click Finish. 7. A template of the testbench code now opens in the text editor, se fig 4-1 below.
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Fig 4-1: Test bench code template The template includes the component declaration section (lines 22-37) and the instantiation of the test (lines 40-46). The template also includes a stub for the main test process (tb:PROCESS, lines 48-52). It is our job to turn this simple stub into an actual test sequence that will stimulate and test our design. 8. Replace WAIT (line 51 in fig4-1) with the code shown in fig 4-2, line 52 to 87 and save the file.
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Fig 4-2: Stimulus part of test bench file
Behavioral Simulation Using ISE Simulator (ISim)

Now that you have a test bench in your project, you can perform behavioral simulation on the design using the ISE Simulator. ISE has full integration with the ISIM Simulator. ISE enables ISIM to create the work directory, compile the source files, load the design, and perform simulation based on simulation properties. To select ISIM as your project simulator: 1. In the Sources tab, right-click the device line (xc3s500e-4fg320). 2. Select Properties. 3. In the Project Properties dialog box, select ISim (VHDL/Verilog) in the Simulator field.
Locating the Simulation Processes

To locate the ISIM processes: 1. In the Sources window, select Behavioral Simulation in the Sources field. 2. Select the test bench file (LED_control_tb).
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Figure 4-3: Sources tab Behavioral Simulation 3. Click the + beside ISIM Simulator to expand the process hierarchy and see the picture shown in fig 4-4.
Fig 4-4: Simulation processes Simulate Behavioral Model This process starts the design simulation.
Specifying Simulation Properties

You will perform a behavioral simulation on the LED_control design after you set some process properties for simulation. ISE allows you to set several ISE Simulator properties in addition to the simulation netlist properties. To see the behavioral simulation properties, and to modify the properties for this tutorial: 1. In the Sources tab, select the test bench file (LED_control_tb). 2. Click the + sign next to ISIM Simulator to expand the hierarchy in the Processes tab. 3. Right-click the Simulate Behavioral Model process. 4. Select Process Properties. 5. Change the Simulation Run Time to 2000 ns. 6. Click OK. Note: For a detailed description of each property available in the Process Property dialog box, click Help.
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Figure 4-5: Behavioral Simulation Process Properties
Performing Simulation
Once the process properties have been set, you are ready to run the ISE Simulator. To start the behavioral simulation, double-click Simulate Behavioral Model. ISE Simulator creates the work directory, compiles the source files, loads the design, and performs simulation for the time specified.
Fig 4-6: Simulation results
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5 Design Implementation
Overview of Design Implementation
Design Implementation is the process of translating, mapping, placing, routing, and generating a BIT file for your design. The Design Implementation tools are embedded in the ISE software for easy access and project management. This chapter demonstrates the ISE Implementation flow. In this chapter, you will be passing an input netlist (EDN, NGC) from the front-end tool to the back-end Design Implementation tools, and you will be incorporating placement constraints through a User Constraints File (UCF). You will add timing constraints later through the Floorplan Editor.
Create Timing Constraints

(This point is not relevant in this example design)
Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. The timing is specified by entering constraints that guide the placement and routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which your design must operate inside the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.
Using the Floorplan Editor

Use the Floorplan Editor to add and edit the pin locations and area group constraints defined in the NGD file. Floorplan Editor generates a valid UCF file. The Translate step uses this UCF file, along with the design source netlists, to produce a newer NGD file. The NGD file incorporates the changes made in the design and the UCF file from the previous section. Floorplan Editor edits the UCF file by adding the created placement constraints. 1. Select Sourses for Implementation 2. Select LED_control in the Sources window. 3. Click the + next to User Constraints to expand the process hierarchy in the Processes window. 4. Double-click Floorplan Area / IO / Logic-Post-Synthesis, located under the User Constraints process.
Figure 5-1: Edit Package Pin Placement This process launches Floorplan Editor PlanAhead, but if an UCF file is not already created, the pop up window shown in fig 5-2 will appear. Answer Yes to create a new UCF file.
Fig 5-2 Pop up window
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extracted from the:
PlanAhead User Guide
Figure 5-3: I/O Planner Environment
Placing I/O Ports

The I/O Planner is shown in Figure 5-3. Select Package to see the pins of the Xilinx component (upper right window). Select I/O Ports in the upper left window. (If necessary use the window drop-down menu to open I/O Ports). Right click one port in the I/O Ports window and select I/O Ports Properties toopenthiswindow. NowyouseeallnecessarywindowsfortheI/Oplacingandconfiguration.
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1. In the I/O Ports view, right click one port and select Place I/O Ports Sequentially. 2. Select an I/O Port in the I/O Ports window and write the assigned pin number in the I/O Ports Properties window.
Figure 5-4: I/O Pin Placement 3.Repeat the placement procedure for all I/O pins with reference to the following list:
sw(3) input port connects to FPGA pin N17 sw(2) input port connects to FPGA pin H18 sw(1) input port connects to FPGA pin L14 sw(0) input port connects to FPGA pin L13 btn_west input port connects to FPGA pin D18 btn_east input port connects to FPGA pin H13 btn_north input port connects to FPGA pin V4 LED(7) output port connects to FPGA pin F9 LED(6) output port connects to FPGA pin E9 LED(5) output port connects to FPGA pin D11 LED(4) output port connects to FPGA pin C11 LED(3) output port connects to FPGA pin F11 LED(2) output port connects to FPGA pin E11 LED(1) output port connects to FPGA pin E12 LED(0) output port connects to FPGA pin F12
Configuring I/O Ports

The configuration is done in the I/O Ports Properties window. 4. Click configure as shown in figure 5.5 and select parameters for the input and output pins as described in the following.
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Figure 5-5: I/O Pin Configuration
Slide Switches
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. UCF constraints for the four slide switches, including the I/O pin assignment and the I/O standard used are shown below. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition.
NET NET NET NET "SW<0>" "SW<1>" "SW<2>" "SW<3>" LOC LOC LOC LOC = = = = "L13" "L14" "H18" "N17" | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVTTL LVTTL LVTTL LVTTL | | | | PULLUP PULLUP PULLUP PULLUP ; ; ; ;
Push-Button Switches
Pressing a push button connects the associated FPGA pin to 3.3V, as shown in Figure 5.6.
Figure 5-6: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA Input Pin Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the button is not pressed. The table below shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button.
NET NET NET NET "BTN_EAST" "BTN_NORTH" "BTN_SOUTH" "BTN_WEST" LOC LOC LOC LOC = = = = "H13" "V4" "K17" "D18" | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVTTL LVTTL LVTTL LVTTL | | | | PULLDOWN PULLDOWN PULLDOWN PULLDOWN ; ; ; ;
Discrete LEDs
Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390current limiting resistor. To light an individual LED, drive the associated FPGA control signal High.
NET NET NET NET NET NET NET NET "LED<7>" "LED<6>" "LED<5>" "LED<4>" "LED<3>" "LED<2>" "LED<1>" "LED<0>" LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = "F9" "E9" "D11" "C11" "F11" "E11" "E12" "F12" | | | | | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = = = = = LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL | | | | | | | | SLEW SLEW SLEW SLEW SLEW SLEW SLEW SLEW = = = = = = = = SLOW SLOW SLOW SLOW SLOW SLOW SLOW SLOW | | | | | | | | DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE DRIVE = = = = = = = = 8 8 8 8 8 8 8 8 ; ; ; ; ; ; ; ;
7. Select File Save design. If you are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK. 6. Close PACE.
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Implement Design and Verify Pin Locations

Implement the design and verify that the ports of the LED_control design are routed to the package pins specified in the previous section. First, review the Pinout Report from the previous implementation by doing the following: 1. Implement the design by double-clicking the Implement Design process. 2. Open the Design Summary by double-clicking the View Design Summary process in the Processes window. 3. Select the Pinout Report and select the Signal Name column header to sort the signal names. 4. Verify that signals are now being routed to the correct package pins. 5. Close the Design Summary.
Figure 5-7: Package Pin Locations After Pin Location Constraints
6 Download Design to the hardware

This is the last step in the design verification process. This section provides simple instructions for downloading the LED_control design to the Spartan-3 Starter Kit demo board (to the Xilinx component). 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and demo board (J7). 3. Select Implementation from the drop-down list in the Sources window. 4. Select LED_control in the Sources window. 5. In the Processes window, double-click the Generate Programming File process. 6. Click the + sign to expand Configure Target Device 7. Double-click the Manage Configuration Project (iMPACT) to open the iMPACT Configure Devices dialog.
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Figure 6-1: iMPACT Welcome Dialog window 9. In the Welcome dialog window, doubleclick Boundary-Scan (JTAG). 10. In the boundary scan window: Right click to add device or initialize JTAG chain.
Figure 6-2: iMPACT Boundary scan window 11. Rigth click in the boundary scan window (fig. 6-2), select Initialize Chain. 12. The boundary scan now looks like the one in fig. 6-3. Click yes in the dialog box.
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Figure 6-4: Assign configuration file 13. The left component in the window is now green and a dialog box (Assign New Configuration File) has popped up. Select the file led_control.bit and click open.
Figure 6-5: SPI or BPI PROM dialog box 14. Click NO in the dialog box shown in fig. 5-7 and then Bypass two times. 15. Click OK in the next dialog box and you are finally ready to program the device by double clicking Program in the iMPACT Processes window.
You have completed the ISE introductory Tutorial.

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Basic ISE tutorial

1 Overview of ISE and Synthesis Tools

Project Navigator Interface

Figure 1-1: Project Navigator

Basic ISE tutorial Sources Window

Basic ISE tutorial

Error Navigation to Source

Error Navigation to Answer Record

Basic ISE tutorial

Starting the ISE Software

=> L7 => L4, L3 => L0 => all leds off

Basic ISE tutorial Lower level HDL module

Creating a New Project: Using the New Project Wizard

Basic ISE tutorial

files. 5. Click Next andthen Finish,

Creating an HDL-Based Module

Basic ISE tutorial

Basic ISE tutorial

Manipulating the Window View

Basic ISE tutorial Defining the LED_control Schematic

Adding I/O Markers

Adding Schematic Components

Figure 3-3: Add Symbol Icon

Basic ISE tutorial

Figure 3-5: Component placement

Basic ISE tutorial

Adding Net Names

Basic ISE tutorial

Adding IO markers to an existing drawing

Basic ISE tutorial

Figure 3-11: Final drawing

Checking the Schematic

Saving the Schematic

Figure 3-12: Save Icon

Basic ISE tutorial

Design Files (VHDL or Schematic)

Test Bench File

Basic ISE tutorial

Basic ISE tutorial

Fig 4-2: Stimulus part of test bench file

Behavioral Simulation Using ISE Simulator (ISim)

Locating the Simulation Processes

Basic ISE tutorial

Specifying Simulation Properties

Basic ISE tutorial

Figure 4-5: Behavioral Simulation Process Properties

Fig 4-6: Simulation results

Basic ISE tutorial

Create Timing Constraints

Using the Floorplan Editor

Fig 5-2 Pop up window

Basic ISE tutorial

PlanAhead User Guide

Figure 5-3: I/O Planner Environment

Placing I/O Ports

Basic ISE tutorial

Configuring I/O Ports

Basic ISE tutorial

Figure 5-5: I/O Pin Configuration

Basic ISE tutorial

Implement Design and Verify Pin Locations

Figure 5-7: Package Pin Locations After Pin Location Constraints

6 Download Design to the hardware