VLSI FILE

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 INDEX
S
Name of experiment Date Remarks
.No.
1 Design of gates
a Design of AND gates.
b Design of OR gates.
c Design of XOR gates.
Design of Xor gate using other basic
2
gates.
Design of 2:1 Mux using other basic
3
gates
4 Design of 2 to 4 decoder
Design of half-adder, full adder, half
5
subtractor, full subtractor.
6 Design of 3:8 decoder
7 Design of 8:3 priority encoder.
Design of 4 bit binary to grey code
8
converter
Design of 4 bit binary to BCD converter
9
using sequential statements

Design an 8bit parity generator ( with

10
for loop and generic statements)

Design of all type of flip-flops using (if-

11
then-else) sequential constructs
Design of 8-Bit Shift Register with shift
12 Right, Rhisft Left, Load and
Synchronous reset.
13 Design of ALU

Design of Synchronous 8-Bit universal

14 shift register ( parallel-in, parallel-out)
with 3-state output ( IC 74299)

15 Design
a. Mod 3 Counter
b. Mod 5 Counter
c. Mod 7 Counter
d. Mod 8 Counter
e. Mod 16 counter
Design a decimal up/down counter that
16 counts up from 00 to 99 or down from
99 to 00
WAVEFORM:

RESULT: Designed AND gate, observed RTL view and waveform.

WAVEFORMS:

RESULT: Designed OR gate, observed RTl view and waveform.

WAVEFORMS:

RESULT: Designed XOR gate, observed RTl view and waveform.

WAVEFORM:

RESULT: Designed XOR gate using basic gates, observed RTL view and wave form.
WAVEFORM:

RESULT: Designed 2:1 mux using basic gates, observed RTL view and waveform.
WAVEFORM:

RESULT: Designed 2:4 decoder using basic gates, observed RTL view and waveform.
WAVEFORM:

RESULT: Designed half adder using dataflow modeling.

WAVEFORM:

RESULT: Designed full adder using dataflow modeling.

WAVEFORM:

RESULT: Designed half subtractor using dataflow modeling.

WAVEFORM:

RESULT: Designed full subtractor using dataflow modeling.

WAVEFORM:

RESULT: Designed 3:8 decoder and RTL view and logic.

WAVEFORM:

RESULT: Designed 8:3 priority encoder.

WAVEFORM:

RESULT: Designed 4 biit binary to grey code converter.

WAVEFORM:

RESULT: Designed 4bit binart to BCD converter using sequential statements.

WAVEFORM:

RESULT: Designed 8 Bit parity generator, observedRTL view and waveform.

WAVEFORM:

RESULT : Designed SR flipflop , absered waveforma nd RTL view.

WAVEFORM:

RESULT: Designed Jk flipflop, Observed RTL view and waveform.

WAVEFORM:

RESULT: Designed D flip flop , observed RTL view and waveform.

WAVEFORM:

RESULT: Designed T flip flop , observed RTL view and waveform.

WAVEFORM:

RESULT : Designed 8 bit shift register, observed RTL view and waveform.
 Experiment No. 13

AIM: Design of ALU.

SOFTWARE USED: Version: Xilinx 6.3i.

Simulator: Model Sim 5.4a.

MODELLING STYLE: Behavioral.

RTL VIEW:
 Experiment No. 13

AIM: Design of ALU.

SOFTWARE USED: Version: Xilinx 6.3i.

Simulator: Model Sim 5.4a.

MODELLING STYLE: Behavioral.

VHDL CODE FOR 8bit ALU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit IS
port(a, b : in std_logic_vector(7 downto 0); -- a and b are busses
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
f : out std_logic_vector(7 downto 0));
END alu8bit;

architecture behavioral of alu8bit is

begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
 end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
f <= temp;
end process;
end behavioral;
WAVEFORM:

RESULT: Designed ALU, observed RTL view and waveform.

WAVEFORM:

RESULT: Designed 8 bit universal shift register, observed RTL view and waveform.
WAVEFORM:

RESULT: Designed mod3 counter, observed RTL view and output waveform.
WAVEFORM:

RESULT: Designed mod 5 counter , observed RTL view and output waveform.
WAVEFORM:

RESULT: Designed mod 7 counter, observed RTL view and waveform.

WAVEFORM:

RESULT : Designed mod 8 counter, observed RTL view and output waveform.
WAVEFORM:

RESULT: Designed mod 16 counter, obsereved RTL view and waveform.

WAVEFORM:

RESULT:Designed a decimal up/down counter, observed RTL view and waveform.