IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.

6, JUNE 1998

649

A Comb Filter Design Using Fractional-Sample Delay

Soo-Chang Pei and Chien-Cheng Tseng

II. COMB FILTER DESIGN USING FRACTIONAL SAMPLE DELAY Generally, the input signal of comb lter has the following form:
M k=0

x(n) = s(n) +
Abstract In this paper, a new comb lter design method using fractional sample delay is presented. First, the specication of the comb lter design is transformed into that of fractional delay lter design. Then, conventional nite impulse response (FIR) and allpass lter design techniques are directly applied to design fractional delay lter with transformed specication. Next, we develop a constrained fractional delay lter design approach to improve the performance of the direct design method. Finally, several design examples and an experiment of the power line interference removal in electrocadiogram (ECG) signal are demonstrated to illustrate the effectiveness of this new design approach. Index TermsComb lter, fractional delay lter, harmonic interference removal.

Ak sin(k!0 n + k )
(1)

= s(n) + I (n)

where s(n) is the desired signal and I (n) is harmonic interference with fundamental frequency !0 . In order to extract s(n) from the corrupted signal x(n) undistortedly, the specication of ideal comb lter is given by

Hd (!) =

0; 1;

otherwise.

! = k!0 k = 0; 1; 1 1 1 ; M

(2)

I. INTRODUCTION In many applications of signal processing it is desired to remove harmonic interferences while leaving the broad-band signal unchanged. Examples are in the areas of biomedical engineering, communication and control [1][5]. A typical one is to cancel power line interference in the recording of electrocardiogram (ECG). Usually, this task can be achieved by the comb lter whose desired frequency response is periodic with small stopband notches at 0 Hz to remove baseline wander as well as at 50 Hz and at its higher harmonics to remove power line disturbance [1]. So far, several methods have been developed to design innite impulse response (IIR) and nite impulse response (FIR) comb lters. When the fundamental frequency of harmonic interference is known in advance [1], [5], xed comb lter can be used. However, when fundamental frequency is unknown or time varying, adaptive comb lters are applicable [2][4]. In this paper, we will focus on xed comb lter design problem. Recently, fractional sample delay has become an important device in numerous eld of signal processing, including communication, array processing, speech processing and music technology. An excellent survey of the fractional delay lter design is presented in tutorial paper [6]. Based on this useful and well-documented device, we will establish the relation between the comb lter design problem and the fractional delay lter design problem. As a result, the comprehensive design tools of the fractional delay lter in the literature can be applied to design comb lter directly. The paper is organized as follows. In Section II, we rst transform the specication of the comb lter design into that of fractional delay lter design. Thus, the comb lter design problem becomes a fractional delay lter design one. Then, conventional FIR and allpass lter design techniques for approximation of a fractional digital delay are utilized to design comb lters. Several examples are provided to illustrate the performance of the method. In Section III, we develop a constrained fractional delay lter design approach to improve the performance of the method in Section II. Finally, an experiment of the power line interference removal in ECG signal is shown.
Manuscript received October 20, 1997; revised March 26, 1998. This paper was recommended by Guest Editors F. Maloberti and W. C. Siu. S.-C. Pei is with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. (e-mail: pei@cc.ee.ntu.edu.tw). C.-C. Tseng is with the Department of Electronics Engineering, Hwa Hsia College of Technology and Commerce, Taipei, Taiwan, R.O.C. Publisher Item Identier S 1057-7130(98)03959-7.

The purpose of this paper is to design a lter such that its frequency response approximates Hd (! ) as well as possible. To achieve this purpose, we rst show that the harmonic interference I (n) satises the following property. Dene the fractional sample delay D = 2=!0 which is the period of the harmonic interference I (n), then we have M I (n 0 D) = Ak sin[k!0 (n 0 D) + k ] k=0 M = Ak sin(k!0 n + k 0 2k) k=0 (3) = I (n): This expression tells us that I (n) is equal to its delayed version I (n 0 D). Thus, if the signal x(n) passes through the lter H (z ) = 0D , then its output y(n) is given by 10z

y(n) = x(n) 0 x(n 0 D) = [s(n) + I (n)] 0 [s(n 0 D ) + I (n 0 D )] = s(n) 0 s(n 0 D ):

(4)

Obviously, the harmonic interference has been eliminated in the output y (n). However, y (n) is not equal to s(n), i.e., some distortion is included in the signal y (n). In order to explain this phenomenon, Fig. 1 shows the frequency response of the lter H (z ) = 10z 0D and desired frequency response Hd (! ) dened in (2) with !0 = 0:22 and M = 4. Note that we usually choose M = b=!0 c which denotes the largest integer smaller than or equal to =!0 . It is clear that both responses have the same positions of stopband notches, but they have a large difference in the passband. In order to remove this distortion, a compensation procedure is performed as follows: It is easy to show that the zeros of the lter H (z ) = 1 0 z 0D are given by k = any integer: (5) zk = ej (2=D)k ; For all zeros zk , we introduce the poles pk = ej (2=D)k ; k = any integer:

(6)

to eliminate the distortion in the passband of the frequency response of H (z ) = 1 0 z 0D . The radius of the pole  must satisfy the inequality 0 <  < 1 in order to constrain the poles to be within the unit circle. After performing this compensation, the new transfer function of the comb lter is given by 0D 10z Hc (z ) = : (7) 1 0 D z 0D

10577130/98$10.00 1998 IEEE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998

Fig. 3. The implementation of the IIR comb lter

Hc (z ).

Fig. 1. The frequency response of the comb lter H (z ) = 1 z0D (dashed line) and the desired frequency response Hd (! ) (solid line) with !0 = 0:22 and M = 4.

Fig. 4. The frequency response of the comb lter Example 1.

Hc (z ) designed in

of fractional delay has been presented. Thus, we can directly use these well-documented techniques to design z 0D . Now, two examples are provided to illustrate the performance of the method. One concerns FIR design case, the other is IIR allpass lter case. Example 1FIR Fractional Delay Case: In this example, we use Lagrange interpolation method to design an FIR lter for approximating a given fractional delay z 0D [6]. In this method, the delay z 0D is approximated by

z 0D 
Fig. 2. The frequency response of the comb lter !0 = 0:22 and  = 0:99.

n=0

h(n)z 0n

(8)

Hc (z ) with parameters

where lter coefcients h(n) have the explicit form as

Fig. 2 shows the frequency response of Hc (z ) with parameters !0 = 0:22 and  = 0:99. It is clear that the frequency response of lter Hc (z ) approximates Hd (! ) very well. In fact, Hc (z ) becomes an ideal comb lter when pole radius  approaches unity. Moreover, Fig. 3 shows an implementation of IIR comb lter Hc (z ) in (7). It is clear that the entire implementation only requires a fractional sample delay z 0D . When D is an integer, the delay z 0D is implementable without requiring any design. However, when D is not an integer, we need to design fractional sample delay z 0D . In [6], a comprehensive review of FIR and allpass lter design techniques for approximation

h(n) = N

D0k ; n0k k=0; k6=n

N

n = 0; 1; 1 1 1 ; N:

(9)

When the parameters are chosen as !0 = 0:22 ,  = 0:99, and = 16, the frequency response of Hc (z ) is shown in Fig. 4. It is clear that the comb lter has an excellent approximation at low frequency because the Lagrange interpolation design is a maximally at design at frequency ! = 0. Example 2Allpass Fractional Delay Case: In this example, we use the maximally at group delay allpass lter to approximate a given fractional delay z 0D [6]. In this case, the z 0D is approximated

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998

651

where vectors

h and e ! h h e!
( =[ ( ) = [1

are

(0)

h(1) 1 1 1 h(N )]t 0j! 1 1 1 e0jN! ]t : e

(13)

Since h(n) is real valued, the frequency response H (! ) is conjugate symmetric, i.e.,

H (0!) = H (!)3 : Fd (!)

(14)

For fractional delay lter design, the desired frequency response is chosen as e0jD! . In this paper, the lter coefcients are obtained by minimizing the following least squares error:

J (h) =

where frequency bands R+ = [0;  ] and R0 = [0; 0]. Using the conjugate symmetric property of H (! ) and Fd (! ), the error J ( ) can be rewritten as the quadratic form:

!2(R

[R

jH ! 0 Fd ! j d!
( ) ( )

(15)

where matrix
Fig. 5. The frequency response of the comb lter Example 2.

Hc (z)

designed in

Q, vector p, and scalar c are real and given by Q e ! eH ! d!

=2

J (h) = ht Qh 0 2ht p + c

(16)

!2R !2R !2R

Re[ (

)]

=2

Re[

Fd (!)e3 (!)] d!
)

by

01 0(N 01) 0N N0 1 z0D  aN + a01 1 z + 1 1 1 + a0zN 01) + z 0N : (10) ( 1 + a1 z + 1 1 1 + aN 01 z + aN z If the positive real number D is split into an integer N plus a fractional number d, i.e., D = N + d, the lter coefcients ak is
given by

c =2

jFd ! j d!
(

= 2

:

(17)

N ak = (01)k Ck

N n=0

D0N +n D0N +k+n

The H denotes the Hermitian conjugate transpose operator, and Re(1) stands for the real part of a complex number. In order to make comb lter be exactly zero valued at the harmonic frequencies k!0 , the following constraints are considered in the design procedure:

(11)

H (k!0 ) = e0jDk!

k = 0; 1; 1 1 1 ; M

(18)

N where Ck = N !=k!(N 0 k)! is a binomial coefcient. Fig. 5 shows the frequency response of the comb lter in this design if the parameters are chosen as !0 = 0:22 ,  = 0:99. It is clear that the specication is well satised at low frequency.
III. COMB FILTER DESIGN BASED ON CONSTRAINED FRACTIONAL DELAY FILTER DESIGN Although the design methods in Examples 1 and 2 provide two excellent approximations to the ideal comb lter, the frequency responses at harmonic frequencies k!0 are not exactly zero valued. This result makes the harmonic interference I (n) can not be eliminated clearly by the designed comb lter. In order to remove this drawback, some suitable constraints need to be incorporated in the design of fractional sample delay z 0D . In the following, the cases of FIR lter and allpass lter will be described in details. A. FIR Fractional Delay Filter Design In this subsection, we will design an FIR lter to approximate the fractional sample delay z 0D implemented in Fig. 3. The transfer function of a causal N th-order FIR lter can be represented as N H (z ) = h(n)z 0n :

where M = b=!0 c. After some maniputation, these constraints can = , where real valued matrix be written in vector matrix form and vector are given by

f C f e ; e! e M! gt f ; D! ; 0
= Re[ (0)] Im[ ( cos( Re[ (

Ch f e!

0 )] Im[ (

0 )]

; 1 1 1 ; Re[e(M!0 )];

0 )]

= [1

sin(

DM!0

0)

t )]

sin(

D!0 ); 1 1 1 ; cos(DM!0 );

where Im(1) stands for the imaginary part of a complex number. Based on the above description, the design problem becomes Minimize Subject to

ht Qh 0 ht p Ch f :
2 =

Using the Lagrange multiplier method, the optimal solution of this constrained problem is given by

h Q0 p 0 Q0 Ct CQ0 Ct 0 CQ0 p 0 f :
=

(19)

n=0 The frequency response of the FIR lter is given by H (!) = t (!) = t (!)

he

(12)

Now, we use an example to examine the performance of this design method. Example 3Constrained FIR Filter Case: In this example, the design parameters are chosen as  = 0:9; !0 = 0:22;  = 0:999, and N = 16. The frequency response of the designed comb lter Hc (z ) is shown in Fig. 6. It is clear that the frequency response of the comb lter is exactly zero valued at harmonic frequencies k!0 and almost has unity gain at the remaining frequencies.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998

Fig. 6. The frequency response of the comb lter Example 3.

Hc (z)

designed in

Fig. 7. The frequency response of the comb lter Example 4.

Hc (z)

designed in

B. Allpass Fractional Delay Filter Design It is easy to show that the phase response A (!) of the allpass lter in (10) can be written as

obtain optimal lter coefcients

J (a) =
where matrix

A (!) = 0N! + 2 arctan

k=1 N
1+

ak

sin(k! ) cos(k! )

(20)

Q, vector p and scalar c are given by  Q= b(!)b(!)t d! p= 0

c=
0

jatb(!) + sin[ (!)]j2 d! t t = a Qa 0 2p a + c

0

(25)

k=1

ak

b(!) sin[ (!)] d!

(26)

The purpose of this subsection is to design an allpass lter such that the A (! ) approximates the prescribed phase response 0D! , that is, we want to achieve the following specication:

2 sin[ (! )] d!:

A (!) = 0D!;

! 2 [0; ]:

In order to make comb lter be exactly zero valued at harmonic frequencies k!0 , the following constraints are incorporated in the design: where M = b=!0 c. After some maniputation, these constraints can = , where real valued matrix be written in vector matrix form and vector are given by

(21)

at b(k!0 ) = 0 sin[ (kw0)]; f

k = 1; 2; 1 1 1 ; M

(27)

Substitute (20) into (21), we obtain the expression [7]

N k=1
where  (! ) =

ak

sin[ (! ) + k! ] =

0 sin[ (!)]

C
(22)

Ca f

01=2(0D! + N!). Dene two vectors 111

t sin[ (! ) + N! ]g ;
(23)

C = [b(!0 ); b(2!0 ); 1 1 1 ; b(N!0 )]t f = f0 sin[ (!0)]; 0 sin[ (2!0)]; 1 1 1 ; 0 sin[ (N!0)]gt: a = Q01 p 0 Q01 Ct(CQ01 Ct)01 (CQ01 p 0 f ):

a 2 1 1 1 aN ] t b(!) = fsin[ (!) + !] sin[ (!) + 2!]

then (22) can be rewritten as

a = [a1

Using the Lagrange multiplier method, the optimal solution of this constrained problem is also given by (28)

at b(!) = 0 sin[ (w)]:

(24)

In this paper, we will minimize the following least squares error to

Finally, we use an example to investigate the performance of this design method. Example 4Constrained Allpass Filter Case: In this example, the design parameters are chosen as  = 0:9; !0 = 0:22;  = 0:999, and N = b2=!0 c = 9, The frequency response of Hc (z ) is shown in Fig. 7. It is clear that the frequency response of the designed comb lter is exactly zero valued at harmonic frequencies k!0 and almost has unity gain at the remaining frequencies.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 6, JUNE 1998

653

(a)

(b) Fig. 8. Power line interference removal in ECG signal. (a) Input waveform of the comb lter. (b) Output waveform of the comb lter.

[3] A. Nehorai and B. Porat, Adaptive comb ltering for harmonic signal enhancement, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-24, pp. 11241138, Nov. 1986. [4] Y. K. Jang and J. F. Chicharo, Adaptive IIR comb lter for harmonic signal cancellation, Int. J. Electron., vol. 75, pp. 241250, 1993. [5] S. C. Pei and C. C. Tseng, Elimination of AC interference in electrocardiogram using IIR notch lter with transdient suppression, IEEE Trans. Biomed. Eng., vol. 42, pp. 11281132, Nov. 1995. [6] T. I. Laakso, V. Valimaki, M. Karjalainen, and U. K. Laine, Splitting the unit delay: Tools for fractional delay lter design, IEEE Signal Processing Mag., pp. 3060, Jan. 1996. [7] M. Lang and T. I. Laakso, Simple and robust method for the design of allpass lters using least squares phase error criterion, IEEE Trans. Circuits Syst. II, vol. 41, pp. 4048, Jan. 1994. [8] C. D. McManus, D. Neubert, and E. Crama, Characterization and elimination of AC noise in electrocardiograms: A comparison of digital ltering methods, Comput. Biomed. Res., vol. 26, pp. 4867, 1993.

IV. APPLICATION EXAMPLE A major problem in the recording of ECG is that the measurement signals degraded by the power line interference. One source of interference is electrical eld characterized by noise concentrated at the fundamental frequency 60 Hz. The other source is magnetic eld which is characterized by high harmonic content. The harmonics are due to the nonlinear characteristics of transformer cores in the power supply [8]. Thus, to use comb lter to reduce interference becomes an important subject in ECG measurement. In this example, we utilize the comb lter designed by the method in Example 4 to remove power line interference. The samples used here have 8 bits and the sampling rate is 600 Hz. Fig. 8(a) shows the input waveform that is ECG signal corrupted by harmonic interference with fundamental frequency 60 Hz. The specication of comb lter is chosen as

A Complete Pipelined Parallel CORDIC Architecture for Motion Estimation

Jie Chen and K. J. Ray Liu

Hd (!) =

0; 1;

! = 0:2k k = 0; 1; 1 1 1 ; 5
otherwise.

(29)

Fig. 8(b) shows the waveform of comb lter output with zero initial. From this result, it is obvious the interference has been removed by our comb lter except some transient states appear at the beginning. V. CONCLUSION In this paper, a new comb lter design method using fractional sample delay has been presented. First, the specication of the comb lter design is transformed into that of fractional delay lter design. Then, the FIR and allpass lter design techniques are directly used to design fractional delay lter with transformed specication. Next, we develop a constrained fractional delay lter design approach to improve the performance of the direct design method. Finally, several design examples and an experiment of the power line interference removal in ECG signal are demonstrated to illustrate the effectiveness of this new design approach. REFERENCES
[1] J. A. Van Alste and T. S. Schilder, Removal of based-line wander and power-line interference from the ECG by an efcient FIR lter with reduced number of taps, IEEE Trans. Biomed. Eng., vol. BME-32, pp. 10521060, Dec. 1985. [2] J. D. Wang and H. J. Trussell, Adaptive harmonic noise cancellation with an application to distribution power line communication, IEEE Trans. Commun., vol. 36, pp. 875884, July 1988.

AbstractIn this paper, a novel fully pipelined parallel CORDIC architecture is proposed for motion estimation. Unlike other block matching structures, it estimates motion in the discrete cosine transform (DCT) transform domain instead of the spatial domain. As a result, it achieves high system throughput and low hardware complexity as compared to the conventional motion estimation design in MPEG standards. That makes the proposed architecture very attractive in real-time high-speed video communication. Importantly, the DCT-based nature enables us not only to efciently combine DCT and motion estimation units into a single component but also to replace all multiply-and-add operations in plane rotation by CORDICs to gain further savings in hardware complexity. Furthermore this multiplier-free architecture is regular, modular, and has solely local connection suitable for VLSI implementation. The goal of the paper is to provide a solution for MPEG compatible video codec design on a dedicated single chip.

I. INTRODUCTION Because of the simplicity of the block matching motion estimation (BKM-ME), it has been adopted in MPEG and H.263 standards. However, the computational complexity of BKM-ME is very high, i.e. O(N 4 ) for a N 2 N block, hence high hardware complexity. To reduce the computational complexity, some simplied block search methods (such as logarithmic search, three-step search, etc.) and the corresponding structures have been proposed. Those methods pick several displacement candidates out of all possible displacement values in terms of minimum mean absolute difference values of the reduced number of pixels and still require two or more sequential steps to nd suboptimal estimates. A good review paper about VLSI architectures for video compression can be found in [1]. Besides
Manuscript received October 17, 1997; revised February 27, 1998. This work was supported in part by the Ofce of Naval Research under Grant N00014-93-10566 and by the National Science Foundation under NYI Award MIP9457397. This paper was recommended by Guest Editors F. Maloberti and W. C. Siu. The authors are with the Electrical Engineering Department and Institute for Systems Research, University of Maryland, College Park, MD 20742 USA. Publisher Item Identier S 1057-7130(98)03964-0.

10577130/98$10.00 1998 IEEE