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Final Exam:
When: Wednesday 12/10 12:30-3:30PM Where: 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets of notes & calculator allowed
IC Technology Advancement
The growth of the semiconductor industry has been tied to transistor scaling
Technology Scaling
Investment
Better Performance/Cost
GATE LENGTH (nm)
100
Market Growth
$141B in 2002
10
LOW POWER HIGH PERFORMANCE 1 2000 2005 2010 YEAR 2015 2020
14 nm CMOS Transistors
Hokazono et al., Toshiba Corporation, presented at the International Electron Devices Meeting (San Francisco, CA) Dec. 02
Outline
Introduction Scaling Si Transistors to the Limit Beyond Scaling Conclusion
Thin-Body MOSFETs
Ultra-Thin Body
Gate SOI SiO2 Drain TBOX
Double Gate
TSi
Source
Vg
Drain
Gate Thin-Body Bulk Source Source MOSFET Drain Drain SOI Wafer
TSi
Silicon Substrate
Tox
Common feature: A thin body, such that no conduction path is far from the gate
Ultra-Thin-Body MOSFET
UTB suppresses leakage Thick S/D => low Rseries
Drain Current [A/um]
1.E-02 1.E-04 1.E-06 1.E-08 1.E-10 1.E-12
Subthreshold swing S (units: mV/dec)
Lg = 12 nm Tox = 2 nm
Simulated Id -Vg Vds=1V
200 0.4V -0.5V 100 -0.3V 100 0.25V 0 -0.1V 0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
M. Takamiya et al., Proc. 1997 ISDRS, p. 215 B. Yu et al., Proc. 1997 ISDRS, p. 623
Double-Gate FinFET
Self-aligned gates straddle thin silicon fin Current flows parallel to wafer surface Gate Length = Lg Source Gate 2
Source Drain Gate
FinFET Layout
Layout is similar to that of conventional MOSFET
Scaling Lg to 10 nm
Gate Drain
Source NiSi
DRAIN
Poly-Si
10 nm
SOURCE
technology transferred
Si fin
Bulk-Si MOSFET
FinFET
Y.-K. Choi et al., presented at the 2001 Intl Electron Devices Meeting
10 nm Lg FinFET Id-Vd
10 5 0
Bulk
SG-UTB
DG
Molybdenum-Gated FinFETs
Y.-K. Choi et al., 2002 IEDM
N+
N+
PolySi Mo
D
10 10 10 10 10
-3
-5
-7
Lg (nm): 65
G S D Si
50
40
30
20
10
-9
W Tbody Lgate
-11
10
-13
M o 15 -2 M (N2=5x10 cm ) oN 0.2
SOI D SiO2
Si substrate
G S
SOI
Tilted N implantation (60) used for sidewall gates N implantation lowers gate work function
Outline
Introduction Scaling Si Transistors to the Limit Beyond Scaling Conclusion
IC Technology Challenges
Limits to transistor scaling exist Power is an issue of increasing importance
Portable & wireless-communication products require high speed, low cost & very low power
Heterogeneous Integration
Enhanced functionality/value of IC products
Example: Integrated Micro-ElectroMechanical Devices low-power, wireless building blocks
MEMS antennas, microswitches, filters
MEMS Technology
Surface Micromachining
(cross-sectional view)
structural film sacrificial layer
Mechanical structures can be made using conventional microfabrication techniques Structures are freed by selective removal of sacrificial layer(s)
Si wafer substrate
microfluidics
Electrostatic force is applied by a comb drive electrode to a suspended shuttle. Motion is detected capacitively by a sense comb electrode.
Cross-sectional views
Micromachines
Optical modulators
micro-mirrors for communications, projection displays
foundry CMOS
foundry MEMS
Enter Silicon-Germanium
SiGe can be processed at significantly lower III IV V process temperatures than Si ( 450oC) B C N
- Conventional process tools are used for deposition and patterning
Al Ga Si Ge P As
Resonator on top of Amplifier smaller area --> lower cost reduced interconnect parasitics --> improved performance
Properties are similar to those of Si, and can be tailored by adjusting Ge content The IC industry has significant experience with SiGe
resonator
A. E. Franke et al., Solid-State Sensor and Actuator Workshop Technical Digest, pp. 18-21, June 2000
BLR
Sense Electrode
Outline
Introduction Scaling Si Transistors to the Limit Beyond Scaling Conclusion
Conclusion
Transistor scaling can extend to below 10 nm
advanced structures, materials & processes needed
Device & Design Innovation, Heterogeneous Integration Investment Lower Cost and/or Lower Power Market Growth
100 GATE LENGTH (nm) LOW POWER HIGH PERF.
10
1 2000
2010
2020 YEAR
2030
2040
Alternative approaches to scaling will provide improvements in cost, power and/or performance, to sustain the silicon revolution well beyond 30 yrs