RESET

WATCHDOG
TIMER
IRQ CTRL FLASH CTRL
DEBUG
INTERFACE
CLOCK MUX
and
CALIBRATION
DMA
8051 CPU
CORE
32-MHz
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
HIGH-
SPEED
RC-OSC
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
TIMER 2
(IEEE 802.15.4 MAC TIMER)
32/64/128/256-KB
FLASH
8-KB SRAM
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1
P2_0
P1_3
P0_3
P1_0
P0_0
MODULATOR
DEMODULATOR
AND AGC
RECEIVE TRANSMIT
F
R
E
Q
U
E
N
C
Y
S
Y
N
T
H
E
S
I
Z
E
R
S
Y
N
T
H
RF_P RF_N
B0301-03
RADIO DATA INTERFACE
CSMA/CA STROBE PROCESSOR
RADIO REGISTERS
F
I
F
O

a
n
d

F
R
A
M
E

C
O
N
T
R
O
L
S
F
R

B
u
s
S
F
R

B
u
s
12-BIT -
ADC
D S
AES
ENCRYPTION
AND
DECRYPTION
MEMORY
ARBITER
SFR
IRAM
XRAM
PDATA
32-kHz
RC-OSC
I
/
O

C
O
N
T
R
O
L
L
E
R
DIGITAL
ANALOG
MIXED
POWER MANAGEMENT CONTROLLER
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWNOUT
VDD (2 V3.6 V)
DCOUPL
SLEEP TIMER
USB
USB
PHY
1-KB
FIFO SRAM
DP
DM
CC2531













































































































































































































0 xFFFF
0x8000
0x0000
0x6000
XREG(1KB)
0x63FF
SFR(128B)
0x7080
SRAM_SIZE 1
SRAMSIZE 256
0x7FFF
XBANK
(SELECTABLE32KBFLASHBANK)
8051SFRSPACE
8051DATA SPACE
INFORMATIONPAGE
(2KB)
0x70FF
0x7800
M0097-02
SRAM
(SRAM_SIZEBytes)

















0x0000
0x7FFF
0x8000
0 xFFFF
Bank07
(32KBFLASH)
Common Area/Bank0
(32KBFLASH)
M0098-02
0x0000
0x7FFF
0x8000
0 xFFFF
SRAM
0x8000+SRAM_SIZE 1
0x8000+SRAM_SIZE
Bank07
(Upper24KBFLASH)
Common Area/"Bank7"
(32KBFLASH)
M0099-02












































































































































































































































































































































































































































































































































































































































































































R
F
E
R
R
I
E
D
M
A
I
E
R
F
I
E
I
P
1
_
0
I
P
0
_
0
I
P
1
_
1
I
P
0
_
1
I
P
1
_
2
I
P
0
_
2
I
P
1
_
3
I
P
0
_
3
I
P
1
_
4
I
P
0
_
4
I
P
1
_
5
I
P
0
_
5
E
A
W
D
T
I
E
P
0
I
E
S
T
I
E
P
1
I
E
T
4
I
E
E
N
C
I
E
U
T
X
1
I
E
T
3
I
E
U
R
X
1
I
E
U
T
X
0
I
E
T
2
I
E
U
R
X
0
I
E
P
2
I
E
T
1
I
E
A
D
C
I
E
p o l l i n g s e q u e n c e
W
D
T
I
F
P
0
I
F
S
T
I
F
P
1
I
F
T
4
I
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E
N
C
I
F
_
1
U
T
X
1
I
F
T
3
I
F
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X
1
I
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X
0
I
F
T
2
I
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X
0
I
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P
2
I
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T
1
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R
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I
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0
R
F
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0
R
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R
R
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F
D
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A
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D
C
T
1
P
2
I
N
T
U
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X
0
T
2
U
T
X
0
U
R
X
1
T
3
U
T
X
1
T
4
P
1
I
N
T
S
T
P
0
I
N
T
W
D
T
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N
C
I
T
1
I
T
0
i
r
c
o
n
.
6
R
F
I
R
Q
M
0
R
F
I
R
Q
F
0
T
1
C
C
T
L
{
0
-
4
}
.
I
M
T
I
M
I
F
.
O
V
F
I
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T
1
S
T
A
T
.
O
V
F
I
F
T
1
S
T
A
T
[
4
:
0
]
T
2
I
R
Q
F
T
2
I
R
Q
M
T
I
M
I
F
T
3
O
V
F
IF
T
3
C
H
0
IF
T
3
C
H
1
IF
2 1 0
T
3
C
C
T
L
1
.
I
M
T
3
C
C
T
L
0
.
I
M
T
3
C
T
L
.
O
V
F
I
M
T
I
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I
F
T
4
O
V
F
IF
T
4
C
H
0
IF
T
4
C
H
1
IF
5 4 3
T
4
C
C
T
L
1
.
I
M
T
4
C
C
T
L
0
.
I
M
T
4
C
T
L
.
O
V
F
I
M
P
I
C
T
L
.
P
1
I
C
O
N
0 1
P
1
I
E
N
1
P
I
C
T
L
.
P
0
I
C
O
N
0 1
0
P
1
I
F
G
P
0
I
F
G
P
I
C
T
L
.
P
2
I
C
O
N
0 1
2
P
2
I
F
G
[
4
:
0
]
P
2
I
E
N
[
4
:
0
]
P
1
[
7
:
0
]
P
0
[
7
:
0
]
P
2
[
4
:
0
]
7
:0
R
F
I
R
Q
M
1
R
F
I
R
Q
F
1
7
:0
U
S
B
_
D
P
P
2
I
F
G
.
D
P
I
F
P
2
I
E
N
[
5
]
7
:0
P
0
I
E
N
7
:0
7
:0
7
:0
5
:0
U
S
B
I
I
F
U
S
B
I
I
E
U
S
B
O
I
F
U
S
B
O
I
E
U
S
B
C
I
F
U
S
B
C
I
E
B
0
3
0
2
-
0
2

Debug Clock
Debug Data
Dataissetuponthe
risingedgeofdebugclock.
Dataissampledbythe
receiveronthefalling
edgeofdebugclock.
T0302-01
Debug Clock
Debug Data
Start of Byte End of Byte
Time
T0303-01
Bit5 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0

















Cmd Byte
Time
Data Byte 1 Data Byte 2 Output Byte
Input Input
Debug
Clock
Debug
Data
DataPad
Direction
Startof
Command
Sequence
Padis
Output
TheLevelis
Sampledby the
ExternalDevice
(Asynchronously)
Startto
Change
Direction
End of
Command
Sequence
Output
T0304-01
t
dir_change


















Time
8 Cycles
Debug
Clock
Debug
Data
DataPad
Direction
Cmd Byte Data Byte 1 Data Byte 2 Output Byte
Input Input Output
T0305-01
Startof
Command
Sequence
PadIsOutput,But
Chip IsNotReadyto
Respond Startto
Change
Direction
End of
Command
Sequence
The LevelIs Sampled.
Result=Ready
ChipIsReadyto
ProvideResponse
The LevelIsSampled.
Result=NotReady
t
sample_wait
t
dir_change




































































































































b10 b9 b8 0 0 0 0 1 b7 b6 b5 b4 b3 b2 b1 b0
BURST_WRITECommand Parameter
T0306-01















































































































































































































































































XTAL1
1
1
0
0
32 MHz Crystal Oscillator
32 MHz Crystal Oscillator
XOSC_STB
XTAL2
SLEEPCMD.OSC_PD
SLEEPCMD.OSC_PD
SLEEPCMD.MODE[1:0]
SLEEPCMD.MODE[1:0]
SLEEPCMD.MODE[1:0]
SLEEPCMD.MODE[1:0]
HFRC_STB
16 MHz RC Oscillator
32 kHz RC Oscillator
CLKCONCMD.OSC
CLKCONCMD.OSC32K
SLEEPCMD.OSC32K_CALDIS
SystemClock
32kHzClock
Sleep Timer
Watchdog Timer
B0303-02












































































































































































































































































































































































































































SetupDMAchannel:
SRCADDR=<XDATAlocation>
DESTADDRR=FWDATA
VLEN=0
LEN=<blocksize>
WORDSIZE=byte
TMODE=singlemode
TRIG=FLASH
SRCINC=1byte
DESTINC=0bytes
IRQMASK=yes
M8=0
PRIORITY=high
ArmDMAChannel
Startflashwrite
Setupflashaddress
F0031-01





















































































































































































































































































































































































































































































































































































































































































































































































Initialization
DMA Channel Idle
DMA Channel Armed
DMAARMn=0
Reconfigure?
Yes
Yes
Yes
Yes
Yes
No
DMAARM.DMAARMn
=1?
Load DMA Channel
Configuration
WriteDMA Channel
Configuration
Trigger or
DMAREQ.DMAREQn
=1?
TransferOneByte or
WordWhenChannel
isGranted Access
Modify Source/Destination
Address
Reached Transfer
Count?
Block Transfer
Mode?
SetInterruptFlag
(DMAIRQ.DMAIFn=1;
IfIRQMASK==1then
IRCON.DMAIF=1)
Repetitive Transfer
Mode?
SettingDMAARM.ABORT =1 abortsall
channelswherethe DMAARMn bitisset
simultaneously.
I.e. ,setting DMAARM=0x85aborts
channel1andchannel3.
Yes
No
No
No
No
No
F0033-01



















































T
i
m
e
Byte/Word n 1
Byte/Wordn
Byte/Word1
Byte/Word2
Byte/Word3

LENGTH=n
Byte/Word n 1 Byte/Word n 1 Byte/Word n 1
Byte/Wordn Byte/Wordn
Byte/Wordn+1 Byte/Wordn+1
Byte/Wordn+2
Byte/Word1 Byte/Word1 Byte/Word1
Byte/Word2 Byte/Word2 Byte/Word2
Byte/Word3 Byte/Word3 Byte/Word3

LENGTH=n LENGTH=n LENGTH=n

VLEN=001 VLEN=010 VLEN=011 VLEN=100
M0103-01
















































































































































































































































































































































OVFL OVFL
FFFFh
0000h
T0308-01
































T1CC0
0000h
T0309-02

OVFL OVFL
T1CC0
0000h
T0310-01

FFFFh
T1CC0
T1CC0 T1CC0
T1CCn
T1CCn T1CCn
0000h
0-SetOutputonCompare
1-ClearOutputonCompare
4-ClearOutputonCompare-Up,
Seton0
5-ClearWhen T1CC0,SetWhen T1CCn
6-SetWhen T1CC0,ClearWhen T1CCn
2- ToggleOutputonCompare
3-SetOutputonCompare-Up,
Clearon0
T0311-01




T1CC0
T1CC0 T1CC0 T1CCn T1CCn
0000h
0-SetOutputonCompare
1-ClearOutputonCompare
4-ClearOutputonCompare-Up,
Seton0
5-ClearWhen T1CC0,SetWhen T1CCn
6-SetWhen T1CC0,ClearWhen T1CCn
2- ToggleOutputonCompare
3-SetOutputonCompare-Up,
Clearon0
T0312-01




T1CC0
T1CC0
T1CCn T1CCn
T1CC0
T1CCn
T1CCn T1CCn
0000h
0-SetOutputonCompare
1-ClearOutputonCompare
5-ClearWhen T1CC0,SetWhen T1CCn
6-SetWhen T1CC0,ClearWhen T1CCn
2- ToggleOutputonCompare
3-SetOutputonCompare-Up,
Clearon Compare-Down
T0313-01
4-ClearOutputonCompare-Up,
Seton Compare-Down



















































Timer1
Timer3
Timer3 Ch1Output
Timer1 Ch1Output
Timer 3Ch0Compare
AND
Gate
IROUT
B0358-01
Timer3 Output
Timer1 Output
IROut
S
t
a
r
t
T
i
m
e
r
s
T
i
m
e
r

C
h

C
o
m
p
a
r
e
T
i
m
e
r

C
h

C
o
m
p
a
r
e
T
i
m
e
r

C
h

C
o
m
p
a
r
e
T0440-01



















PIN
Diode
IR
Demod
CC253x
Timer1Ch2
Timer3Ch1
B0359-01




















































































































































































































































































































































































































































































































































































































































































P0_0
P0IFG[0]
STCS.VALID
SLEEPSTA.CLK32K
STCV[23:0]
Read STCV[23:0],
ThenClear
STCS.VALID
Clear P0IFG[0] After
HavingDetecteda
RisingEdgeOn
SLEEPSTA.CLK32K
TimerValueisCaptured
T0412-01

AIN0
.
.
.
VDD/3
TMP_ SENSOR
AIN7
AVDD
AIN6AIN7
Decimation
Filter
ClockGeneration
and
Control
AIN7
Input
Mux
Ref
Mux
Sigma-Delta
Modulator
InternalReferenceVoltage
B0304-01























































































































































































































































15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + +
+ in_bit
M0105-01

BAUD_E
28
(256 BAUD_M) 2
Baud Rate f
2
+
=
































































































































































M O S I



































































































































USB PHY
DP
DM
EP0
EP1
EP2
EP3
EP4
EP5
USB Controller
USB SIE
1KB
SRAM
(FIFOs)
Memory
Arbiter
B0305-01























































































































































































IN FIFO
OUT FIFO
USBMAXI-1
0
b)DoubleBuffering a)SingleBuffering
USBMAX0-1
0
0
0 0
0
USBMAXI-1
USBMAX0-1
USBMAXI-1
USBMAX0-1
INFIFO
(Buffer1)
INFIFO
(Buffer2)
OUT FIFO
(Buffer2)
OUT FIFO
(Buffer1)
M0106-01

( )
TICK
T
C T
O
P
-
=
24
OH
ST(max)
ck
(2 1) P T
T
K
- +

c
f 2405 5(k 11) MHz k 11, 26 = + -






























































I
Q
250kbps 62. 5 ksymbol/s 2 Mchips/s 1Mchips/s
1Mchips/s
Transmitted
Bit-Stream
(LSBFirst)
Modulated
Signal
( toDACs)
Bit-to-
Symbol
Symbol-
to-Chip
O-QPSK
Modulator
B0306-01
t
C
2t
C
I-Phase
Q-Phase
1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
M0107-01





























Bytes: 0 to 20
Frame Payload
n 2
MAC Header (MHR) MAC Payload
Bytes: 1 1 5 + (0 to 20) + n 4
11 + (0 to 20) + n
MAC
Layer
PHY
Layer
M0108-01
2 1
Frame
ControlField
(FCF)
Data
Sequence
Number
Address
Information
FrameCheck
Sequence
(FCS)
MAC Footer
(MFR)
MACProtocol
Data Unit
(MPDU)
PHY ServiceDataUnit
(PSDU)
Preamble
Sequence
Start-of-Frame
Delimiter
(SFD)
Frame
Length
SynchronizationHeader
(SHR)
PHY Header
(PHR)
PHY Protocol DataUnit
(PPDU)






















































































LEN LEN 2Bytes
LEN
AUTOCRC=0
AUTOCRC=1 LEN 2Bytes
FCS
(2Bytes)

(Ignored)

(Ignored)
M0109-01





































Frametransmittedsuccessfully Incompleteornoframetransmission
Writeaframetothe
TXbufferusing:
- TXBUF
- TXBUFCP
-Memoryaccess
- A combinationof
thesemethods
Thiscanbedone
before,after,orin
parallelwiththe TX
strobe.
STXONCCA STXON
SSAMPLECCA
No TXcompletes?
TX_FRM_DONE
TXstarted?
Yes
Nexttime...
Why?
Toretransmitor
transmita
differentframe...
TX_OVERFLOW
TXbufferoverfilled
Errorcondition
Nexttime...
SFLUSHTX SFLUSHTX
Errorcondition
(leftsideoftheflow
diagramshouldbe
ignoredbecausethe
TXbufferiscorrupted.)
TX_UNDERFLOW
SFLUSHTX
Writethenext
frametothe TX
buffer
(before,after,orin
parallelwiththe
TXstrobe)
Writethenew
frametothe TX
buffer
before,after,orin
parallelwiththe
TXstrobe)
Writethenext
frametothe TX
buffer
before,after,orin
parallelwiththe
TXstrobe)
Writethenew
frametothe TX
buffer
(before,after,orin
parallelwiththe
TXstrobe)
Success?
Yes
(SAMPLED_CCA =1)
Yes
(SAMPLED_CCA =1)
No
(SAMPLED_CCA =0)
No
(SAMPLED_CCA =0)
NoCSMA-CA UnslottedCSMA-CA SlottedCSMA-CA
Betweentwotransmissions,therecanbemultipleotheractivitiessuchasframereception,RXFIFOaccess,andacknowledgmenttransmission(usingSACK,
SACKPEND,or AUTOACK),oridleperiods(randombackoffs). Thishasnosideeffectsonthestateofthe TXbuffer.
TheplacementoftheSFLUSHTXstrobeinthediagramshowsthelatestpointintimewherethisstrobecanbeexecuted.Iffewerspecialcasesisdesired,itis
alwayspossibletousetheSFLUSHTXstrobeandthenloadorreload TXBUFwiththenextframetobetransmitted.
Restartfromthe
topofthediagram
Ifanythingis
writtentothe TX
buffer,itis
appendedtothe
currentdata.
Databuffering
Restartfromthe
topofthediagram
Donotwrite
anythingtothe TX
buffer
Restartfromthe
topofthediagram
Restartfromthe
topofthediagram
Restartfromthe
topofthediagram
Restartfromthe
topofthediagram
TXisabortedby
SRXON,
STXONorSRFOFF
T
I
M
E
Toretransmitthe
currentframe...
Totransmita
differentframe...
To(re)transmit
whatis
currentlyin
the TXbuffer...
Totransmita
differentframe...
Toretransmitor
transmita
differentframe...
F0035-01






Preamble SFD MHR FCS LEN
(1) (3) (2)
MAC Payload
Received Frame
M0110-01

0 0 0 0 0 0 0 0 7 A
Preamble
Synchronization Header
SFD
IEEE 802.15.4
CC2520
1 Symbol 1 Byte
M0111-01
2(PREAMBLE_LENGTH+2)ZeroSymbols































+ + +
DataInput
(LSBFirst)
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
B0307-01









































Preamble SFD MHR FCS LEN
(1) (5) (4) (3) (2)
MAC Payload Preamble SFD MHR FCS LEN
Transmitted Acknowledgment Frame Received Frame
M0110-02










































Preamble SFD LEN
Frame Rejected
ReceivedFrame
SFD(AcceptedFrame)
SFD(RejectedFrame)
MPDU(LEN[6:0]Bytes)
T0319-01

















































































SFD LEN Remainder of Received Frame
FCF+SEQ+Destination+
SourcePANID
FilteringisEnabled,FrameRejected
FilteringisEnabled,Frame Accepted
FilteringisDisabled
SFD
Interrupt
SFD
Interrupt
SFD
Interrupt
Frame
Rejected
FIFOP interruptoccursduringthisinterval
(DependingonFIFOPCTRL Value)
FIFOP interruptoccursduringthisinterval
(DependingonFIFOPCTRL Value)
SFDSearch
Resumed
RX_FRM_ACCEPTED
Interrupt
RX_FRM_DONE
Interrupt
RX_FRM_DONE
Interrupt
M0112-01

SFD LEN
- - - - -
When There Is No Source Address:
FCF+SEQ+Destination
SFD
Interrupt
RX_FRM_ACCEPTED
Interrupt
RX_FRM_DONE
Interrupt
Last
Byte
SRC_MATCH_DONE
Interrupt
SFD LEN
- - - - -
When There Is a Source Address:
FCF+SEQ+Destination+
SourcePANID
SFD
Interrupt
RX_FRM_ACCEPTED
Interrupt
RX_FRM_DONE
Interrupt
M0113-01
Last
Byte
Source
Address
SRC_MATCH_FOUNDinterrupt
may occurduringthisinterval
SRC_MATCH_DONEinterrupt
occursduringthis interval




















Length Byte
n
MPDU
MPDU
1
Correlation Value (Unsigned)
0 1 2 3 4 5 6 7
SRCRESINDEX
0 1 2 3 4 5 6 7
RSSI(Signed2sComplement)
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
Data in RXFIFO
AUTOCRC=0
MPDU
2
FCS
2
FCS
1
MPDU
n2
FRMCTRL0Settings
AUTOCRC=1and
APPEND_DATA_MODE=0
AUTOCRC=1and
APPEND_DATA_MODE=1
CRC
OK
CRC
OK
RSSI(Signed2sComplement)
M0114-01

2 1 2
MAC Header (MHR)
Bytes: 1 1 4
Preamble
Sequence
Start-of-Frame
Delimiter
(SFD)
Frame
Length
Frame
ControlField
(FCF)
Data
Sequence
Number
FrameCheck
Sequence
(FCS)
MACFooter
(MFR)
PHY Header
(PHR)
SynchronizationHeader
(SHR)
M0115-01
























Slotted ACK (1)
SFD Unslotted ACK (0) RX Frame SFD ACK Frame Preamble
SFD RX Frame SFD ACK Frame Preamble
Preamble
Preamble
12SymbolPeriods=192 s m
1231SymbolPeriods
nBackoffPeriods=n 320 s m
T0320-01
SFD Preamble
Valid Strobe Interval STROBE_ ERROR STROBE_ ERROR
RXFrame(Rejectedor Accepted)
T0321-01











































































FSMSTAT1:SFD
Received Frame Preamble SFD LEN
FSMSTAT1:FIFO
FSMSTAT1:FIFOP
(Low Threshold)
FSMSTAT1:FIFOP
(High Threshold)
A
c
c
e
p
t
e
d
F
r
a
m
e
R
e
j
e
c
t
e
d
F
r
a
m
e FSMSTAT1:SFD
FSMSTAT1:FIFO
FSMSTAT1:FIFOP
MPDU(LEN[6:0]Bytes)
FirstByte
Received
Frame
Filtering
Complete
Last Byte
Received
T0322-01




































































a
l
l
s
t
a
t
e
s
i
d
l
e
0
r
x
e
n
a
b
l
e
!
=
0
r
x
e
n
a
b
l
e

0
S
R
X
O
N

o
r

S
F
L
U
S
H
R
X
S
F
L
U
S
H
R
X
a
n
y
R
X

s
t
a
t
e
R
X
c
a
l
i
b
r
a
t
i
o
n
2
S
R
F
O
F
F

a
n
d
t
x
_
a
c
t
i
v
e

0
S
T
X
O
N
S
T
X
O
N
C
C
A
a
n
d
c
c
a
=
1
T
X
c
a
l
i
b
r
a
t
i
o
n
3
2 T
i
m
e
o
u
t
1
9
2
s
m
F
r
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c
o
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p
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d

a
n
d
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o

a
c
k

s
c
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d
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d
T
i
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u
t
1
9
2
s
m
T
i
m
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o
u
t
1
9
2
s
m
T
X
3
4

3
8
F
r
a
m
e
s
e
n
t
T
X

u
n
d
e
r
f
l
o
w
5
6
U
n
d
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r
f
l
o
w
T
i
m
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o
u
t

2
s
m
r
x
e
n
a
b
l
e
!
=
0
r
x
e
n
m
a
s
k
!
=
0
T
X

f
i
n
a
l
3
9
T
X
/
R
X

t
r
a
n
s
i
t
4
0
a
l
l
T
X
a
n
d
A
C
K
s
t
a
t
e
s
S
R
F
O
F
F

o
r
S
R
X
O
N
r
x
e
n
a
b
l
e
=
0
T
X

s
h
u
t
d
o
w
n
2
6
,

5
7
A
C
K
4
9

5
4
S
F
D

w
a
i
t
3

6
R
X
7

1
3
T
i
m
e
o
u
t

1
9
0
s
m
R
X
F
I
F
O
r
e
s
e
t
1
6
F
r
a
m
e
n
o
t
f
o
r
m
e
S
F
D
d
e
t
e
c
t
e
d
R
X
/
R
X

w
a
i
t
1
4
T
i
m
e
o
u
t

1
9
2
s
o
r
r
x
2
r
x
_
t
i
m
e
_
o
f
f

1
m
O
v
e
r
f
l
o
w
S
l
o
t
t
e
d
A
C
K
R
X

o
v
e
r
f
l
o
w
1
7
A
C
K

d
e
l
a
y
5
5
U
n
s
l
o
t
t
e
d
A
C
K
A
C
K
c
a
l
i
b
r
a
t
i
o
n
4
8
T
i
m
e
o
u
t

x
s
(
d
e
p
e
n
d
i
n
g

o
n

l
e
n
g
t
h

b
y
t
e
o
f

t
h
e

r
e
c
e
i
v
e
d

f
r
a
m
e
)
m
F
0
0
3
6
-
0
1










































3 2 1 0 1 2 3
80
70
60
50
40
30
20
10
0
P
S
D

P
o
w
e
r

S
p
e
c
t
r
a
l

D
e
n
s
i
t
y

P
o
w
e
r
/
B
i
n
f Frequency rad
G001
0 50 100 150 200 250
600
605
610
615
620
625
630
645
650
C
o
u
n
t
Bin Number
G002
640
635































































































































Yes
No
Writeinstructionto
RFST
Allinstructions
written?
SetupCSPT, CSPX,
CSPY, CSPZ,and
CSPCTRL registers
Start executionby
writingISSTART to
RFST
SSTOP instruction,
endofprogram,or
writingISTOP to
RFST stopsprogram
F0037-01







































































































































































































































































































































































































































































































































































































































LNA
LNA_ CURRENT_OE
1
0
rf_input
read_data
write_data
AGC
Module
AGCCTRL2
Register
B0308-01