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Berkeley Wireless Research Center A Bandpass Analog-to-Digital Converter Using Voltage-Controlled Oscillators
Berkeley Wireless Research Center
A Bandpass Analog-to-Digital Converter
Using Voltage-Controlled Oscillators

Young-Gyu Yoon & SeongHwan Cho

Communication Circuits and Systems Group, KAIST http://ccs.kaist.ac.kr

Y.G. Yoon et al., “Time-based Bandpass ADC using Time-Interleaved Voltage-Controlled Oscillators”, IEEE Trans. On Circuits & Systems I, Dec., 2008.

Oscillators”, IEEE Trans. On Circuits & Systems I, Dec., 2008. 2009-02-13 CCS Group @ KAIST 11
Oscillators”, IEEE Trans. On Circuits & Systems I, Dec., 2008. 2009-02-13 CCS Group @ KAIST 11
Oscillators”, IEEE Trans. On Circuits & Systems I, Dec., 2008. 2009-02-13 CCS Group @ KAIST 11
Motivation WLAN ZigBee Bluetooth RFID USN UWB DECT GPS W-CDMA GSM • Next-generation receivers require

Motivation

WLAN ZigBee Bluetooth RFID USN UWB DECT GPS W-CDMA GSM
WLAN
ZigBee
Bluetooth
RFID
USN
UWB
DECT
GPS
W-CDMA
GSM

Next-generation receivers require multi-mode multi-standard communication.

Programmable and digital-intensive receiver is necessary.

communication. • Programmable and digital-intensive receiver is necessary. 2009-02-13 CCS Group @ KAIST 2
communication. • Programmable and digital-intensive receiver is necessary. 2009-02-13 CCS Group @ KAIST 2
Receiver Architectures A/D conversion at IF LNA IF Amp ADC DBB LO  Large dynamic

Receiver Architectures

Receiver Architectures A/D conversion at IF LNA IF Amp ADC DBB LO  Large dynamic range

A/D conversion at IF

LNA IF Amp ADC DBB
LNA
IF Amp
ADC
DBB

LO

Large dynamic range Many analog components Low programmability

A/D conversion at RF

LNA ADC DBB
LNA
ADC
DBB

Highly digital High programmability Dynamic range is limited (ADC) High power consumption (ADC)

Low-power high-performance ADC is necessary.

High power consumption ( ∵ ADC) • Low-power high-performance ADC is necessary. 2009-02-13 CCS Group @
High power consumption ( ∵ ADC) • Low-power high-performance ADC is necessary. 2009-02-13 CCS Group @
High power consumption ( ∵ ADC) • Low-power high-performance ADC is necessary. 2009-02-13 CCS Group @

Bandpass ADCs for Direct RF Sampling

Bandpass ADCs for Direct RF Sampling f Nyquist ADC f Bandpass ADC • Bandpass ADC can
f
f

Nyquist ADC

Bandpass ADCs for Direct RF Sampling f Nyquist ADC f Bandpass ADC • Bandpass ADC can
f
f

Bandpass ADC

ADCs for Direct RF Sampling f Nyquist ADC f Bandpass ADC • Bandpass ADC can be

Bandpass ADC can be more efficient than a Nyquist ADC for a narrow-band communication receiver.

ADC can be more efficient than a Nyquist ADC for a narrow-band communication receiver. 2009-02-13 CCS
ADC can be more efficient than a Nyquist ADC for a narrow-band communication receiver. 2009-02-13 CCS
Conventional RF bandpass ADC Analog Input CLK + H(s) − DAC Digital Output • Mostly

Conventional RF bandpass ADC

Analog

Input

CLK

+ H(s) − DAC
+ H(s)
DAC

Digital

Output

• Mostly implemented in expensive processes due to high speed requirement

– SiGe BiCMOS, InP HBT, etc

due to high speed requirement – SiGe BiCMOS, InP HBT, etc • High power consumption due

• High power consumption due to high-speed analog components (loop filter & DAC)

Filter is not programmable.due to high-speed analog components (loop filter & DAC) 2 0 0 9 - 0 2

components (loop filter & DAC) Filter is not programmable. 2 0 0 9 - 0 2
components (loop filter & DAC) Filter is not programmable. 2 0 0 9 - 0 2
High Performance BP ΣΔ ADCs • A Low-Noise 40Gs/s Continuous-Time Bandpass ΣΔ ADC Centered at

High Performance BP ΣΔ ADCs

High Performance BP ΣΔ ADCs • A Low-Noise 40Gs/s Continuous-Time Bandpass ΣΔ ADC Centered at 2GHz

• A Low-Noise 40Gs/s Continuous-Time Bandpass ΣΔ ADC Centered at 2GHz for Direct Sampling Receivers

– Continuous-time bandpass ΣΔ architecture using Gm-LC

– LNA included in main path

ΣΔ architecture using Gm-LC – LNA included in main path Center frequency 2GHz Sampling frequency 40GHz

Center frequency

2GHz

Sampling frequency

40GHz

SNR @ 10MHz BW

63dB (0dBm input)

Power consumption

1.6W

Supply Voltage

2.5V

Technology

0.13µm SiGe BiCMOS

Active area

2.40mm 2

Chalvatzis et al., “A Low-Noise 40-GS/s Continuous-Time Bandpass ΣΔ ADC Centered at 2GHz for Direct Sampling Receivers,” IEEE JSSC May, 2007.

ΣΔ ADC Centered at 2GHz for Direct Sampling Receivers,” IEEE JSSC May, 2007. 2009-02-13 CCS Group
ΣΔ ADC Centered at 2GHz for Direct Sampling Receivers,” IEEE JSSC May, 2007. 2009-02-13 CCS Group
ΣΔ ADC Centered at 2GHz for Direct Sampling Receivers,” IEEE JSSC May, 2007. 2009-02-13 CCS Group
High Performance BP ΣΔ ADCs • Continuous-time bandpass ΣΔ architecture – Passive L & C

High Performance BP ΣΔ ADCs

High Performance BP ΣΔ ADCs • Continuous-time bandpass ΣΔ architecture – Passive L & C for

• Continuous-time bandpass ΣΔ architecture

– Passive L & C for band-pass filtering

architecture – Passive L & C for band-pass filtering Center frequency 950MHz Sampling frequency 3.8GHz

Center frequency

950MHz

Sampling frequency

3.8GHz

SNR @ 1MHz BW

 

59dB

Power consumption

75mW

Supply Voltage

±

1.25V

Technology

0.25µm SiGe BiCMOS

Active area

1.08mm 2

Thandri and Martinez, "A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology," IEEE JSSC, Feb. 2007

MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology," IEEE JSSC, Feb. 2007 2009-02-13 CCS Group
MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology," IEEE JSSC, Feb. 2007 2009-02-13 CCS Group
MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology," IEEE JSSC, Feb. 2007 2009-02-13 CCS Group
Previous Works on Direct RF Sampling Ref f carrier f sample BW SNDR Power Supply

Previous Works on Direct RF Sampling

Previous Works on Direct RF Sampling Ref f carrier f sample BW SNDR Power Supply Process

Ref

f

carrier

f

sample

BW

SNDR

Power

Supply

Process

Mscl

JSSC

1.8~2.0GHz

 

40GHz

60MHz

55dB

1.6W

V

DD =2.5V

0.13um SiGe

4 th ∆Σ 2.40mm 2

2007

 

V

SS =0V

BiCMOS

JSSC

950MHz

3.8GHz

1MHz

59dB

75mW

V

DD =1.25V

0.25um SiGe

4 th ∆Σ 1.08mm 2

2007

V

SS =-1.25V

BiCMOS

TCAS-II

 

1GHz

 

4GHz

20MHz

37dB

450mW

V

DD =5V

0.5um SiGe

4 th ∆Σ 1.36mm 2

2000

   

V

SS =0V

HBT

CICC

1.3GHz

4.3GHz

200MHz

39dB

6.2W

V

DD =5V

InP HBT

4 th ∆Σ 5.28mm 2

2003

V

SS =-5V

Goal

800MHz ~

6.4GHz

20MHz

55dB

~ 15mW

V

DD =1V

65nm

Time-

based

2.4GHz

V

SS =0V

CMOS

ADC

Conventional bandpass ΔΣ ADCs rely on fast devices (SiGe BiCMOS) and none have yet developed a CMOS RF sampling ADC.

Analog circuits are extensively used in conventional bandpass ΔΣ ADCs Not compatible with future nanoscale CMOS devices.

conventional bandpass ΔΣ ADCs  Not compatible with future nanoscale CMOS devices. 2009-02-13 CCS Group @

2009-02-13

conventional bandpass ΔΣ ADCs  Not compatible with future nanoscale CMOS devices. 2009-02-13 CCS Group @

CCS Group @ KAIST

conventional bandpass ΔΣ ADCs  Not compatible with future nanoscale CMOS devices. 2009-02-13 CCS Group @

88

• Motivation Contents • Introduction to the VCO-based ADC – Time-based ADC – Operation principle

Motivation

• Motivation Contents • Introduction to the VCO-based ADC – Time-based ADC – Operation principle •

Contents

Introduction to the VCO-based ADC

Time-based ADC

Operation principle

VCO-based ADC – Time-based ADC – Operation principle • Proposed VCO-based bandpass ADC • Implementation •

Proposed VCO-based bandpass ADC

Operation principle • Proposed VCO-based bandpass ADC • Implementation • Measurement results • Conclusion

Implementation

• Proposed VCO-based bandpass ADC • Implementation • Measurement results • Conclusion 2 0 0 9

Measurement results

bandpass ADC • Implementation • Measurement results • Conclusion 2 0 0 9 - 0 2

Conclusion

ADC • Implementation • Measurement results • Conclusion 2 0 0 9 - 0 2 -
ADC • Implementation • Measurement results • Conclusion 2 0 0 9 - 0 2 -
Time-based Signal Processing Voltage domain VDD VDD noise GND GND Lower SNR Conventional ADC Time

Time-based Signal Processing

Voltage domain

VDD VDD noise GND GND
VDD
VDD
noise
GND
GND

Lower SNR

Conventional ADC

Time domain

VDD VDD GND GND Faster transition
VDD
VDD
GND
GND
Faster transition

Time-based ADC

domain VDD VDD GND GND Faster transition Time-based ADC In a deep-submicron CMOS process, time-domain resolution

In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals.

[ Staszewski et al., “All digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS ,” IEEE JSSC, 2004 ]

 Time-based ADC is a promising candidate for direct RF sampling bandpass ADCs.
 Time-based ADC is a promising candidate for direct RF sampling
bandpass ADCs.
]  Time-based ADC is a promising candidate for direct RF sampling bandpass ADCs. 2009-02-13 CCS
]  Time-based ADC is a promising candidate for direct RF sampling bandpass ADCs. 2009-02-13 CCS

2009-02-13

CCS Group @ KAIST

]  Time-based ADC is a promising candidate for direct RF sampling bandpass ADCs. 2009-02-13 CCS

1010

Operation Principle clk CLKs CLKs CLKs Analog Analog Digital Code Digital VCO Counter input Input
Operation Principle
clk
CLKs
CLKs
CLKs
Analog
Analog
Digital Code
Digital
VCO
Counter
input
Input
Generator
Output
• VCO : Voltage-to-phase conversion
Time
VCO
output
voltage
Time
• Counter: Phase quantization
VCO
output
- Counting the edges of VCO output
phase
ex) rising edge detection
 LSB =
ex) rising/falling edge detection  LSB = π
• Digital code generator: LUT
Time
Rising edge
Rising edge
Counter out
Counter out
- Mapping circuit
= 3
= 5
edge Counter out Counter out - Mapping circuit = 3 = 5 VCO Voltage to phase

VCO

Voltage to

phase

domain

• H. Burke, “A survey of analog-to-digital converters”, Proceedings of the IRE, 1954.

• A. Iwata et al., “The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage-Controlled Oscillator as a Multibit Quantizer,” IEEE Trans. Circuits Syst. II,, July 1999.

• A. Younis, H. Marwan, and R. Moises, “Method and system for VCO-based analog-to-digital conversion (ADC),” US pat. # : 6,809,676 , 2004.

• E. Alon, et al, “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise, IEEE Symp. on VLSI Circuits, 2004

Measurement of On-Chip Power Supply Noise, IEEE Symp. on VLSI Circuits , 2004 2009-02-13 CCS Group
Measurement of On-Chip Power Supply Noise, IEEE Symp. on VLSI Circuits , 2004 2009-02-13 CCS Group
Measurement of On-Chip Power Supply Noise, IEEE Symp. on VLSI Circuits , 2004 2009-02-13 CCS Group
Resolution of VCO-based ADC
Resolution of VCO-based ADC

V max

V min

Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)
Resolution of VCO-based ADC V max V min 1LSB V max -V min 1LSB =8 Resolution(N=3)

1LSB

V

max

-V

min

1LSB

=8

Resolution(N=3)

Resolution= log

= log

2

2

V

V

MIN

MAX

1

LSB () V

V

FS

1

LSB () V

Sampling period (Conversion Window) Number of rising edges f 9 max 1LSB(2π) f 2 min
Sampling period
(Conversion Window)
Number of
rising edges
f
9
max
1LSB(2π)
f
2
min
1LSB(2π)
t
Resolution = log
∆φ − ∆φ 
max
min
2
1
LSB () rad
2( π K
V
VT )
VCO
max
min
period
= log
2
1
LSB () rad
2 π
f tune
= log
2  
1
LSB () rad
f sample
  

For high resolution ADC, a wide tuning range VCO is necessary.

f sample    For high resolution ADC, a wide tuning range VCO is necessary.
f sample    For high resolution ADC, a wide tuning range VCO is necessary.
f sample    For high resolution ADC, a wide tuning range VCO is necessary.
Operation Principles Revisit Sampling Clock n-1 n n+1 Digital x[n] input output Sampling S/H VCO

Operation Principles Revisit

Sampling Clock

n-1 n n+1 Digital x[n] input output Sampling S/H VCO Counter clock Y[n] Sampled pn
n-1
n
n+1
Digital
x[n]
input
output
Sampling
S/H
VCO
Counter
clock
Y[n]
Sampled
pn
[]
=
K
xn
[]
Input
VCO
x[n]
=⋅
2
π
yn
[]
p
[]
n
+
en
[]
i
VCO output
=
2
π ⋅
yn
[
]
− −+ en
en
[
1]
[
]
e[n-1]
p
i [n]
e[n]
p
i [n+1]
Counter
Ouput
4
3
yn
[
]
=
1 K
{
xn
[
]
en
[
]
+− en
[
1]
}
y[n]
VCO
2
π
e[n-1]
1
10π
{
1
Yz (
)
=
K
Xz (
)
− (1 −
z
)
Ez (
)
}
VCO
VCO
2
π
e[n]
phase shift
p[n]
p[n]
1
p
i [n]
NTF
=
( z
1)
0
time

Inherent 1-st order noise shaping property.

A. Iwata et al. “The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer," IEEE Trans. Circuits Syst. II, 1999.

oscillator as a multibit quantizer," IEEE Trans. Circuits Syst. II, 1999. 2009-02-13 CCS Group @ KAIST
oscillator as a multibit quantizer," IEEE Trans. Circuits Syst. II, 1999. 2009-02-13 CCS Group @ KAIST
SNR of VCO-based ADC SNR ≅ 6.02 3.41 M −+ Q 30log( OSR ) Example)

SNR of VCO-based ADC

SNR of VCO-based ADC SNR ≅ 6.02 3.41 M −+ Q 30log( OSR ) Example) f

SNR

6.02

3.41

M −+

Q

SNR ≅ 6.02 3.41 M −+ Q 30log( OSR )
SNR ≅ 6.02 3.41 M −+ Q 30log( OSR )

30log(

OSR

)

Example)

f sample = 200MHz VCO Tuning Range : 50MHz~1GHz Input frequency = 5MHz ENOB = 8.48(bits)

where OSR = f /2 f sample in   f 2 π tune M
where OSR
= f
/2
f
sample
in
f
2
π
tune
M
=
log
×
Q
2
f
1
LSB () rad
sample
  
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
10
20
30
40
50
60
70
80
90
100
Frequency[MHz]
PSD[dB]
20 30 40 50 60 70 80 90 100 Frequency[MHz] PSD[dB] • Oversampling can be used

Oversampling can be used to increase the resolution.

100 Frequency[MHz] PSD[dB] • Oversampling can be used to increase the resolution. 2009-02-13 CCS Group @
100 Frequency[MHz] PSD[dB] • Oversampling can be used to increase the resolution. 2009-02-13 CCS Group @
100 Frequency[MHz] PSD[dB] • Oversampling can be used to increase the resolution. 2009-02-13 CCS Group @
Analog Input Past Work on VCO-based ADCs clk VCO Counter Digital Code Generator Digital Output

Analog

Input

Past Work on VCO-based ADCs

clk

Analog Input Past Work on VCO-based ADCs clk VCO Counter Digital Code Generator Digital Output Oversampling

VCO

Counter

Analog Input Past Work on VCO-based ADCs clk VCO Counter Digital Code Generator Digital Output Oversampling

Digital Code Analog Input Past Work on VCO-based ADCs clk VCO Counter Generator Digital Output Oversampling Clock(fos) Analog
Digital Code

Generator

on VCO-based ADCs clk VCO Counter Digital Code Generator Digital Output Oversampling Clock(fos) Analog Digital

Digital

Output

Oversampling

Clock(fos) Analog Digital input output Analog VCO Counter Integrator X(z) Y(z) -1 DAC z
Clock(fos)
Analog
Digital
input
output
Analog
VCO
Counter
Integrator
X(z)
Y(z)
-1
DAC
z
Analog VCO Counter Integrator X(z) Y(z) -1 DAC z • A. Iwata et al., “The Architecture

• A. Iwata et al., “The Architecture of Delta Sigma Analog-to-Digital Converters Using a Voltage- Controlled Oscillator as a Multibit Quantizer,” IEEE Trans. Circuits Syst. II, July 1999.

• R. Naiknaware et al., “Time-referenced single-path multi-bit ΔΣ ADC using a VCO-based quantizer,” IEEE Trans. Circuits Syst. II, July 2000.

• T.Watanabe, et al., “An All-Digital Analog-to-Digital Converter With 12-uV/LSB Using Moving-Average Filtering,” IEEE JSSC, Jan. 2003.

• J.Kim et al., “A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator”, ISCAS 2006

U. Wismar et al., “A 0.2V 0.44μW 20kHz Analog to Digital ΔΣ Modulator with 57fJ/conversion FoM,” ESSCIRC, 2006.

• Straayer et al., “A 10-bit 20MHz 38mW 950MHz CT ΔΣ ADC with a 5-bit noise-shaping VCO-based Quantizer and DEM circuit in 0.13um CMOS”, VLSI 2007.

2009-02-13
2009-02-13
a 5-bit noise-shaping VCO-based Quantizer and DEM circuit in 0.13um CMOS”, VLSI 2007. 2009-02-13 CCS Group

CCS Group @ KAIST

a 5-bit noise-shaping VCO-based Quantizer and DEM circuit in 0.13um CMOS”, VLSI 2007. 2009-02-13 CCS Group

15

Analysis of Two-Channel Time Interleaved VCO-ADC S/H VCO Counter Analog CLK1 Reset Input (CLK2) MUX

Analysis of Two-Channel Time Interleaved VCO-ADC

Analysis of Two-Channel Time Interleaved VCO-ADC S/H VCO Counter Analog CLK1 Reset Input (CLK2) MUX x(t)
S/H VCO Counter Analog CLK1 Reset Input (CLK2) MUX x(t) S/H VCO Counter CLK2
S/H
VCO
Counter
Analog
CLK1
Reset
Input
(CLK2)
MUX
x(t)
S/H
VCO
Counter
CLK2

Digital

Output

y[n]

φ

n

[]

Gxn []

v

1

2

π

(

φ

1

2

π

1

2

π

1

2

π

(

(

{

=

+

p

i

[] n

en []

)

6π e[n−2] 4π G x[n] e[n] v 2π φ[n] p n + 2] p n
e[n−2]
G x[n]
e[n]
v
φ[n]
p
n +
2]
p
n
]
i [
i [
0
G x[n+1]
e[n+1]
v
e[n−1]
φ[n+1]
p
n +
1]
i [
p
n +
3]
i [
0
n-1
n
n+1
n+2
n+3
Time (sample)

[]

yn

[] n

=

Sampling Clock

CLK1

CLK2

Analog Input

VCO Input 1

VCO Input 2

Gxn []

v

[]

n

+−

p

i

en []

)

=

Gxn []

v

en []

)

+ −−

[

en

2]

=

(

Y

()

z

GX () z

v

2

1

)

Ez ()

}

=

+− z

VCO phase 1

NTF ()z

=

z

2

1

2 1 ) Ez () } = +− z VCO phase 1 NTF () z =

VCO phase 2

2 1 ) Ez () } = +− z VCO phase 1 NTF () z =
2 1 ) Ez () } = +− z VCO phase 1 NTF () z =
SNR of the Two-channel T.I. VCO-ADC NTF () z 2 = z −= 1 −

SNR of the Two-channel T.I. VCO-ADC

NTF () z

2

= z −= 1

(

z

)(

11

1

−−

z

+

1

)

P

e

=

=

=

SNR

π

/

OSR

/

OSR

/

S

N

( )|

ω

NTF

(

2

ωω

)|

d

π

π

/

OSR

2

Sed

N

(

ω

) 4|

⋅−

1|

π

OSR

 

3

j

ω

2

ω

π

OSR

∆ 

 

4

36

π

 P



 P

f

tune

f

s

10log

S

e

6.02log

2

=

=

2

(

z

≈ 

1

2

(

z

P

=

1

S

8

 

=

4

f

s

∆=

/ 2

f tune

1

1

1

)

)

,

,

1

z

+

≈−

1

z

1 ∆⋅

2

f

tune

V

2

=

FS

8

f

tune

f

s

2

/2

1 ∆⋅

8

f

s

V

FS

(input referred quantization step)

−+ 3.41

30log

OSR

V FS (input referred quantization step) −+ 3.41 30log OSR • Increase in |NTF| is canceled

• Increase in |NTF| is canceled by the increased quantizer resolution.

30log OSR • Increase in |NTF| is canceled by the increased quantizer resolution. 2009-02-13 CCS Group
30log OSR • Increase in |NTF| is canceled by the increased quantizer resolution. 2009-02-13 CCS Group
30log OSR • Increase in |NTF| is canceled by the increased quantizer resolution. 2009-02-13 CCS Group
Proposed N t h -order ADC architecture CLK1 (f s /N) S/H VCO CLK2 (f

Proposed N th -order ADC architecture

CLK1

(f s /N)

S/H VCO
S/H
VCO

CLK2

(f s /N)

Reset

(CLK1)

CLK1 (f s /N) S/H VCO CLK2 (f s /N) Reset (CLK1) Counter Reset (CLK2) Counter
Counter
Counter

Reset

(CLK2)

S/H VCO CLK2 (f s /N) Reset (CLK1) Counter Reset (CLK2) Counter Reset (CLK3) Counter MUX
Counter
Counter

Reset

(CLK3)

Counter
Counter
(CLK1) Counter Reset (CLK2) Counter Reset (CLK3) Counter MUX S/H VCO CLK3 (f s /N) S/H
MUX

MUX

MUX
S/H VCO
S/H
VCO
Reset (CLK2) Counter Reset (CLK3) Counter MUX S/H VCO CLK3 (f s /N) S/H VCO CLKN

CLK3

(f s /N)

S/H VCO
S/H
VCO

CLKN

(f s /N)

S/H VCO
S/H
VCO

Analog

Input

x(t)

Reset

(CLKN)

CLKN (f s /N) S/H VCO Analog Input x(t) Reset (CLKN) Counter Digital Output y[n] ()
Counter
Counter

Digital

Output

y[n]

()

NTF z

N

z

Nz

1

=

≈−

1

(

1

)

,

Counter Digital Output y[n] () NTF z − N z Nz 1 = ≈− − −

z

1

Counter Digital Output y[n] () NTF z − N z Nz 1 = ≈− − −
Counter Digital Output y[n] () NTF z − N z Nz 1 = ≈− − −
Counter Digital Output y[n] () NTF z − N z Nz 1 = ≈− − −
Comparison to a Conventional ∆Σ -ADC | Q 2nd | Q N ( f )

Comparison to a Conventional ∆Σ-ADC

Comparison to a Conventional ∆Σ -ADC | Q 2nd | Q N ( f ) |
| Q 2nd | Q N ( f ) | 2nd N ( f )
| Q
2nd
| Q
N ( f ) |
2nd
N ( f ) |
4th
4th
8th
8th
16th
16th
32th
32th
0
π
0
π
TI VCO-based ADCs
TI conventional ΣΔ ADCs

• Interleaving conventional DSM results in same NTF but quantization noise increases

Constant quantization noise level with time-interleaving is a unique property of VCO-based bandpass ADC.

noise level with time-interleaving is a unique property of VCO-based bandpass ADC. 2009-02-13 CCS Group @
noise level with time-interleaving is a unique property of VCO-based bandpass ADC. 2009-02-13 CCS Group @
noise level with time-interleaving is a unique property of VCO-based bandpass ADC. 2009-02-13 CCS Group @
Behavioral Simulation Results N=4 N=128 N=2 N=16 • Bandstop noise-shaping property is shown. • Increasing

Behavioral Simulation Results

N=4 N=128
N=4
N=128

N=2

N=16

• Bandstop noise-shaping property is shown.

• Increasing the number of channels results in more available bands.

• SNR is nearly the same regardless of the number of channels.

more available bands. • SNR is nearly the same regardless of the number of channels. 2009-02-13
more available bands. • SNR is nearly the same regardless of the number of channels. 2009-02-13
Performance of the Proposed ADC architecture N = 4 f s = 2GHz 8stage VCO

Performance of the Proposed ADC architecture

Performance of the Proposed ADC architecture N = 4 f s = 2GHz 8stage VCO (16phase)
Performance of the Proposed ADC architecture N = 4 f s = 2GHz 8stage VCO (16phase)
Performance of the Proposed ADC architecture N = 4 f s = 2GHz 8stage VCO (16phase)
Performance of the Proposed ADC architecture N = 4 f s = 2GHz 8stage VCO (16phase)

N = 4

f s = 2GHz

8stage VCO (16phase) with tuning range of 100MHz - 450MHz

Ideally, more than 10bits can be achieved with less than 10MHz of bandwidth.

• Ideally, more than 10bits can be achieved with less than 10MHz of bandwidth. 2009-02-13 CCS
• Ideally, more than 10bits can be achieved with less than 10MHz of bandwidth. 2009-02-13 CCS
• Ideally, more than 10bits can be achieved with less than 10MHz of bandwidth. 2009-02-13 CCS
Practical Issues: Effect of Non-Idealities • Issues in VCO-based ADCs – Non-linearity of VCO tuning

Practical Issues: Effect of Non-Idealities

• Issues in VCO-based ADCs

– Non-linearity of VCO tuning curve

– Non-linearity of S/H circuit

– Phase noise of sampling clock

– Phase noise of VCO

– Meta-stability of flip-flops

– Backward coupling in VCO (output to input)

of flip-flops – Backward coupling in VCO (output to input) • Issues in time-interleaved ADCs –

• Issues in time-interleaved ADCs

– Mismatch between sub-ADCs

– Timing mismatch (input and clock skew)

between sub-ADCs – Timing mismatch (input and clock skew) • Issues in time-interleaved VCO-based ADCs –

• Issues in time-interleaved VCO-based ADCs

– Coupling between VCOs

clock skew) • Issues in time-interleaved VCO-based ADCs – Coupling between VCOs 2009-02-13 CCS Group @
clock skew) • Issues in time-interleaved VCO-based ADCs – Coupling between VCOs 2009-02-13 CCS Group @
Practical Issues: Non-linearity of S/H & VCO • Non-linearity results in harmonic spurious tones in

Practical Issues: Non-linearity of S/H & VCO

• Non-linearity results in harmonic spurious tones in the output.

• Harmonic spurs limit SNDR performance.

in the output. • Harmonic spurs limit SNDR performance. • Two-tone simulation with non-linearity 2009-02-13 CCS

• Two-tone simulation with non-linearity

• Harmonic spurs limit SNDR performance. • Two-tone simulation with non-linearity 2009-02-13 CCS Group @ KAIST

2009-02-13

• Harmonic spurs limit SNDR performance. • Two-tone simulation with non-linearity 2009-02-13 CCS Group @ KAIST

CCS Group @ KAIST

23

Effect of VCO Phase Noise PSD from CppSim 0 -20 -40 -60 -80 -100 -120

Effect of VCO Phase Noise

PSD from CppSim

0 -20 -40 -60 -80 -100 -120 -140 0 100 200 300 400 500 600
0
-20
-40
-60
-80
-100
-120
-140
0
100
200
300
400
500
600
700
800
900
1000
PSD [dB]

Frequency [MHz]

Ideal VCO

13 12 11 10 9 8 7 6 5 4 3 -120 -115 -110 -105
13
12
11
10
9
8
7
6
5
4
3
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
ENOB for 10MHz bandwidth [bit]

Phase noise @ 1MHz offset [dBc/Hz]

PSD from CppSim

0 -20 -40 -60 -80 -100 -120 0 100 200 300 400 500 600 700
0
-20
-40
-60
-80
-100
-120
0
100
200
300
400
500
600
700
800
900
1000
Frequency [MHz]
VCO with phase noise
PSD [dB]

Assuming power consumption of ~ 1mW, phase noise of -100dBc @ 1MHz , f osc =500MHz results in -153dB of FOM.

@ 1MHz , f o s c =500MHz results in -153dB of FOM. • Phase noise

Phase noise limits the timing accuracy and hence the resolution of the ADC.

FOM of ~ -150 is easily achievable in today’s ring oscillators.

of the ADC. • FOM of ~ -150 is easily achievable in today’s ring oscillators. 2009-02-13
of the ADC. • FOM of ~ -150 is easily achievable in today’s ring oscillators. 2009-02-13
of the ADC. • FOM of ~ -150 is easily achievable in today’s ring oscillators. 2009-02-13
Effect of Clock Jitter • < 0.1% clock jitter is required for > 10bit performance.

Effect of Clock Jitter

Effect of Clock Jitter • < 0.1% clock jitter is required for > 10bit performance. 2009-02-13

< 0.1% clock jitter is required for > 10bit performance.

of Clock Jitter • < 0.1% clock jitter is required for > 10bit performance. 2009-02-13 CCS
of Clock Jitter • < 0.1% clock jitter is required for > 10bit performance. 2009-02-13 CCS
Metastability and Coupling • Meta-stability of flip-flops – Not an issue if the resolution of

Metastability and Coupling

• Meta-stability of flip-flops

Metastability and Coupling • Meta-stability of flip-flops – Not an issue if the resolution of flip-flops

– Not an issue if the resolution of flip-flops is better than the time-resolution of VCOs.

– Also first-order shaped.

Backward coupling in VCOthe time-resolution of VCOs. – Also first-order shaped. – VCO output can corrupt its input. –

– VCO output can corrupt its input.

– Effect can be minimized if its tuning range of the VCO does not overlap with the input frequency range.

if its tuning range of the VCO does not overlap with the input frequency range. 2009-02-13
if its tuning range of the VCO does not overlap with the input frequency range. 2009-02-13
if its tuning range of the VCO does not overlap with the input frequency range. 2009-02-13
Practical Issues : Mismatch between sub-ADCs • Mismatch between sub-ADCs – One of the performance

Practical Issues : Mismatch between sub-ADCs

• Mismatch between sub-ADCs

: Mismatch between sub-ADCs • Mismatch between sub-ADCs – One of the performance bottleneck in time-interleaved

– One of the performance bottleneck in time-interleaved ADCs

– Simulated by giving random mismatch in the tuning curves of the VCOs

by giving random mismatch in the tuning curves of the VCOs • ENOB degradation due to

• ENOB degradation due to mismatch e.g.) 60dB 50dB with 1% mismatch

2009-02-13
2009-02-13
of the VCOs • ENOB degradation due to mismatch e.g.) 60dB  50dB with 1% mismatch

CCS Group @ KAIST

of the VCOs • ENOB degradation due to mismatch e.g.) 60dB  50dB with 1% mismatch

27

Conclusions • Time-interleaved VCO-based ADCs exploiting time-based signal processing has been introduced. – RF

Conclusions

• Time-interleaved VCO-based ADCs exploiting time-based signal processing has been introduced.

– RF signals can be digitized in an energy & area efficient manner.

• Limitations of the proposed ADC include

– Timing mismatch, non-linearity, supply noise, phase noise, etc.

– Performance can improved with better measurement layout, measurement setup and already established calibration techniques.

• Time-based signal processing will become increasingly more prevalent in the future

• Time-based signal processing will become increasingly more prevalent in the future 2009-02-13 CCS Group @
• Time-based signal processing will become increasingly more prevalent in the future 2009-02-13 CCS Group @
[1] References R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for

[1]

References

R. B. Staszewski et al., “All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS”, IEEE J. Solid-State Circuits, vol. 39, pp. 2278-2291, Dec

2004.

J. Solid-State Circuits, vol. 39, pp. 2278-2291, Dec 2004. [2] A. Iwata, N. Sakimura, M. Nagata,

[2] A. Iwata, N. Sakimura, M. Nagata, and T. Morie, “The architecture of delta sigma analog-to- digital converters using a voltage-controlled oscillator as a multibit quan-tizer," IEEE Trans. Circuits Syst. II, vol. 46, pp. 941-945, July 1999.

[3]

Y-.G. Yoon et al., “A time-based bandpass ADC using time-interleaved voltage-controlled

[4]

oscillators,” IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3571-3581, Dec 2008 Y.-C. Jenq, “Digital spectra of nonuniformly sampled signals : Fundamentals and high-speed

[5]

waveform digitizers," IEEE Trans. Instrum. Meas., vol. 37, pp. 245-251, June 1988. J. Lee and B. Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control,"

[6]

IEEE J. Solid-State Circuits, vol. 35, pp. 1136-1145, Aug. 2000. H. Wang, "A 1.8V 3mW 16.8GHz frequency divider in 0.25um CMOS," in IEEE Int. Solid-State

[7]

Circuits Conference, Digest of Technical Papers, 2000. T. Chalvatzis et al., “A low-noise 40-GS/s continuous-time bandpass ADC centered at 2 GHz

[8]

for direct sampling receivers,” IEEE J. Solid-State Circuits, vol. 42, pp. 1065-1075, May 2007. B. K. Thandri and J. S. Martinez, “A 63dB SNR, 75-mW bandpass RF ADC at 950MHz using

[9]

3.8-GHz clock in 0.25-um SiGe BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 42, pp. 269-279, Feb 2007. J. Rychaert et al., "A 2.4GHz 40mW 40dB SNDR/62dB SFDR 60MHz bandwidth mirrored- image RF bandpass ΣΔ ADC in 90nm CMOS," in Proc. of Asian Solid-State Circuits Conference.

ΣΔ ADC in 90nm CMOS," in Proc. of Asian Solid-State Circuits Conference. 29/44 2009-02-13 CCS Group
ΣΔ ADC in 90nm CMOS," in Proc. of Asian Solid-State Circuits Conference. 29/44 2009-02-13 CCS Group
ΣΔ ADC in 90nm CMOS," in Proc. of Asian Solid-State Circuits Conference. 29/44 2009-02-13 CCS Group
Communication Circuits & Systems (CCS) Group
Communication Circuits & Systems (CCS) Group

2005.3~ , 13 students

Research area of interest

PLL : Low-noise low-power frequency synthesis, clock generation & building blocks for wireless applications

ADC: Reconfigurable, ADCs for software radios

Bio-medical circuits: Health care and neuro-science

ADCs for software radios – Bio-medical circuits: Health care and neuro-science 2009-02-13 CCS Group @ KAIST
ADCs for software radios – Bio-medical circuits: Health care and neuro-science 2009-02-13 CCS Group @ KAIST
ADCs for software radios – Bio-medical circuits: Health care and neuro-science 2009-02-13 CCS Group @ KAIST
Wireless Transceivers & PLLs • PLL-based transmitter for non-continuous modulation. [Lee, IEEE TCAS2007] • 800uW

Wireless Transceivers & PLLs

Wireless Transceivers & PLLs • PLL-based transmitter for non-continuous modulation. [Lee, IEEE TCAS2007] • 800uW

• PLL-based transmitter for non-continuous modulation. [Lee, IEEE TCAS2007]

• 800uW charge recycling frequency synthesizer [Park, VLSI08]

• Low-jitter PLL with fast & accurate frequency calibration. [Lee, A-SSCC07]

• Low-noise all digital PLLs

D I (t) Frequency Synthesizer Base π/2 Band D Q (t) Frequency Synthesizer
D
I (t)
Frequency
Synthesizer
Base
π/2
Band
D
Q (t)
Frequency
Synthesizer

[Lee, IEEE TCAS2, ‘07]

D Q (t) Frequency Synthesizer [Lee, IEEE TCAS2, ‘07] 2.4~2.5-GHz output Charge recycling path Signal
2.4~2.5-GHz output Charge recycling path Signal Programmable Divide-by-2 DSM K<14:0> divider Vmid
2.4~2.5-GHz output
Charge recycling path
Signal
Programmable
Divide-by-2
DSM
K<14:0>
divider
Vmid
Decoupling
capacitor
Level
Shifter
PFD
REF

External loop filter

[Park, Symp. on VLSI ‘08]

PFD REF External loop filter [Park, Symp. on VLSI ‘08]   JSSC JSSC This 04 07
 

JSSC

JSSC

This

04

07

work

Optimality

X

 

X

O

Test

Cal Time

12.6

us

4 us

350 ns

Cycles to Calibrate 2 n Curves

20.5

· n

5 · 2 n

n+2

[Lee, A-SSCC 07]

20.5 · n 5 · 2 n n+2 [ L e e , A - S
20.5 · n 5 · 2 n n+2 [ L e e , A - S
20.5 · n 5 · 2 n n+2 [ L e e , A - S
Building Blocks for PLLs: PVT Immune VCOs • VCO with wide tuning range & immunity

Building Blocks for PLLs: PVT Immune VCOs

Building Blocks for PLLs: PVT Immune VCOs • VCO with wide tuning range & immunity to

• VCO with wide tuning range & immunity to PVT variations [Park, IEEE MTT08]

• Design techniques for robust low-voltage VCOs [Park, IEEE MTT09]

• Charge-recycling VCO & prescaler [Park, IEEE MWCL08]

V DD V out_n V out_p V DD_dig Voltage V out_n Boosting V out_p Circuit
V DD
V out_n
V out_p
V DD_dig
Voltage
V out_n
Boosting
V out_p
Circuit
V DD_dig
V DD_dig
b
off
V
out_n
V out_p
Amplitude
Detector
V
b
V
out_n
V out_p
V b
V out_p Amplitude Detector V b V out_n V out_p V b [Park, ESSCIRC06, IEEE MTT09,
V out_p Amplitude Detector V b V out_n V out_p V b [Park, ESSCIRC06, IEEE MTT09,

[Park, ESSCIRC06, IEEE MTT09, IEEE MWCL09]

 

JSSC 2005

This work

Tech

0. 18-um

0. 18-um

Frequency

3.8 GHz

2.41 GHz

Tuning

3 %

20 %

Range

Supply

0.5 V

0.5 V

0.43 V

Phase Noise

     

@ 1-MHz

-119

-117.3

-115.6

FoM

-193

-190

-191

FoMT

-182.5

-196

-197

Area

0.23 mm 2

0.31 mm 2

-190 -191 FoM T -182.5 -196 -197 Area 0.23 mm 2 0.31 mm 2 2009-02-13 CCS
-190 -191 FoM T -182.5 -196 -197 Area 0.23 mm 2 0.31 mm 2 2009-02-13 CCS
-190 -191 FoM T -182.5 -196 -197 Area 0.23 mm 2 0.31 mm 2 2009-02-13 CCS

Building Blocks for PLLs: Low Noise VCOs • Low-noise VCO using parasitic V-NPN [Ku, IEEE MTT06] • Optimum current mirror ratio for

• Low-noise VCO using parasitic V-NPN [Ku, IEEE MTT06]

• Optimum current mirror ratio for VCOs [Park, IEEE MTT09]

Optimum current mirror ratio for VCOs [Park, IEEE MTT09] V-NPN C E B E C N+
Optimum current mirror ratio for VCOs [Park, IEEE MTT09] V-NPN C E B E C N+

V-NPN

C E B E C N+ N+ P+ N+ N+ N-Well P-Well N-Well Deep N-Well
C
E
B
E
C
N+
N+
P+
N+
N+
N-Well
P-Well
N-Well
Deep N-Well

P-Substrate

P+ N+ N+ N-Well P-Well N-Well Deep N-Well P-Substrate Vc [Ku, IEEE MTT06] [Ku, IEEE MWCL08]
Vc
Vc
N+ N+ N-Well P-Well N-Well Deep N-Well P-Substrate Vc [Ku, IEEE MTT06] [Ku, IEEE MWCL08] 2009-02-13

[Ku, IEEE MTT06]

[Ku, IEEE MWCL08]

N-Well P-Well N-Well Deep N-Well P-Substrate Vc [Ku, IEEE MTT06] [Ku, IEEE MWCL08] 2009-02-13 CCS Group
N-Well P-Well N-Well Deep N-Well P-Substrate Vc [Ku, IEEE MTT06] [Ku, IEEE MWCL08] 2009-02-13 CCS Group

Building Blocks for PLLs: VCO, Divider & DCOs

Building Blocks for PLLs: VCO, Divider & DCOs • Multi-modulus injection locked frequency divider [Lee, A-SSCC07]
Building Blocks for PLLs: VCO, Divider & DCOs • Multi-modulus injection locked frequency divider [Lee, A-SSCC07]

• Multi-modulus injection locked frequency divider [Lee, A-SSCC07]

• High resolution DCO using complimentary varactors [Han, EL08]

• Self-noise canceling VCO [Cho, EL08]

Output D 1 D 2 D 3 D 4 D 2n D 2n+1 A B
Output
D 1
D 2
D 3
D 4
D 2n
D 2n+1
A
B
Programmable
D
0
M
1
delay cells

Input

[Lee, A-SSCC07]

Programmable D 0 M 1 delay cells Input [Lee, A-SSCC07] Δ C proposed = Δ C
Programmable D 0 M 1 delay cells Input [Lee, A-SSCC07] Δ C proposed = Δ C

Δ C proposed = Δ C NMOS Δ C PMOS

[Han, EL08]

PD

D φ I CP R VCDL C φ 0 D I CP v D ctrl
D
φ
I
CP
R
VCDL
C
φ
0
D
I
CP
v
D
ctrl
PMOS [Han, EL08] PD D φ I CP R VCDL C φ 0 D I CP

[Cho, EL08]

PMOS [Han, EL08] PD D φ I CP R VCDL C φ 0 D I CP
PMOS [Han, EL08] PD D φ I CP R VCDL C φ 0 D I CP
PMOS [Han, EL08] PD D φ I CP R VCDL C φ 0 D I CP