STATIC LOGIC CMOS Introduction

TRANSISTOR

BJT

MOSFET

NPN

PNP

NMOS

PMOS

BJT and MOSFET transistor

BJT Vs MOSFET Comparison BJT (Bipolar Junction Transistor) MOSFET (Metal Oxide Silicon Field Effect Transistor)

Symbol

Construction

Basic principle

Current operate -low i/p impedance -small i/p time constant (high speed) -large power consumption

Voltage operate -high i/p impedance -large time constant (dynamic logic) -small power consumption

Fabrication

Vertical structure -isolation -low packing density -large mask count

Horizontal structure -no isolation -high packing density -small mask count Flexible switch device -in/out separation -bidirectional -controllable VT -n/p channel

Design

Devices that needed to amplify a signal -BCE cannot change place

Example 1 Vdd

i/p

o/p

Transformation inverter to cmos circuit

Vss

1st Method Step 1 Identify 2n = X 21 = 2 Step 2 Built t.t (truth table) for it. A 0 1 Step 3 Then put the output from t.t into k.map(karnaugh map) Note: Dont forget to label all boxes with numbering. The reason why, it is because to make easy to put output from t.t into k.map boxes as reference. -Sketch 2 boxes for k.map to simplify the 2 output from t.t -do a loop for each different output **Remember pmos is good for 1 nmos is good for 0 st - 1 loop is around 1 and read as A and it is belongs to pmos expressionbut - 2nd loop is around 0 and read as A and it is belongs to nmos expression F 1 0 Note: in t.t we can see there are two logic input are used to test the output. As a result the output will invert both of it. -0 input become 1 after tested also -1 input become 0 after tested Note : n=input x=output

A 1
0

A 0
1

A - pmos

A - nmos

Step 4 Write the expression of : Pmos = A -- F = 1 Nmos = A -- F = 0 Step 5 Draw a cmos circuit Vdd PMOS Pull-up A F NMOS Pull-down Vss Note :**Remember pmos transistor must draw at above and nmos transistor draw at the bottom. Note: Look at back to the expression has been produced. - Draw the cmos circuit with complete labeling with Vdd,Vss, input and output. **Remember If the expression with + arrange the transistor in parallel, If the expression with . arrange the transistor in series.

2nd Method Step 1 Identify the output from the logic gate F=A Step 2 0F = A - natural (nmos) =A 1 F = A demorgan (pmos) Step 3 Write the expression of : Pmos = A -- F = 1 Nmos = A -- F = 0 Step 4 Draw a cmos circuit Vdd Note :**Remember pmos transistor must draw at above and nmos transistor draw at the bottom. Note: Look at back to the expression has been produced. -Draw the cmos circuit with complete labeling with Vdd,Vss, input and output. F **Remember If the expression with + arrange the transistor in parallel, If the expression with . arrange the transistor in series. Note: **Remember pmos is good for 1 nmos is good for 0 Note: Get the output equation F from the logic gate

Vss

Exercises 1. 2. 3. 4. Transform Nand gate with 2 input to cmos circuit using method 1 and 2 Transform Nor gate with 2 input to cmos circuit using method 1 and 2 Transform Nand gate with 3input to cmos circuit using method 1 and 2 Transform Nand gate with 3 input to cmos circuit using method 1 and 2

Example 2 Vdd Vdd X D X D Vss Vss Step 1 cmos circuit Vdd G A G D Vss Step 2 Draw an eular path Vdd D A S S D Vss Step 3 Draw a stick diagram Vdd X D X D Vss A X S X S Note: 1. Draw 2 vertical line first line as pmos and the second one as nmos 2. Draw 1 horizontal line as an input of A. 3. Label up with D S follows the euler path that has been sketch inside the cmos circuit. 4. Then plot the contact at each legs of transistor. 5. Draw a connection through the Vdd, pmos, nmos and output F Note: eular path is sketch to get know the current flow from vdd through vss. D S S F Transformation cmos circuit to stick diagram Note: From cmos circuit label up the G D S for every part at the transistor pmos and nmos. Make sure the sequences of labeling are repeated. A X S X S

i/p

o/p

Exercises 1. 2. 3. 4. Transform cmos circuit for Nand gate with 2 input into stick diagram Transform cmos circuit for Nor gate with 2 input into stick diagram Transform cmos circuit for Nand gate with 3 input into stick diagram Transform cmos circuit for Nand gate with 3 input into stick diagram Vdd Example 3 Vdd X D X D Vss A X S X S Transformation stick diagram to layout

F i/p o/p

Vss Step 1 Stick diagram Vdd X D X D Vss Step 2 PMOS Vdd A X S X S Note: PMOS part i. Draw an Nwell as a outbox ii. Draw Pselect (top) & Nsel ect (bottom) as beside iii. Draw an Active iv. Draw contact as 2x2 square v. Draw a Metal 1 as connection to Vdd and overlap it with 2 contact **Remember now contacts become 3 because 2 contacts for transistor and another one for vdd. Note: From stick diagram transform it into layout by sketches it part by part. i. PMOS ii. NMOS F

Step 3

NMOS

Note: NMOS part i. Draw Pselect (top) & Nsel ect (bottom) as beside ii. Draw an Active iii. Draw contact as 2x2 square iv. Draw a Metal 1 as connection to vss overlap it with 2 contact Vss **Remember in this part there is no NWell is used. For contacts also same as PMOS 2 contacts for transistor and another one for vss. Note: now combine the part of PMOS (top) and NMos (bottom) to create a CMOS layout.

Step 4

Combine PMOS and NMOS Vdd

Vss Step 5 CMOS Layout Vdd

i/p

o/p

Note: Draw combination part with: i. Polysilicon start at edge of NWell through the edge of pselect. Extend the polysilicon at center and label up as input. ii. Metal 1 including contact at pmos till contact at nmos. Extend the metal 1 at center and label up as output.

Vss

Exercises 1. 2. 3. 4. Transform stick diagram for Nand gate with 2 input into layout Transform stick diagram for Nor gate with 2 input into layout Transform stick diagram for Nand gate with 3 input into layout Transform stick diagram for Nand gate with 3 input into layout