Notes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - P rof.

Diana Marculescu, UMD Lecture 1 Digital VLSI Design Laboratory Instructor: Prof. Diana Marculescu Fall 1999 Fall 1999

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD

Why VLSI? Moore s Law. The VLSI design process. The VLSI design process. Overview

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Why VLSI? Integration improves the design: lower parasitics = higher speed; lower power; lower power; physically smaller. Integration reduces manufacturing cost (almost) no manual assembly.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD

Microprocessors: personal computers; microcontrollers. microcontrollers. DRAM/SRAM. VLSI and you

Special-purpose processors.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Moore s Law Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD The cost of fabrication Current cost: about $1 billion. Typical fab line occupies about 1 city block, employs a few hundred people.

employs a few hundred people. Most profitable period is first 18 months-2 years. Currently > 15 new fab lines coming on line worldwide. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Cost factors in ICs For large-volume ICs: packaging is largest cost; testing is second-largest cost. testing is second-largest cost. For low-volume ICs, design costs may swamp all manufacturing costs.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD The VLSI design process May be part of larger product design. Major steps: specification; specification; architecture; logic design; circuit design; layout. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD The steps Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Hierarchical design Divide-and-conquer: divide into smaller pieces recursively subdivide recursively subdivide Module = interface + implementation.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Hierarchical design example

Full-add add32 ...

Xor

Carry-in Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Hierarchical VLSI design VLSI components are harder to abstract: physical size/shape overlapping geometry overlapping geometry electrical parameters initialization In some ways, VLSI components are easier

to abstract: well-defined behavior Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Design validation Must check at every step that errors haven t been introduced-the longer an error remains, the more expensive it becomes to remove it. the more expensive it becomes to remove it. Forward checking: compare results of less and more-abstract stages. Back annotation: copy performance numbers to earlier stages. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD The design process spec behavior RT function cost logic circuit layout Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Challenges in VLSI design Good layout design is an essential factor in success. Circuit behavior cannot be ignored: Circuit behavior cannot be ignored: delay power crosstalk Logic, circuit, and layout design all interact.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRChallenges in VLSI design, cont d Notes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - P rof. Diana Marculescu, UMD

Floorplan mis-predictions can have major design consequences. Interesting chips are very large. Interesting chips are very large. Pinout is a major restriction.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Manufacturing test Not the same as design validation: just because the design is right doesn t mean that every chip coming off the line will be that every chip coming off the line will be right. Must quickly check whether manufacturing defects destroy function of chip. Must also speed-grade. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD

Basic fabrication steps Transistor structures

Basic transistor behavior Basic transistor behavior Topics

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Fabrication services Educational services: U.S.: MOSIS EC: EuroPractice EC: EuroPractice Taiwan: CIC Japan: VDEC Foundry = fabrication line for hire.

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD l-based design is the size of a minimum feature. Specifying particularizes the scalable rules. rules. Parasitics are generally not specified in units In our 0.5 micron process, l = 0.25 microns. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Fabrication processes IC built on silicon substrate: some structures diffused into substrate; other structures built on top of substrate. other structures built on top of substrate. Substrate regions are doped with n-type and

p-type impurities. (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). Silicon dioxide (SiO 2 ) is insulator. Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Photolithography Mask patterns are put on wafer using photo sensitive material:

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub n-tub substrate

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Process steps, cont d. Pattern polysilicon before diffusion regions: poly poly gate oxide p-tub n-tub

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Process steps, cont d Add diffusions, performing self-masking: poly poly n+n+ p+ p+ p-tub n-tub

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Process steps, cont d Start adding metal layers: metal 1 metal 1 vias poly poly n+n+ p+ p+ p-tub n-tub

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD

n-type transistor: Transistor structure

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTRNotes courtesy of Prof. Wayne Wolf, Princeton University ENEE459Y, Fall 1999 - Prof. Diana Marculescu, UMD Transistor layout n-type (tubs may vary): L L w

Modern VLSI Design 2e: Lecture 1 Copyright 1998 Prentice Hall PTR